Minimization Of Chip Area Research Articles

MFMW: Modified Floor planning with Minimum Wire length

Floorplanning is one of the most critical phases inVLSI circuit design. The module alignment has a substantial concentration on the minimization of chip area and total wirelength in slicing floorplan. At foremost, the disadvantages of dead space are investigated and an instinctive and profligate method is proposed to find the equitable part of component. Then, a tormenting for standardized expression is improved to produce new solution, and the proposed simulated annealing algorithm which improves design efficiency is opted for the best floorplan solution. The proposed MFMW method attains less area on the commonly used AMI33 and AMI 49 benchmark circuits.

Chip Area Minimization with Voltage-Island and Fixed-Outline Constraints Using Dual Level Meta-Heuristic Optimization Algorithms

Chip Area Minimization with Voltage-Island and Fixed-Outline Constraints Using Dual Level Meta-Heuristic Optimization Algorithms

A Genetic Approach to Standard Cell placement using Various Genetic Operators

Genetic algorithm (GA) is a powerful optimization algorithm, which starts with an initial set of random configurations and uses a process similar to biological evolution to improve upon them [1]. As we know that there is a progression towards miniaturization. This paper describes the Genetic Algorithm for standard cell placement on a VLSI Chip for minimization of chip area. Unlike the other placement algorithms that apply transformations on the physical layout, the genetic algorithm applies transformations on the chromosomal representation of the physical layout.

Effectiveness of an evolutionary algorithm for the multi‐objective rectangular packing problem

AbstractThis paper considers the rectangular packing problem and investigates the effectiveness of the neighborhood cultivation genetic algorithm (NCGA). NCGA, which we proposed, is a new algorithm in which the unique mechanism of neighborhood crossover is combined with effective mechanisms for search in multi‐objective GA proposed in the past. The effectiveness of the proposed method in typical test problems has already been investigated with satisfactory results in past studies. The rectangular packing problem, on the other hand, is applied to floor planning, such as chip area minimization in large‐scale integrated circuits. It is a kind of discrete combinatorial problem in which it is known that the search is difficult and a very long time is required until the solution is obtained. This paper formulates the rectangular packing problem as a multi‐objective problem with the vertical and horizontal lengths of the placement configuration as the objectives. The sequence‐pair is used as the block placement representation, and PPEX is used as the crossover procedure. Using these processes, the effectiveness of NCGA is investigated. For comparison, three other methods—NSGA‐II, SPEA2, and non‐NCGA (NCGA without neighborhood crossover)—are investigated. © 2007 Wiley Periodicals, Inc. Electron Comm Jpn Pt 2, 90(12): 111–120, 2007; Published online in Wiley InterScience (www.interscience.wiley.com). DOI 10.1002/ecjb.20427

A theoretical design basis for minimizing CMOS fixed taper buffer area

This paper develops a theoretical basis for the minimization of chip area required for fixed taper buffer design. It modifies the well-known procedure for minimizing delay time in such circuits to derive a minimum number of required stages. Rather than minimize delay time, the procedure realizes a specified buffer delay time using a stage-area scale factor that minimizes the total area of the buffer. Since an integer number of tapered stages must be used while the calculations lead to noninteger results, the effects of roundoff errors are included.

A Sea-of-Gates Style FPGA Placement Algorithm

Field Programmable Gate Arrays (FPGAs) have a pre-defined chip boundary with fixed cell locations and routing resources. Placement objectives for flexible architectures (e.g., the standard cell design style) such as minimization of chip area do not reflect the primary placement goals for FPGAs. For FPGAs, the layout tools must seek 100% routability within the architectural constraints. Routability and congestion estimates must be made directly based on the demand and availability of routing resources for detailed routing of the particular FPGA. We. present a hierarchical placement approach consisting of two phases: a global placement phase followed by a detailed placement phase. The global placement phase minimizes congestion estimates of the global routing regions and satisfies all constraints at a coarser level. The detailed placer seeks to maximize the routability of the FPGA by considering factors which cause congestion at the detailed routing level and to precisely satisfy all of the constraints. Despite having limited knowledge about the gate level architectural details, we have achieved a 90%reduction in the number of unrouted nets in comparison to an industrial tool (the only other tool) developed specifically for this architecture.

Design of GaAs operational amplifiers for analog sampled data applications

High-grain operational amplifiers for implementation in GaAs technology are an essential component for analog GaAs signal processing systems using switched-capacitor circuit techniques. The requirement for high voltage gains and fast settling times in the context of the inherent technological disadvantages of GaAs (MESFET) devices leads to the development of a whole range of novel circuit techniques. For optimum performance, single-stage designs with single-ended input are considered initially. A description is given of a differential-to-single-ended converter stage that can be combined with these high gain stages to yield differential input amplifiers. A new procedure for characterizing amplifiers in terms of settling time is presented. It reveals the ultimate speed limitation for a given amplifier design and allows the MESFET gatewidths to be scaled in order to obtain optimum settling behavior for any given capacitive load. Ideas are pursued for a new generation of amplifiers with very fast settling times approaching 200 ps, intended for future switched-capacitor systems with 1-GHz switching frequencies. Considerable emphasis is placed throughout on the minimization of chip area and power consumption. The application of one of the amplifier designs in an integrated switched capacitor filter chip is presented, along with encouraging preliminary measurement.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>