A theoretical design basis for minimizing CMOS fixed taper buffer area

Abstract

This paper develops a theoretical basis for the minimization of chip area required for fixed taper buffer design. It modifies the well-known procedure for minimizing delay time in such circuits to derive a minimum number of required stages. Rather than minimize delay time, the procedure realizes a specified buffer delay time using a stage-area scale factor that minimizes the total area of the buffer. Since an integer number of tapered stages must be used while the calculations lead to noninteger results, the effects of roundoff errors are included.