MIMD Architectures Research Articles

Parallel implementation of a particle simulation for modeling rarefied gas dynamic flow

When the conditions of flow are rarefied and hypersonic, a more suitable alternative to the use of the Navier-Stokes equations for developing a numerical solution is the Direct Simulation Monte Carlo method (DSMC), a method of simulation which employs a large number of particles in modeling a rarefied gas. The performance of a parallel DSMC code developed for the Intel iPSC/860 Touchstone Gamma prototype computer is studied and the scaleup is found to be very nearly linear over the range of 16–128 processors. When using 128 processors the absolute performance is found to be 0.6 μs particle −1 time step −1, as compared with 2.0 and 1.0 μs particle −1 time step −1 for single processor runs on the CRAY-2 and CRAY-YMP, respectively. A high degree of compatibility is found between the spatial decomposition of a particle method and the resulting mapping onto a MIMD architecture.

An efficient distributed thinning algorithm

We present a detailed solution for the problem of computing a skeleton of a digital image by a distributed system. The proposed algorithm uses domain decomposition of the image to be thinned rather than computing one pixel per processor. We will show that the rectangular tesselation with 4-subfields technique is especially appropriate for the distributed thinning. The theoretical model as well as a distributed implementation on a distributed memory MIMD architecture are presented.

Parallel Gram-Schmidt orthogonalisation on a network of transputers

A parallel algorithm to perform modified Gram-Schmidt orthogonalisation of a set of vectors using an MIMD architecture is described. An array of transputers configured in a simple pipeline topology is used for the computation. The speedup obtained by using P processors asymptotically approaches P/2 when the size of the problem becomes large.

Microprocessor architectures and systems: RISC, CISC and DSP

Part 1 Complex instruction set computers: enter the MC68000 complex instructions, Microcode and Nanocode the MC68000 hardware M68000 asynchronousbus M6800 synchronousbus the user/supervisor concept the MC68010 virtual memory processor MC68010 supervisor resource the MC68008. Part 2 32-bit CISC processors: enter HCMOS technology the MC68020 32-bit performance standard coprocessor interface MC68881 and MC68882 floating point coprocessors the MC68851 paged memory management unit (PMMU) the MC68030, the first commercial 50 MHz. Part 3 The rise challenge: the 80/20 rule the initial RISC research the Berkeley model the Stanford model the catalysts the M88000 family the MC88100 programming model the MC88100 instruction set MC88100 external functions M88200 cache MMU the MBUS protocol M88000 master/checker fault tolerance. Part 4 Digital signal processing: the DSP56000 family move commands. Part 5 Memory, memory management and caches: shadow RAM DRAM v SRAM optimizing the DRAM interface memory management multitasking and user/supervisor conflicts. Part 6 Real time software interrupts and exceptions: interrupting an MC88100 MC88100 interrupt service routines interrupting the DSP56000 triadic instruction sets register windowing the M68300 family. Part 7 Multiprocessing: SISD - single instruction, single data SIMD - single instruction, multiple data MIMD - multiple instruction, multiple data MISD - multiple instruction, single data constructing a MIMD architecture processor bandwidths. Part 8 Application ideas: MC68020 and MC68030 design techniques for high-reliability applications transparent update techniques for digital filters using the DSP56000 motor and servo control. Part 9 Semiconductor technology: semiconductor technology silicon technology CMOS and bipolar technology. Part 10 The changing design cycle: the changing design cycle the shortening design cycle simulation v emulation. Part 11 Generation: enter the MC68040 the instruction execution unit the bus interface unit the M68300 family DSP96000 combining integration and performance once a new approach to emulation integration and higher performance. Part 12 Selecting a microprocessor architecture: meeting performance needs development support considering all the options. Appendices: benchmarking binary compatibility standards.

Stochastic Ray Tracing Using SIMD Processor Arrays

Stochastic ray tracing is one of the most elegant methods for anti-aliasing and for generating such phenomena as soft shadows, fuzzy reflections, depth of field, and motion blur, which are difficult to accomplish with the conventional ray-tracing algorithm. Unfortunately, it makes use of stochastic sampling, which requires more than one sample for each pixel. One possible way to speed up ray tracing is to explore the inherent parallelism of the algorithm. In the past few years, the major focus of parallel ray-tracing research has been on the use of MIMD architectures. Although SIMD architectures may be ideal for ray tracing simple scenes, they have been thought unsuitable for ray tracing complex scenes. However, by using scene coherence, we have found that stochastic ray tracing using SIMD processor arrays can be as efficient as most of the existing MIMD ray-tracing algorithms and more cost effective.

Transputers-past, present and future

The progress, products, and results of ongoing work in transputer development are discussed with particular reference to the ESPRIT Supernode project and other ESPRIT projects. The Supernode project, which lasted from Dec. 1985 to Nov. 1989, was aimed to create a low-cost, high-performance computer system from transputers and incorporated the development of the T800 floating-point transputer and the Supernode RTP (Reconfigurable Transputer Processor). The three-year GPMIMD (General-Purpose, Multiple-Instruction, MUltiple-Data) project aims to develop a standard European MIMD architecture based on H1 transputers and virtual communications. The OMI MAP (Open Microsystems Initiative Microprocessor Architecture Project) forms the core of the European-led Open Microsystems Initiative. It aims to define the architecture of a new microprocessor family designed to exploit the VLSI capabilities anticipated in the latter half of the 1990s. >

Load balancing and Poisson equation in a graph

AbstractWe present a fully distributed dynamic load balancing algorithm for parallel MIMD architectures. The algorithm can be described as a system of identical parallel processes, each running on a processor of an arbitrary interconnected network of processors. We show that the algorithm can be interpreted as a Poisson (heath) equation in a graph. This equation is analysed using Markov chain techniques and is proved to converge in polynomial time resulting in a global load balance. We also discuss some important parallel architectures and interconnection schemes such as linear processor arrays, tori, hypercubes, etc. Finally we present two applications where the algorithm has been successfully embedded (process mapping and molecular dynamic simulation).

A parallel algorithm for global optimization

A parallel global optimization algorithm based on the density clustering technique by Boendeb is described. Two versions, the synchronous and the asynchronous one, are proposed and numerical experiments are carried out using a simulation environment of a parallel MIMD machine. A comparison between the sequential and parallel versions of the algorithm, both in term of time and of number of function evaluations, shows that the asynchronous one is very promising for machines based on MIMD architecture

Assessment of reconfiguring algorithms for MIMD architectures

Some issues of reconfigurable computing systems with MIMD architecture are considered. A number of reconfiguring algorithms are analyzed by simulation from the aspect of the attainable fault tolerance.

Domain decomposition on parallel computers

We consider the application of domain decomposition techniques to the solution of sparse linear systems arising from implicit PDE discretizations on parallel computers. Representatives of two popular MIMD architectures, message passing (the Intel iPSC/2-SX) and shared memory (the Encore Multimax 320), are employed. We run the same numerical experiments on each, namely stripwise and boxwise decompositions of the unit square, using up to 64 subdomains and containing up to 64K degrees of freedom. We produce a tight-fitting complexity model for the former and discuss the difficulty of doing so for the latter. We also evaluate which of three types of domain decomposition preconditioners that have appeared in the literature of self-adjoint elliptic problems are most efficient in different regions of machine-problem parameter space. Some form of global sharing of information in the preconditioner is required for efficient overall parallel implementation in the region of most practical interest (large problem sizes and large numbers of processors); otherwise, an increasing iteration count inveighs against the gains of concurrency. Our results on a per iteration basis also hold for sparse discrete systems arising from other types of partial differential equations, but in the absence of a theory for the dependence of the convergence rate upon the granularity of the decomposition, the overall results are only suggestive for more general systems.

Microprogramming instruction systolic arrays

The instruction systolic array (ISA) is a programmable parallel architecture suitable for VLSI implementation. This paper presents a generalization of the ISA, called the microprogrammed ISA, which uses simple microprogramming techniques. Microprogrammed ISAs use dynamic microcodes whose length and contents are tailor made to the current program to be executed, and this can be efficiently implemented in VLSI. Here, microprogramming has the novel advantage of extending the range of algorithms that can be implemented on a given ISA. In particular, microprogramming can extend an ISA's effective communication abilities. Also, the reduction of the program input bandwidth (and pinout) afforded by microprogramming is even more important on large-scale MIMD architectures, such as the ISA. This paper also presents a weakest precondition semantics for the (microprogrammed) ISA model, which provides a means for verifying microprogrammed ISA programs. The semantics is modeled at the micro level, and has potential in the optimization of the microcodes of ISA programs.

Synchronised execution on shared memory multiprocessors

Threads provides a mechanism for simulating the execution of parallel algorithms on a simplified model of a shared-memory multiprocessor. The algorithms can be expressed in a high-level block-structured language, which supports multiple threads of execution within a common body of program code. Results show an ability to achieve good speedup for small problems using algorithms derived by simple modifications of sequential algorithms. As well, a sibling thread synchronisation feature provides the basis for the synchronous execution of threads. k-parallel algorithms tailored to the machine size and implemented as synchronously executing iterations, can provide near linear speedup as the problem size is increased. The techniques described in this paper seem to promise an effective synchronous execution mode for shared-memory MIMD architectures.

Evaluating parallel processors for real-time applications

Increasing acceptance of the necessity for high-order parallelism in order to progress digital processing still leaves open the large question of what machine architectures are best for which class of problem. To help answer this, we are investigating and comparing the use of both SIMD and MIMD architectures for programmable processing in real-time systems. A distributed array machine, Mil-DAP (derived from the original ICL DAP) has been developed and benchmarked on radar, image processing, and on terrain modelling problems. Multi-transputer arrays have been applied to an overlapping set of problems in image processing, FFT and terrain-based computation. The results are compared and preliminary conclusions drawn.

A parallelization of adaptive task partitioning algorithms

An adaptive task partitioning scheme for MIMD architectures is investigated. For many serial adaptive procedures this methodology provides a direct translation into reasonably efficient parallel versions. A proto-type of a two-dimensional integration method has been implemented in this manner. This was facilitated by using a set of high-level macros, layered over the Argonne macro package, which provides the primitives in the adaptive partitioning scheme. Because of the portable nature of the Argonne macro package our code should be readily ported to other MIMD machines with shared memory. A version of the macros for other MIMD architectures is also possible.

Parallel depth first search. Part I. Implementation

This paper presents a parallel formulation of depth-first search which retains the storage efficiency of sequential depth-first search and can be mapped on to any MIMD architecture. To study its effectiveness it has been implemented to solve the 15-puzzle problem on three commercially available microprocessors - Sequent Balance 21000, the Intel Hypercube and BBN Butterfly. We have been able to achieve fairly linear speedup on Sequent up to 30 processors (the maximum configuration available) and on the Intel Hypercube and BBN Butterfly up to 128 processors (the maximum configurations available). Many researchers considered the ring architecture to be quite suitable for parallel depth-first search. Our experimental results show that hypercube and shared-memory architectures are significantly better. At the heart of our parallel formulation is a dynamic work distribution scheme that divides the work between different processors. The effectiveness of the parallel formulation is strongly influenced by the work distribution scheme and architectural features such as presence/absence of shared memory, the diameter of the network, relative speed of the communication network, etc. In a companion paper [16], we analyze the effectiveness of different load-balancing schemes and architectures, and also present new improved work distribution schemes.

The efficient termination of Ada tasks in a multi-processor environment

An efficient implementation of Ada task termination for shared memory MIMD architectures is presented. The solution is highly parallel and distributed; termination is not synchronized by a centralized supervisor, and there are no critical sections. The handling of block and subprogram termination that depend on nested tasks is also included. This implementation can be easily adapted to message based systems.

Parallelization and Performance Analysis of the Cooley–Tukey FFT Algorithm for Shared-Memory Architectures

We present here a study of parallelization of the Cooley-Tukey radix two FFT algorithm for MIMD (nonvector) architectures. Parallel algorithms are presented for one and multidimensional Fourier transforms. From instruction traces obtained by executing Fortran kernels derived from our algorithms, we determined the precise instructions to be executed by each processor in the parallel system. We used these instruction races to predict the performance of the IBM Research Parallel Processing Prototype, RP3, as a computer of FFT's. Our performance results are depicted in graphs included in this paper.

Reduction of the Effects of the Communication Delays in Scientific Algorithms on Message Passing MIMD Architectures

The efficient implementation of algorithms on multiprocessor machines requires that the effects of communication delays be minimized. The effects of these delays on the performance of a model problem on a hypercube multiprocessor architecture is investigated, and methods are developed for increasing algorithm efficiency. The model problem under investigation is the solution by red-black Successive Over Relaxation of the heat equation; most of the techniques to be described here also apply equally well to the solution of elliptic partial differential equations by red-black or multicolor SOR methods. This paper identifies methods for reducing communication traffic and overhead on a multiprocessor and reports the results of testing these methods on the Intel iPSC Hypercube. We examine methods for partitioning a problem’s domain across processors, for reducing communication traffic during a global convergence check, for reducing the number of global convergence checks employed during an iteration, and for concurrently iterating on multiple time-steps in a time dependent problem. Our empirical results show that use of these methods can markedly reduce a numerical problem’s execution time.

The performance analysis of the Homogeneous Multiprocessor Proper

Presents the structure and implementation details of a simulator which was written for the homogeneous multiprocessor proper. The homogeneous multiprocessor is a tightly coupled MIMD architecture composed of a number of processing elements and a distributively controlled network of switches, which permits each processor to access the resources of its two immediate neighbours. In addition, a fast local area network permits each processor to communicate with all other processors in a point-to-point or broadcast mode. The results of two simulation experiments which were carried out using the simulator are also presented. The first experiment was designed to test the behaviour of the network of switches under a varying interprocessor communication demand, while the second experiment was designed to obtain a performance measure of the multiprocessor by simulating a distributed algorithm for the calculation of the autocorrelation functions of a given signal.

Evolution and implementations of the RAP database machine

The article presents the evolution of the RAP. 1, RAP. 2, and RAP. 3 database architectures and discusses various implementations carried out to date. The RAP database machine has evolved from a fixed head disk based SIMD architecture into one that is an MIMD architecture and optimized around solid state bulk memories. With the dynamic and order preserving data space partitioning strategy, binary relational algebra and projection operation complexity has been reduced to a linear order. Its tagging based universal language has enabled various system implementations such as multimodel support, integrated text retrieval capabilities, and security and integrity control.