Efficient thermal dissipation remains one of the foremost challenges in modern electronics, as excessive heat can critically damage device performance and reliability. In this work, we introduce a novel thermal interface material (TIM) based on polyvinyl-formaldehyde (PVF) foam functionalized with multi-walled carbon nanotubes (MWCNTs) for advanced processor cooling. The developed composite exhibits high thermal conductivity, remarkable stability up to 200 °C, and minimal weight loss across a wide temperature range. A TIM with a[Formula: see text]cm2cross-section was engineered to interface directly with a CPU chip. The heat dissipation from the CPU was systematically investigated as a function of composition and design parameters to identify the optimal cooling configuration. Thermal characterization and CPU package modeling confirmed the superior heat dissipation capacity of the TIM. Among the tested configurations, the PVF/MWCNT composite with 4 wt% loading, fabricated in a square geometry and 2 mm thickness, demonstrated the most effective performance, achieving a minimum CPU temperature of66.72°C under an 80 W heat load. The square-shaped TIM outperformed its circular counterpart due to better conformity with the CPU surface, maximizing contact area and minimizing thermal resistance. Experimental validation closely matched the simulation results, confirming the reliability of the adopted model. These results establish PVF/MWCNT composites as a lightweight, thermally stable, and highly efficient TIM, offering strong potential for next-generation electronic devices operating at elevated temperatures.

ABSTRACT The word 'microprocessor' originated in 1971 when Intel in the USA produced their first microprocessor, the Intel-4004, which was a four bit microprocessor. A microprocessor is an essential component of a digital computer. It is an integrated circuit, programmed with a variety of instructions for performing arithmetic calculations as well as making decisions (just as a CPU does), all within a single semiconductor chip. A microprocessor-based computer is referred to as a computer that has a microprocessor as its central processing unit (CPU). This document examines current issues regarding Micro Processor (MP) technology development by gathering data from multiple research publications about latest trends, challenges, and potentials for future developments. It is intended that this paper addresses various topics including development of novel technologies such as neuromorphic processors (based on brain) and chips that have been built using the "Microprocessor without Interlocked Pipelined Stages (MIPS)" architecture, and a shift toward developing energy-efficient microprocessors and achieving better cross-platform compatibility between software and hardware platforms. This analysis will summarize each research publication in order to identify key points, methodologies, findings, and limitations of research conducted thus far, as well as summarize the main points presented in their respective introductions and discussions. This analysis can then be used to illustrate differing directions for development of MP technology. The documentation identified main trends associated with MP development such as widespread implementation of Reduced Instruction Set Computer (RISC) architectures; a requirement for energy-efficient approaches for developing future microprocessors; and developing means through microcode and software to control usage of pipelined processors. The documentation also includes summaries of major historical achievements associated with MP technology, as well as provides evidence of how MP technology has changed through use of new technologies, and outlines the technological evolution and design characteristics of the Central Processing Unit (CPU) and MP's over time. Keyword: - Microprocessor,CPU, AI Processor, Architecture, Real life technology, etc

As the industry moves toward High Performance Computing(HPC) for huge data transmission with low power consumption. The requirements for PKG structure have become more challenging. The major engineering requirements for HPC application are high-density, high-speed data transmission, low loss, precision manufacturing with low-cost process. High pin count need large area package with high mechanical stability and low warpage. The demand for high density and high-speed data transmission becomes strong needs for leading edge semiconductor packaging. 2.5D and 3D heterogenous package realize this solution. On the 2.5D heterogenous package structure, key technology is fine wiring connected with CPU chip and HBM chips. The fine wires needed high speed transmission. Silicon interposers with through silicon vias (TSVs) have developed to meet this demand, but face three major barriers high electrical loss, package size and cost. On the other hand, glass has many properties that make it an ideal substrate for BGA core substrates such as ultra-low loss tangent, adjustable thermal expansion (CTE), mechanical stability and manufacturability with large panel size. This paper presents the demonstration of Fine line Redistribution Layer (RDL) on Glass and Glass Core Substrate with fine pitch metalized through via. The ultra-high density RDL process using non-organic protective layer fabricated on the glass substrate. High aspect ratio 3 traces enable to minimum 3um pitch, high transmission rate and high reliability. We also focus on the potential for applying high-speed transmission performance to the next generation such as HBM3 and UCIe 1.0 based on the analysis of electromagnetic field simulation and the measurement results obtained from the fine pitch wiring composed on the glass material. We conducted experimental measurement on the electrical transmission characteristics of fine-wiring with a width ranging from 1.5 µm to 3 µm. Furthermore, our proposed fine wiring structure of covered with inorganic material had less influence on signal transmission performance. We have done actual measurement comparison with inorganic protective layers and without inorganic protective layers. we checked a comparative evaluation of eye patterns using measured S-parameters at the high-speed signal transmission condition with transient analysis. Furthermore, we utilized the obtained measurement results to validate their applicability for next- generation high-speed transmission, and we report the findings of our verification.

Fault detection of CPU chips using an interval estimation method

This article presents a cost-effective, robust, and reliable system for EMG/MMG (electromyography/mechanomyography). Signals indicating muscle activity have numerous applications and are the subject of many studies. However, acquiring these signals is challenging. Commercial measurement systems are often expensive, limiting their accessibility. Therefore, the primary goal of this project was to develop a simple and affordable system for simultaneous EMG and MMG data acquisition, offering efficiency comparable to commercial systems. The system consists of eight EMG/MMG probes, 16-bit analog-to-digital converters with 16 channels, and a microprocessor unit. Despite its multiple components, the system remains simple and user-friendly. This paper describes the construction of the EMG/MMG probe and analyzes the intrinsic noise of the preamplifier, as well as electromagnetic interference, particularly power line noise. The elimination of power line noise was carried out in two stages: first, using techniques known for electromagnetic compatibility (EMC), and second, by implementing a digital filter in the microprocessor system. The proposed solution enables direct data collection from eight EMG/MMG probes using any computer equipped with a USB interface. This interface facilitates both data transmission and power supply, making EMG/MMG data acquisition straightforward and efficient.

Aim. To analyse the dependability terminology as regards embedded software and hardware systems, to develop a methodology for assessing the functional dependability of the components of embedded software and hardware computer-based control systems, and to conduct a practical assessment of the dependability of the modern software and hardware components of embedded computers and microcontrollers for the purpose of selecting the optimal control system architecture. A prototype medical robot intended for holding surgical instruments, Farabeuf retractors, etc. is used as the controllable object. The robotics system includes a microprocessor unit based on a common single-board computer that implements high-level control and voice command recognition functions, an additional microprocessor unit for controlling servo drives and receiving input signals, as well as the actuating modules, i.e., drives. Methods. The paper uses reference source analysis, analyses non-peer-reviewed collections of documents, previously restricted foreign standards and publications. Results. The author presents a method for assessing the functional dependability of the components of an embedded software and hardware control system. The probability of no failure of software and hardware components of the examined system was calculated based on statistical estimates and on the amount of code. Despite the different calculation methods and reference data, the results are generally close. The paper also estimated the probability of no software failure for an alternative control system architecture, whereas a part of important functions is shared with an additional software and hardware unit having a higher level of dependability. In this case, such is an Atmega32 microcontroller that is to directly control the drives. A comparative analysis of the results shows that the additional level with partially parallelised functions and partial control channel redundancy significantly improved the assessment of the system’s probability of no failure under predefined conditions. Based on the calculated data, the paper defines a control system architecture with two system levels that has high values of probability of no failure. Conclusion. Given the trend of growing numbers of functions being integrated within a single microprocessor-based system, improved functional dependability should be achieved through a two-level functional architectural solution, whereas the key tasks in terms of direct interaction with the hardware environment are redistributed in favour of a separate hardware module. Additionally, as regards embedded systems, such an approach often allows defining a lower, real-time system layer and an upper system layer that is responsible for highlevel functions such as speech recognition, data communication via interfaces, and artificial intelligence. The matter of practical evaluation of embedded software dependability is not yet completely resolved. Such software is characterised by the lack of virtualisation and a level of hardware abstraction, which, in turn, causes a close relationship with the hardware and peripherals. Obviously, repeating the required tests is not enough. Test combinations should include external hardware effects (signal level anomalies) and software effects on the periphery of a microcontroller.

Abstract The topology optimization (TO) method is developed and applied to 3D heat sink design optimization using the finite element method (FEM). To go from theory to practical application of optimized heat sink designs, the impact of the ratio between fin height (Hc) and substrate thickness (Hb) on the performance of heat sinks was investigated, studying the critical role of geometric parameters in heat dissipation performance, focusing on optimizing the internal fluid channels to enhance the overall hydraulic and thermal efficiencies under various operating conditions. Optimal flow conditions vary across TO designs; notably, structures with near-equal (Hc) and (Hb) ratios demonstrated superior energy and fluid flow overall performances. At high Reynolds numbers, the optimized heat sink designs showed an enhancement in the overall performance up to 41.2%, showcasing the effectiveness of the present TO method. The new 3D optimal designs can be applied to different applications such as the cooling of CPU, GPU, and different electronic chips.

As the industry moves toward high-performance computing (HPC) for huge data transmission with low power consumption. The requirements for advanced package (PKG) structures have become more challenging. The major engineering requirements for HPC application are high-density, high-speed data transmission, low loss, precision manufacturing with low-cost process. High pin counts need large area package with high mechanical stability and low warpage. The demand for high density and high-speed data transmission becomes strong need for leading edge semiconductor packaging. 2.5D and 3D heterogenous package realize this solution. On the 2.5D heterogenous package structure, high interconnect density with fine line wiring layers providing high speed transmission is required to-connect CPU chips or chiplet arrays and HBM chip stacks. Silicon interposers with through silicon vias (TSVs) have scaled to meet this demand, but face three major barriers: high electrical loss, package size and cost. On the other hand, glass has many properties that make it an ideal core material for advanced substrates such as ultra-low loss tangent, adjustable thermal expansion (CTE), mechanical stability and manufacturability with large panel formats. This paper presents the demonstration of Glass core substrate with fine line redistribution layers (RDL). Glass core substrate with fine pitch metalized through glass vias (TGV) and fabricate RDL with low loss dielectrics. In case of Glass core substrate, three TGV copper metalized processes were compared for process capability, -reliability and high-speed transmission characteristics. Copper metallization provides low resistance, high transmission rate and high-power density. The reliability test results show stable resistance data because of combination of double-sided polymer dielectrics. The double-sided polymer dielectrics providing stress buffer for glass and copper CTE differences. TGVs filled with Cu by three methods were demonstrated with large panel size format max 550x650mm.The ultra-high density RDL process using non-organic protective layer fabricated on the glass substrate. High aspect ratio Cu traces enable to minimum 3um pitch, high transmission rate and high reliability. We also compare high speed transmission characteristics with TGV and transmission trace with multi-layer RDL on panel level format. Finally, we compare the transmission characteristics using eye diagram for heterogenous integration application.

Abstract Enhancing critical heat flux (CHF) and heat transfer coefficient (HTC) by promoting the nucleation, growth, and departure of boiling bubbles has drawn significant attention owing to its wide applications. However, in‐depth understanding and comprehensive manipulation of under‐liquid bubble dynamics from in situ microscale perspectives remain challenging. Herein, in situ observations and analyses of the microsized boiling bubbles of ultra‐low surface tension fluorinated liquids (FLs) are conducted on the superaerophobic silicon surfaces with crisscross microchannels and selective nanowires. It is revealed that deep microchannels yet short nanowires enable ultrafast liquid spreading (<549.6 ms) and ultralow bubble adhesion (≈1.1 µN), while an appropriate spacing (240–600 µm) between microchannels minimizes the bubble departure time (<20.6 ms) due to timely coalescence. By verifying the above bubble dynamics principles through the collaborative enhancement of CHF and HTC, an optimized structure (microchannel depth ≈52.9 µm, microchannel spacing ≈362.9 µm, nanowire length ≈0 nm) is obtained and further implemented onto the exposed Si surface of a commercial CPU chip. Cooled by phase‐change of FLs, the average temperature of CPU maintains ≈64.9 °C even under extreme power loads (≈130 W), far below than those in conventional air‐cooling and water‐cooling operations.

We aim to determine the applicability of standard microprocessor units of relay protection and automatics for obtaining a digital signal of currents for their subsequent mathematical processing with the purpose of identifying internal faults of electrical equipment. Mathematical processing of experimental data (time series) based on regression analysis approximation in orthogonal basis was carried out. To that end, the weight coefficients of basis functions obtained by the least squares method were compared in terms of multidimensional space vectors, corresponding to the coordinates of this space. The investigated signal was a data set obtained by field experiments conducted with an induction motor, which assumed the possibility of creating artificial internal damage. Experimental data were obtained using two devices with different sampling rates and quantization levels. The first set of data was obtained using a 12-bit PCI board of analog-to-digital converter for installation in a National Instruments 6024E PC at a sampling rate of 10 kHz. The second set of data was obtained using a standard block of microprocessor relay protection and automation at a sampling rate of 2.4 kHz. Indicators for the presence of internal damage to the rotor circuit of an induction motor, which reduces the motor energy characteristics without affecting its operation significantly, were determined. The indicators of the damaged and undamaged state differed by a factor of five. The proposed method for selecting the diagnostic sign of internal damage of electrical equipment of electrical installations detects a 3% deviation in their parameters from the normal state, ignoring the presence of electrical/mechanical load. The diagnostic sign was established to behave similarly in the presence of internal damage, in both sets of signals under study. Thus, the possibility of obtaining a digital signal of acceptable accuracy from standard relay protection units for ensuring reliable identification of internal faults of electrical equipment of electrical installations is confirmed.

Abstract A high‐sensitivity cavity ring‐down spectroscopy gas detection system with integrated optical components and embedded microprocessor units is presented for the detection of hydrogen sulfide (H 2 S) in sulphur hexafluoride (SF 6 ) and its mixture with nitrogen (N 2 ). The system exploits a periodic laser wavelength modulation to simplify the mode matching. Spectral line profile fitting is used for sample quantitative analysis. To verify the sensitivity and stability of concentration detection, the effect of background gas and temperature on the responses of spectral line broadening and absorption cross‐section are investigated. The result deviation caused by variation of background gas can be compensated by the pre‐correction of empty cavity ring‐down time. It is also found that the implication of temperature on the spectra cannot be ignored. The full width at half maximum and peak value decreased linearly with the increase of temperature, while the baseline is undergoing accelerated growth. Using Allan variance analysis, the limits of detection reach 4.44 × 10 −9 in SF 6 and 2.96 × 10 −9 in N 2 with average time of 67 s. This study provides a meaningful approach for the online detection of characteristic gas in gas insulation equipment.

Simulation of displacement damage in Si & SiO2 caused by protons

An automated interferometric stand (AIS) was created to determine the amplitude-frequency characteristics of acoustic emitters in the range from 0.5 to 200 kHz. The created AIS contains a unit for generating acoustic sinusoidal excitation pulse packets and a recording unit. The unit for generating acoustic pulse packets includes a generator of sinusoidal signals, a microprocessor unit for pulse packets generation and the AIS synchronization, a power amplifier of a sinusoidal signal to create a sufficient power of the acoustic emitter excitation signal. The recording unit includes a Michelson interferometer with a sound-conducting rod in one of the arms. One of the ends of the rod has a mirror surface. The other end is connected to the acoustic emitter through an acoustic contact. The length of the sound-conducting rod is 50 cm, which is enough to ensure measurements at the lower limit of the frequency range of the acoustic emitter radiation. The propagation time of the acoustic wave in the rod is of the order of 75 microseconds. As the end of the rod vibrates due to acoustic excitation, the initial path difference of the optical beams in the interferometer will change, causing a change in the intensity of the illumination produced by the interfering beams. These changes are recorded by photodiode in the other arm of the interferometer. After the photodiode signal is amplified in the amplifier, it is fed to the analog-to-digital converter, the output of which is transferred to the buffer memory, where the discretized values of the response signal amplitude during the time of the measuring pulse are accumulated. The control algorithm of the AIS is carried out with the help of developed software. The results of measuring the amplitude-frequency characteristics of mass-produced broadband acoustic emitters using AIS proved the satisfactory convergence of the obtained frequency responses with the passport data of these serial devices frequency responses. The amplitude-frequency characteristic of experimental sample of a piezoelectric acoustic emitter, made for research on the detection and identification of internal defects in laminated composite structures and "composite-concrete" adhesive joints, was obtained.

MicroRNA (miRNA) biogenesis is initiated upon cleavage of a primary miRNA (pri-miRNA) hairpin by the Microprocessor (MP), composed of the Drosha RNase III enzyme and its partner DGCR8. Multiple pri-miRNA sequence motifs affect MP recognition, fidelity, and efficiency. Here, we performed cryoelectron microscopy (cryo-EM) and biochemical studies of several let-7 family pri-miRNAs in complex with human MP. We show that MP has the structural plasticity to accommodate a range of pri-miRNAs. These structures revealed key features of the 5' UG sequence motif, more comprehensively represented as the "flipped U with paired N"(fUN) motif. Our analysis explains how cleavage of class-II pri-let-7 members harboring a bulged nucleotide generates a non-canonical precursor with a 1-nt 3' overhang. Finally, the MP-SRSF3-pri-let-7f1 structure reveals how SRSF3 contributes to MP fidelity by interacting with the CNNC motif and Drosha's Piwi/Argonaute/Zwille (PAZ)-like domain. Overall, this study sheds light on the mechanisms for flexible recognition, accurate cleavage, and regulated processing of different pri-miRNAs by MP.

SummarymiRNA biogenesis is initiated upon cleavage of a primary miRNA (pri-miRNA) hairpin by the Microprocessor (MP), composed of the Drosha RNase III enzyme and its partner DGCR8. Multiple pri-miRNA sequence motifs affect MP recognition, fidelity, and efficiency. Here, we performed cryo-EM and biochemical studies of several let-7 family pri-miRNAs in complex with human MP. We show that MP has the structural plasticity to accommodate a range of pri-miRNAs. These structures revealed key features of the 5’ UG sequence motif, more comprehensively represented as the “fUN” motif. Our analysis explains how cleavage of class-II pri-let-7 members harboring a bulged nucleotide generates a noncanonical precursor with a 1-nt 3’ overhang. Finally, the MP-SRSF3-pri-let-7f1 structure reveals how SRSF3 contributes to MP fidelity by interacting with the CNNC-motif and Drosha’s PAZ-like domain. Overall, this study sheds light on the mechanisms for flexible recognition, accurate cleavage, and regulated processing of different pri-miRNAs by MP.

With the advancement in artificial intelligence technology, autonomous mobile robots have been utilized in various applications. In autonomous driving scenarios, object classification is essential for robot navigation. To perform this task, light detection and ranging (LiDAR) sensors, which can obtain depth and height information and have higher resolution than radio detection and ranging (radar) sensors, are preferred over camera sensors. The pillar-based method employs a pillar feature encoder (PFE) to encode 3D LiDAR point clouds into 2D images, enabling high-speed inference using 2D convolutional neural networks. Although the pillar-based method is employed to ensure real-time responsiveness of autonomous driving systems, research on accelerating the PFE is not actively being conducted, although the PFE consumes a significant amount of computation time within the system. Therefore, this paper proposes a PFE hardware accelerator and pillar-based object classification model for autonomous mobile robots. The proposed object classification model was trained and tested using 2971 datasets comprising eight classes, achieving a classification accuracy of 94.3%. The PFE hardware accelerator was implemented in a field-programmable gate array (FPGA) through a register-transfer level design, which achieved a 40 times speedup compared with the firmware for the ARM Cortex-A53 microprocessor unit; the object classification network was implemented in the FPGA using the FINN framework. By integrating the PFE and object classification network, we implemented a real-time pillar-based object classification acceleration system on an FPGA with a latency of 6.41 ms.

Abstract The heart produces bioelectrical signals, which can be measured as an electrocardiogram (ECG) for the detection of rhythm disturbances. Rapid and precise detection of these arrhythmias is crucial for their termination by closed‐looped therapeutic interventions to counteract detrimental effects. However, there is a current lack of such systems tailored for experimental cardiovascular applications. This hampers not only in‐depth mechanistic studies but also translational testing of new therapeutic strategies, especially in an untethered manner in awake animal models. To break new ground, recent advances to develop a non‐invasive AI‐supported heart rhythm monitoring system for untethered automated arrhythmia detection in a continuous manner is combined. This system is housed in a lightweight jacket for mobile use and includes an on‐skin ECG sensor, a low‐power microprocessor unit, a massive data storage unit, and a power‐management system. By implementing a novel hybrid algorithm based on so‐called heart rate (R‐R) variability and a case‐specific AI model, 100% sensitivity and 95% specificity is achieved in detecting atrial arrhythmias within 2 s upon initiation in adult rats. Thereby, the novel system sets the stage for advanced mechanistic studies and therapeutic testing, including closed‐loop applications aiming for the termination of a broad range of atrial arrhythmias.

Abstract Rare earth luminescent materials based on negative thermal expansion (NTE) have achieved thermally enhanced photoluminescence, but these materials typically exhibit relatively weak luminescence intensity at room temperature. In this work, adopting the cationic heterovalent substitution strategy, a series of Sc2‐2xZrxNbxW3‐1.5xO12‐3x:Yb/Er (SZNWOx:Yb/Er) phosphors are prepared by solid‐state reaction. With the increase of x value, the substitution of Sc3+ by Zr4+/Nb5+ leads to a decrease in the local symmetry of Er3+. Compared with Sc2W3O12:Yb/Er (SWO:Yb/Er), this heterovalent substitution strategy significantly improves the luminescence intensity of SZNWOx:Yb/Er while retaining its anti‐thermal quenching luminescence and negative thermal expansion properties. By comparing and analyzing the temperature dependent temperature‐dependent steady‐state/transient spectra of SZNWO0.10:Yb/Er and SWO:Yb/Er phosphors, the anti‐thermal quenching mechanism is discussed from a new perspective. The luminescence intensity ratio (LIR) of the thermal coupled levels (TCL) of Er3+(2H11/2/4S3/2) is adopted for optical temperature sensing, achieving a maximum absolute sensitivity of 1.04% K−1 at 464 K and a maximum relative sensitivity of 1.08% K−1 at 298 K for the SZNWO0.10:Yb/Er phosphors. Finally, the potential applicability using the constructed flexible thin film to real‐world sensing scenarios is demonstrated, offering accurate and real‐time temperature monitoring at the local hotspot in the electronic component of the CPU chip.

With the high-speed and high-frequency operation of CPU chips, as well as miniaturization and dense assembly of integrated circuits, the heat generated by the Raspberry Pi CPU is constantly increasing. To address the urgent need for efficient Raspberry Pi CPU heat dissipation and ensure normal operation within a safe temperature range, this study first established a model to simulate the CPU's thermal physics parameters during operation using CFD simulation software. An experimental platform was then set up to validate the CFD simulation results. Based on the validated CFD model, initial heat dissipation design was carried out. On this basis, the heat dissipation system was optimized by altering the heat sink’s length, width, fin height, thickness, spacing, and the thermal grease’s thermal conductivity between the heat sink and CPU chip. A surrogate model was established using the response surface methodology, and the NSGA-II genetic algorithm was employed for multi-objective optimization of the heat dissipation system’s cooling performance. Compared to the initial solution, the chip temperature was reduced by 6.19 °C, but the heat sink mass was increased by 0.65 g. By conducting multi-objective optimization design and making reasonable choices for the parameters, a suitable and an optimum design, in terms of both economics and efficiency, is obtained. These results demonstrate that this research can provide theoretical guidance and technical support for practical production. Furthermore, the methods and findings from this study can be applied to the design of heat dissipation systems for similar applications.

Interposers for system in package will became more and more important for advanced electronic systems. As the industry moves toward HPC (High Performance Computing) for huge data transmission with low power consumption. The major engineering requirements for HPC application are highdensity, high speed data transmission, low loss, precision manufacturing and low cost. On the 2.5D heterogenous package structure, key technology is fine wiring connected with CPU chip and HBM chips. The fine wires needed high speed transmission. This paper presents the demonstration of Glass-based twin type interposers, Glass interposer with fine pitch metalized through via and RDL interposer with low loss dielectrics on Glass carrier. We compare twin types of Interposes fabrication process capability with panel size format 300x400mm. Finally, we compare the transmission characteristics using eye diagram for heterogenous integration application. Glass Interposer has low loss glass via, it is effective vertical interconnection. RDL interposer has low loss dielectric layers, excellent transmission characteristics obtained on fine pitch trace area.