Microprocessor Without Interlocked Pipeline Stages Research Articles

Design of 16 Bit RISC Processor and Implementation using MIPS Technique

This research paper presents design & simulation of a high performance five stage pipelined 8 bit or 16-bit Microprocessor without Interlocked Pipeline Stages (MIPS), which is a Reduced Instruction Set Computing (RISC) architecture based processor. The purpose of RISC microprocessor is to execute a minuscule batch of instructions, with the intention of proliferating the celerity of the processor. This processor was designed with 5 phases of pipeline in particular Instruction Fetch (IF), Instruction Decode & Register Fetch (ID), Execution & Address Calculation (EX), Memory Access (MEM) and Write Back (WB) modules. The designing process was done using a myriad of modules which are the ALU, Control Unit, Program Counter, MUX, Instruction Memory, Data Memory, CPU, Register File, and Sign Extension. The Proposed design is developed by Verilog HDL and Simulated by Modelsim 6.4 c and Synthesized by Xilinx tool and proposed system implemented in FPGA Spartan 3 XC3S 200 TQ-144.

FPGA-Based Multi-Core MIPS Processor Design

This research presents a study for multicore Reduced Instruction Set Computer (RISC) processor implemented on the Field Programmable Gate Array(FPGA).The Microprocessor without- Interlocked Pipeline Stages (MIPS) processor is designed for the implementation of educational purposes, as well as it is expected that this prototype of processor will be used for multimedia or big data applications. 32- bit MIPS processor was designed by using Very High speed Hardware Description Language (VHDL). Pipelined MIPS processor contains three parts that are : data path 32-bit MIPS pipeline, control unit, and hazard unit. The single cycle MIPS system was subdivided into five pipeline stages to achieve the pipeline MIPS processor. The five parts include: instruction fetch (IF), Instruction Decode (ID), execution (EXE), memory (MEM) and Write Back (WB). Three types of hazard: data hazard , control hazard and strctural hazard are resolved. Certain components in the pipelined stage for the design processor were iterated for four core SIMD pipelined processors. The MIPS is developed using Xilinx ISE 14.7 design suite. The designed processor was implemented successfully on Xilinx Virtex-6 XC6VLX240T-1FFG1156 FPGA. The total power analysis of multi-core MIPS processor is obtanined 3.422 watt and the clock period was 7.329 ns (frequency: 136.444MHz). Index Terms— FPGA, MIPS, RISC, VHDL.

Exploring User Interface Improvements for Software Developers who are Blind

Software developers who are blind and interact with the computer non-visually face unique challenges with information retrieval. We explore the use of speech and Braille combined with software to provide an improved interface to aid with challenges associated with information retrieval. We motivate our design on common tasks performed by students in a software development course using a Microprocessor without Interlocked Pipeline Stages (MIPS) architecture simulation tool. We test our interface via a single-subject longitudinal study, and we measure and show improvement in both the user’s performance and the user experience.

A Concept Map-Based Remedial Learning System With Applications to the IEEE Floating-Point Standard and MIPS Encoding

Contributions: A concept-map-based remedial learning system is presented to enhance students' grasp of the learning concepts of the IEEE floating-point standard and microprocessor without interlocked pipeline stages (MIPSs) encoding according to their understanding of these learning concepts. Background: Concept maps have been used to represent the knowledge structures of learning topics. This study presents another usage of concept maps, illustrating the prerequisite relationships between and among the learning concepts in a concept map. Simulation-based systems for learning the IEEE floating-point standard and MIPS encoding have been implemented. A simple remedial learning system that helps students to learn the IEEE floating-point standard and MIPS encoding would therefore be valuable, but had yet to be designed. Intended Outcomes: Students' understandings of the IEEE floating-point standard and MIPS encoding are expected to enhance via studying the remedial materials generated by this system. Application Design: A one-group-pretest-posttest design was utilized. The students first took a pretest to get their grasp of the learning concepts, and then studied the remedial learning materials according to their understanding of the learning concepts in the pretest. Findings: 1) The score progress of the IEEE floating-point learners was significant after they undertook remedial learning; 2) the score progress of the low-achieving students was significantly greater than that of the high-achieving students, in their learning of the IEEE float-pointing standard; 3) the score progress of the MIPS encoding learners was significant after they undertook remedial learning; and 4) the score progress of the low-achieving students was significantly greater than that of the high-achieving students in their learning of MIPS encoding, with weak evidence.

Design and Implementation of 6-Stage 64-bit MIPS Pipelined Architecture

Pipelining is the concept of overlapping of multiple instructions to perform their operations to optimize the time and ability of hardware units. This paper presents the design and implementation of 6 stage pipelined architecture for High performance 64-bit Microprocessor without Interlocked Pipeline Stages (MIPS) based Reduced Instruction set computing (RISC) processor. In this work, combining efforts of pre-fetching unit, forwarding unit, Branch and Jump predicting unit, Hazard unit are used to reduce the hazards. Low power unit is used to minimize the power. Cache Memories, other devices and especially balancing pipeline stages optimize the Speed in this work. DDR4 SDRAM (Double Data Rate type4 Synchronous Dynamic Random Access Memory) controller is employed in this pipeline to achieve high-speed data transfers and to manage the entire system efficiently. Low power, Low delay Flip flops are used in pipeline registers that implicitly enhance the performance of the system. The proposed method provides better results compared to the existing models. The simulation and synthesis results of the proposed Architecture are evaluated by Xilinx 14.7 software and supporting graphs are plotted through MATLAB tool

Secure and Dynamic Memory Management Architecture for Virtualization Technologies in IoT Devices

The introduction of the internet in embedded devices led to a new era of technology—the Internet of Things (IoT) era. The IoT technology-enabled device market is growing faster by the day, due to its complete acceptance in diverse areas such as domicile systems, the automobile industry, and beyond. The introduction of internet connectivity in objects that are frequently used in daily life raises the question of security—how secure is the information and the infrastructure handled by these devices when they are connected to the internet? Security enhancements through standard cryptographic techniques are not suitable due to the power and performance constraints of IoT devices. The introduction of virtualization technology into IoT devices is a recent development, meant for fulfilling security and performance needs. However, virtualization augments the vulnerability present in IoT devices, due to the addition of one more software layer—namely, the hypervisor, which enables the sharing of resources among different users. This article proposes the adaptation of ASMI (Architectural Support for Memory Isolation—a general architecture available in the literature for the improvement of the performance and security of virtualization technology) on the popular MIPS (Microprocessor without Interlocked Pipeline Stages) embedded virtualization platform, which could be adopted in embedded virtualization architectures for IoT devices. The article illustrates the performance enhancement achieved by the proposed architecture with the existing architectures.

A Flexible Framework for the Automatic Generation of SBST Programs

Software-based self-test (SBST) techniques are used to test processors and processor cores against permanent faults introduced by the manufacturing process or to perform in-field test in safety-critical applications. However, the generation of an SBST program is usually associated with high costs as it requires significant manual effort of a skilled engineer with in-depth knowledge about the processor under test. In this paper, we propose an approach for the automatic generation of SBST programs. First, we detail an automatic test pattern generation (ATPG) framework for the generation of functional test sequences. Second, we describe the extension of this framework with the concept of a validity checker module (VCM), which allows the specification of constraints with regard to the generated sequences. Third, we use the VCM to express typical constraints that exist when SBST is adopted for in-field test. In our experimental results, we evaluate the proposed approach with a microprocessor without interlocked pipeline stages (MIPS)-like microprocessor. The results show that the proposed method is the first approach able to automatically generate SBST programs for both end-of-manufacturing and in-field test whose fault efficiency is superior to those produced by state-of-the-art manual approaches.

REALIZATION OF HIGH PERFORMANCE RUN-TIME LOADABLE MIPS SOFT-CORE PROCESSOR

Soft-core processors on Field Programmable Gate Array (FPGA) chips are becoming a solution for application-specific customization. Soft-core processors provide several advantages for designer. Currently using microprocessor doesn’t support realtime loading. If, any change in the assembly code of the implemented processor, it requires re-implementation and downloads the softcore on FPGA. This project proposes realization of run-time loading technique of a MIPS (Microprocessor without Interlocked Pipeline Stages) soft- core processor on FPGA. The proposed system consists of mainly three components: microprocessor soft-core, software tool and universal asynchronous Receiver/Transmitter (UART). Since, here MIPS code is updating instantly there is no need of resynthesize, place, route, and reload the soft-core. The software tool communicates between the user and MIPS soft-core processor through UART. Five stage pipelining is included to improve the overall processor performance. In this paper 32-bit MIPS soft-core processor, RAM module, APB Interface is designed and simulated using Modelsim. Design architecture will be doing in Verilog, simulate using Modelsim 10.3 simulator and realize in Spartan-6 FPGA using Xilinx ISE 14.2.

AODV-UI Proof of Concept on MIPS-based Wireless Router

AODV routing protocol facilitates changing and simple-to-setup network environment. It helps setting up a network without sufficient infrastructure, such as in disaster area. Development of AODV protocol has gathered a worldwide research interest. However, not many researches implement AODV routing protocol in real mobile nodes and real MANET. In addition, real implementation deals with other works concerning underlying protocol, firmware and hardware configuration, as well as detailed topology both in logical and physical arrangement. This work aims to implements Ad-hoc On-demand Distant Vector – particularly University of Indonesia AODV (AODV-UI) routing protocol on low-end inexpensive generic wireless routers as a proof of concept. AODV-UI is an improved version of AODV routing protocol that implements gateway interconnection and reverse route capability. This routing protocol has been previously successfully tested in NS-2. In this work, current AODV-UI protocol is ported to OpenWRT + MIPS (Microprocessor without Interlocked Pipeline Stages) little endian architecture then tested on the real networking environment. Underlying media access layer is also altered to provide the protocol greater control over the network. Performance of this implementation is measured in terms of energy consumption, routing overhead, end-to-end delay, protocol reliability and packet delivery ratio.

Area Optimized Implementation For Mips Processor

The implementation of 32 bit RISC processor with microprocessor without interlocked pipeline stages (MIPS) is presented. It was implemented in VHDL so as to reduce the instruction set present in the programmable memory. As the result the processor will contain the necessary logics for the implementation that requires fewer gates to be synthesized in the programmable matrix and has the capability to increase the speed of the target processor with reduced memory. In this paper we propose a novel technique of run-time loading of machine code for MIPS-32 soft-core processor. As we know, implementing fewer instructions on silicon reduces the complexity of the instruction decoder, the addressing logic, and the execution unit. This allows the machine to be clocked at a faster speed, since less work needs to be done each clock period. In this paper we used Xilinx- ISE tool for logical verification, and further synthesizing it on Xilinx-ISE tool using target technology and

A Component-based Simulator for MIPS32 Processors

Processor concepts, implementation details, and performance analysis are fundamental in computer architecture education, and MIPS (microprocessor without interlocked pipeline stages) processor designs are used by many universities in teaching the subject. In this paper we present a MIPS32 processor simulator, which enriches students’ learning and instructors’ teaching experiences. A family of single-cycle, multi-cycle, and pipeline processor models for the MIPS32 architecture are developed according to the parallel Discrete Event System Specification (DEVS) modeling formalism. A collection of elementary sequential and combinational model components along with the processor models are implemented in DEVS-Suite. The simulator supports multi-level model abstractions, register-transfer level animation, performance data collection, and time-based trajectory observation. These features, which are partially supported by a few existing simulators, enable important structural and behavioral details of computer architectures to be described and understood. The MIPS processor models can be reused and systematically extended for modeling and simulating other MIPS processors.