Microprocessor Techniques Research Articles

Application of the Nucleo STM32 module in teaching microprocessor techniques in automatic control

Wydawnictwo SIGMA-NOT wydaje czasopisma fachowe informujące swoich czytelników o najnowszych osiągnięciach naukowych i nowoczesnych rozwiązaniach technicznych w Polsce i na świecie, popularyzuje problemy techniczne oraz poszerza wiedzę i kulturę techniczną.

Algorithm of generation test for adaptable test based on structural numbers

The algorithm of generation tests based on structural numbers was proposed, was given a description of structural numbers and providing operations with them. Forming base of tasks with structural numbers was considered with examples from subject “Additional chapters of microprocessor technique”, was considered tests adaptability. Reference 3, figures 1.

Recent thermal management techniques for microprocessors

Microprocessor design has recently encountered many constraints such as power, energy, reliability, and temperature. Among these challenging issues, temperature-related issues have become especially important within the past several years. We summarize recent thermal management techniques for microprocessors, focusing on those that affect or rely on the microarchitecture. We categorize thermal management techniques into six main categories: temperature monitoring, microarchitectural techniques, floorplanning, OS/compiler techniques, liquid cooling techniques, and thermal reliability/security. Temperature monitoring, a requirement for Dynamic Thermal Management (DTM), includes temperature estimation and sensor placement techniques for accurate temperature measurement or estimation. Microarchitectural techniques include both static and dynamic thermal management techniques that control hardware structures. Floorplanning covers a range of thermal-aware floorplanning techniques for 2D and 3D microprocessors. OS/compiler techniques include thermal-aware task scheduling and instruction scheduling techniques. Liquid cooling techniques are higher-capacity alternatives to conventional air cooling techniques. Thermal reliability/security issues cover temperature-dependent reliability modeling, Dynamic Reliability Management (DRM), and malicious codes that specifically cause overheating. Temperature-related issues will only become more challenging as process technology continues to evolve and transistor densities scale up faster than power per transistor scales down. The overall objective of this survey is to give microprocessor designers a broad perspective on various aspects of designing thermal-aware microprocessors and to guide future thermal management studies.

Revisiting reorder buffer architecture for next generation high performance computing

Modern microprocessors achieve high application performance at an acceptable level of power dissipation. Reorder buffer is used for out-of-order instructions to be committed in-order. The reorder buffer plays a key role in modern microprocessors because performance improvement techniques highly rely on aggressive speculation to feed wider issue, out-of-order, and deep pipelines. In terms of power to performance trade-off, reorder buffer is particularly important. This is because enlarging the reorder buffer size achieves high performance but naive scaling of the conventional reorder buffer architecture can severely increase the complexity and power consumption. In this paper, we propose low-power reorder buffer techniques for contemporary microprocessors. First, the separated reorder buffer reduces power dissipation by deferred allocation and early release. The deferred allocation delays the SROB allocation of instructions until all their data dependencies are resolved. Then, the instructions are executed in program order and they are released faster from the SROB. The result of the instruction is written into rename buffers immediately after the execution completes. Then, the result values in the rename buffer are written into the architectural register file at the commit state. The proposed approaches in this paper provide higher resource utilization and low power consumption.

Portable Embedded Data Display and Control Unit using CAN Bus

The development trend and research focus of control system is networked control. The Field Bus Control System (FCS) which is important segment in networked system is widely applied in control system. The CAN (Controller Area Network) bus which has strong fault tolerance, high reliability and low cost plays an important role in FCS. The CAN is a serial communication protocol which efficiently supports distributed real-time control with a very high level of security. Its domain of application ranges from high speed networks to low cost multiplex wiring. In automotive electronics, engine control units, sensors, anti-skid-systems, etc. are connected using CAN with bit rates up to 1M bit/s. This project is to develop an automatic monitor and control of any non-industrial process using a Portable Embedded data display and control unit based on CAN Bus. It is implemented by applying 16 bit RISC key microprocessor technique, embedded software technology, embedded GUI (Graphics User Interface) technology, CAN bus communication technology, information storage and management technology[6]. The Proposed system involves the CAN Protocol to communicate the data. The system consists of many nodes each comprising a PIC microcontroller and a sensor. The data is retrieved from the sensor and forwarded to a PIC microcontroller through a CAN transceiver. The PIC Microcontroller establishes connection with a CAN Protocol and process the sensor data and the data through the CAN Bus which is twisted pair of wires. Another PIC microcontroller at remote end is interfaced with LCD (Liquid Crystal Display) to view the sensor data and send back control signal to the sensor through CAN protocol. The research and development of this project was driven by robustness of CAN communication and its practicality of application.

An Energy Efficient Instruction Window for Scalable Processor Architecture

Modern microprocessors achieve high application performance at the acceptable level of power dissipation. In terms of power to performance trade-off, the instruction window is particularly important. This is because enlarging the window size achieves high performance but naive scaling of the conventional instruction window can severely increase the complexity and power consumption. In this paper, we propose low-power instruction window techniques for contemporary microprocessors. First, the small reorder buffer (SROB) reduces power dissipation by deferred allocation and early release. The deferred allocation delays the SROB allocation of instructions until their all data dependencies are resolved. Then, the instructions are executed in program order and they are released faster from the SROB. This results in higher resource utilization and low power consumption. Second, we replace a conventional issue queue by a direct lookup table (DLT) with an efficient tag translation technique. The translation scheme resolves the instruction dependency, especially for the case of one producer to multiple consumers. The efficiency of the translation scheme stems from the fact that the vast majority of instruction dependency exists within a basic block. Experimental results show that our proposed design reduces the power consumption significantly for SPEC2000 benchmarks.

Processor validation: a top-down approach

This work presents the design validation techniques for microprocessors. The verification effectiveness validates the design implementation using a combination of simulation techniques and formal methods. This article presents a top-down validation methodology that complements existing bottom-up verification techniques. The validation team applies model checking to a high-level description of the design abstracted from the RTL implementation. Formal verification uses a formal language to describe the system. The specification for the formal verification comes from the architecture description; the implementation can come from either the architecture specification or the abstracted design. A top-down methodology for validating microprocessors using a combination of symbolic simulation and equivalence checking is presented. Specification-driven hardware generation and validation of design implementation using equivalence checking has one limitation: the structure of the generated hardware reference model is similar to that of implementation.

A uniform approach to mixed-signal circuit test

Owing to the analogue nature of many industrial processes and the increasing use of microprocessor techniques, many circuits nowadays carry mixed (digital and analogue) signals. As complexities of these circuits increase, the testability of mixed-signal circuits has become an important issue that must be dealt with by both design and test engineers. A systematic approach to study the testability of mixed-signal circuits is urgently needed, because current ad hoc methods cannot efficiently handle increasingly complex and ever-changing circuits. In this paper we develop a uniform and systematic approach to the mixed-signal circuit testability problem. The approach is based on a recently developed theory of discrete event systems. It is suitable for the following tasks: (i) checking the testability of a circuits; (ii) computing the minimum test set; (iii) finding the fault coverage; (iv) dividing a circuit into testable modules.

Hardware in Loop Simulation for Missile Guidance and Control Systems

The purpose of the guidance law is to determine appropriate missile flight path dynamics to achieve mission objective in an efficient manner based on navigation information. Today, guided missiles which are aerodynamically unstable or non-linear in all or part of the flight envelopes need control systems for stability as well as for steering. Many classical guidance and control laws have been used for tactical missiles with varying degrees of performance, complexity and seeker/sensor requirements. Increased accuracy requirements and more dynamic tactics of modern warfare demand improvement of performance which is a trade-off between sophisticated hardware and more sophisticated software. To avoid increase in cost by hardware sophistication, today's trend is to exploit new theoretical methods and low cost high speed microprocessor techniques. Missile test flights are very expensive. The missile system with its sophisticated software and hardware is not reusable after a test launch. Hardware-in-loop Simulation (HILS) facilities and methodology form a well integrated system aimed at transforming a preliminary guidance and control system design to flight software and hardware with trajectory right from lift-off till its impact. Various guidance and control law studies pertaining to gathering basket and stability margins, pre-flight, post-flight analyses and validation of support systems have been carried out using this methodology. Nearly full spectrum of dynamically accurate six-degrees-of-freedom (6-DOF) model of missile systems has been realised in the HILS scenario. The HILS facility allows interconnection of missile hardware in flight configuration. Pre-flight HILS results have matched fairly well with actual flight trial results. It was possible to detect many hidden defects in the onboard guidance and control software as well as in hardware during HILS. Deficiencies in model, like tail-wag-dog (TWD), flexibility, seeker dynamics and defects in the guidance and control system were demonstrated in HILS. Appropriate design modifications were introduced and tested in record time to reduce the number of expensive flight trials.

Investigation into optimising high switching frequency regular sampled PWM control for drives and static power converters

A new high switching frequency regular sampled PWM control technique is presented, which significantly reduces the number of calculations required to generate PWM control in real-time. It is shown that this new PWM technique greatly simplifies the microprocessor software implementation, thereby considerably reducing the on-line computing requirements, and thus allows significantly higher switching frequency PWM to be generated using microprocessor techniques. Moreover, it is confirmed using both simulation and experimental results that this reduction in the computational burden does not significantly increase the harmonic distortion. Finally, it is shown that the new regular sampled PWM technique can be described and generated using both the conventional ‘per-phase’ and ‘space-vector’ techniques.

Development of highly reliable control systems for the gas-insulated switchgear

Microprocessor-based control, protection and monitoring devices, such as digital relays and diagnostic systems, have been applied to electric power fields. The highly reliable control systems (HRCS) based on microprocessor techniques for gas-insulated switchgear (GIS) have been developed. From the results of the CIGRE circuit breaker reliability survey, the need for improving the reliability of switchgear control circuits is presented. The HRCS for the GIS uses the programmable logic controller (PLC), solid-state electronics and optical sensors as a replacement for conventional hard-wired electromechanical control circuits which improves reliability and availability of the GIS control circuits. The HRCS has been verified and applied to the substation. This paper introduces the results of verification tests together with the principle of the HRCS. Also reported is application to the high voltage substation.

Field-oriented control of induction motors using DSP

Because of the complexity of mathematical models of induction motors, the dynamic behaviour of ordinary algorithms is poor. The field-oriented control method has numerous advantages, but requires high computing power. However, implementation of this method has recently become more justifiable as a result of the decreasing price stemming from the development of power electronic devices and microprocessor techniques. A DSP (TMS320C25) based field-orientation control system with digital current regulation of the induction motor without an external current control loop is proposed. Some aspects of the theory, computer simulations and experimental results of the proposed method are given.

Designing, packaging, and testing a 300-MHz, 115 W ECL microprocessor

A custom microprocessor implemented with 1-μm bipolar technology operates at 300 MHz and dissipates 115 W. By using full-custom ECL technology, we achieved clock rates three to six times faster than 1-μm CMOS processors. We designed this research prototype to develop VLSI ECL circuit techniques, a new style of CAD tools, high-performance chip interfaces, and advanced packaging techniques for high-power microprocessors.

Microprocessor-Based Memory Device for Ambulatory Heart Rate and Physical Activity Recording

Using microprocessor techniques, a portable digital memory device has been designed for the ambulatory monitoring of heart rate and physical activity. The device consists of a microprocessor, an ECG amplifier to record the heart rate and an accelerometer to detect the physical activity. This accelerometer is piezo-resistive and is suitable for ambulatory physical activity recording, because this sensor requires low electrical power, has high durability and wide frequency response (DC approximately 1.2 kHz). Changes in heart rates and physical activity in daily life have been successfully recorded.

A 300-MHz 115-W 32-b bipolar ECL microprocessor

A full-custom single-chip bipolar ECL RISC microprocessor was implemented in a 1.0- mu m single-poly bipolar technology. This research prototype contains a CPU and on-chip 2-KB instruction and 2-KB data caches. Worst-case power dissipation with a nominal -5.2 V supply is 115 W. The chip has been designed for a worst-case clock frequency of 275 MHz at a nominal supply. The chip verifies a new style of CAD tools developed during the design process, advanced packaging techniques for high-power microprocessors, and VLSI ECL circuit techniques. >

Development and application of a computer control system for an analytical electron microscope

The authors deal with the use of microprocessor techniques in the field of electron microscopy, in particular with the computer control of an analytical electron microscope (AEM) and the digital recording of the image. The design of a comprehensive computer control system is outlined, which has been developed to carry out most of the electron-optical functions of the AEM. For example, computer control of the high-voltage supply can be useful in electron energy loss spectroscopy, with a resolution of 2 eV. Initial results of application are given to demonstrate the performance of the system. Its ability to be used in combination with a digital image acquisition system is shown.

Microprocessor technique in gas purification equipment

Microprocessor technique in gas purification equipment

Symbiosis of microprocessor and film techniques in X-ray diffractometry

A two-axis X-ray diffractometer run by a microprocessor and equipped with a climbing detector to cover the upper hemisphere was provided with the option of exchanging the point detector with flat or cylindrical film cassettes. By synchronisation of the specimen rotation and the film motion, Weissenberg-type and other exposures are obtained. Various choices of the relative motions may be used to focus the attention on selected parts of the reciprocal space, which may be magnified and reshaped. The importance and convenience of being able to perform film and point detector studies on the same instrument and at any temperature are pointed out.

Quantitative analysis of coronary arteriograms by microprocessor cinevideodensitometry.

A rapid microprocessor technique for measuring the cross-sectional area, diameter, and relative percentage stenosis of coronary atherosclerotic lesions by cinevideodensitometric analysis was developed and validated. Video images of projected 35-mm coronary arteriographic cine frames were analyzed from cinevideodensitometric profile curves recorded for the catheter shaft, normal artery, and stenotic segment. In radiographic phantom studies of calibrated, contrast-filled, plexiglass cylinders, cinevideodensitometric measurements correlated linearly with percentage relative stenosis (r = 0.98; SEE = 4.1%), diameter (r = 0.99; SEE = 0.12 mm), and cross-sectional area (r = 0.99; SEE = 0.32 mm2). In postmortem studies of two patients dying after coronary arteriography, cross-sectional areas of arterial segments measured by cinevideodensitometry correlated well (r = 0.99; SEE = 0.71 mm) with areas of acrylic resin casts of the coronary arteries. Intraobserver variability (r = 0.99; SEE = 2.6%) and interobserver variability (r = 0.96; SEE = 5.3%) of cinevideodensitometric measurements of coronary arteriograms were low. Additionally, percentage relative stenosis measured in the right anterior oblique projection correlated well with measurements in the left anterior oblique projection (r = 0.98; SEE = 0.11 mm2) of patients with eccentric stenotic lesions. Lastly, cinevideodensitometric measurements were significantly (p less than 0.05) more reproducible than caliper measurements. This inexpensive dedicated microprocessor system provides rapid cinevideodensitometric measurements of coronary arterial dimensions, without requiring manual tracing of arterial segments or the major expense of a main-frame computer system.

X-ray diffraction using combined film and microprocessor techniques

X-ray diffraction using combined film and microprocessor techniques