Microprocessor-based Hardware Research Articles

Coexisting Infinite Orbits in an Area-Preserving Lozi Map.

Extreme multistability with coexisting infinite orbits has been reported in many continuous memristor-based dynamical circuits and systems, but rarely in discrete dynamical systems. This paper reports the finding of initial values-related coexisting infinite orbits in an area-preserving Lozi map under specific parameter settings. We use the bifurcation diagram and phase orbit diagram to disclose the coexisting infinite orbits that include period, quasi-period and chaos with different types and topologies, and we employ the spectral entropy and sample entropy to depict the initial values-related complexity. Finally, a microprocessor-based hardware platform is developed to acquire four sets of four-channel voltage sequences by switching the initial values. The results show that the area-preserving Lozi map displays coexisting infinite orbits with complicated complexity distributions, which heavily rely on its initial values.

Study of Application Layer MQTT Protocol with Assessment & Comparison of Hardware to Enable IOT

The tiny sensors used in roaring technology era is composed of the power supply with, computing facilities & communication of data with a network of the internet. Transfer of data among things can be materialized through lightweight, cheap and low bandwidth application layer protocol for which MQTT is the right choice. This protocol will publish-subscribe the topics via host performing as the server also termed as a broker. In this article, an ESP NodeMCU microprocessor-based hardware module with limited computing abilities is used along with numerous real-time analog and digital sensors. Interfacing of all these temperature, humidity & motion sensors has been described. For transmitting-receiving and routing of data was done through MQTT protocol. The bunch of devices communicating with each other emulates attest bed for the machine to machine communication which gets further enhanced to industry 4.0. The sensors provide condition based monitoring system and get the data to the subscribed clients on a smartphone or web-based service.

Biologically Inspired Components in Embedded Vision Systems

Biological vision components like visual attention (VA) algorithms aim to mimic the mechanism of the human vision system. Often VA algorithms are complex and require high computational and memory requirements to be realized. In biologically-inspired vision and embedded systems, the computational capacity and memory resources are of a primary concern. This paper presents a discussion for implementing VA algorithms in embedded vision systems in a resource constrained environment. The authors survey various types of VA algorithms and identify potential techniques which can be implemented in embedded vision systems. Then, they propose a low complexity and low memory VA model based on a well-established mainstream VA model. The proposed model addresses critical factors in terms of algorithm complexity, memory requirements, computational speed, and salience prediction performance to ensure the reliability of the VA in a resource constrained environment. Finally a custom softcore microprocessor-based hardware implementation on a Field-Programmable Gate Array (FPGA) is used to verify the implementation feasibility of the presented model.

This Is Not a Computer: Negotiating the Microprocessor

The Intel 4004 μ-Computer is the earliest known microprocessor-based hardware distributed by Intel. This article relates the information concerning the 4004 μ-Computer in an effort to gain a more complete historical perspective on the liminal period in the corporate history of Intel when, soon after the introduction of its first microprocessor, the company was wrestling with the one-chip CPU--computer or component? dilemma and tried to position itself in the emerging microcomputing market that it helped to create.

Low memory visual saliency architecture for data reduction in wireless sensor networks

Traditionally, to reduce communication overheads because of bandwidth limitations in wireless sensor networks (WSNs), image compression techniques are used on high-resolution captures. Higher data reduction rates can be achieved by first removing redundant parts of the capture prior to the application of image compression. To locate these redundant parts, biologically plausible visual saliency processing is used to isolate parts that seemed important based on visual perception. Although visual saliency proves to be an effective method in providing a distinctive difference between important and unimportant regions, computational complexity and memory requirements often impair implementation. This study presents an implementation of a low-memory visual saliency architecture with reduced computation complexity for data reduction in WSNs through salient patch transmission. A custom softcore microprocessor-based hardware implementation on a field programmable gate array is then used to verify the architecture. Real-time processing demonstrated that data reductions of more than 50% are achievable for simple to medium scenes without the application of image compression techniques.

Very Low-Memory Wavelet Compression Architecture Using Strip-Based Processing for Implementation in Wireless Sensor Networks

This paper presents a very low-memory wavelet compression architecture for implementation in severely constrained hardware environments such as wireless sensor networks (WSNs). The approach employs a strip-based processing technique where an image is partitioned into strips and each strip is encoded separately. To further reduce the memory requirements, the wavelet compression uses a modified set-partitioning in hierarchical trees (SPIHT) algorithm based on a degree-0 zerotree coding scheme to give high compression performance without the need for adaptive arithmetic coding which would require additional storage for multiple coding tables. A new one-dimension (1D) addressing method is proposed to store the wavelet coefficients into the strip buffer for ease of coding. A softcore microprocessor-based hardware implementation on a field programmable gate array (FPGA) is presented for verifying the strip-based wavelet compression architecture and software simulations are presented to verify the performance of the degree-0 zerotree coding scheme.

Improvements in ground-fault protection of unit-connected generator stator winding using laboratory test environment

This paper describes an idea of realization of a software–hardware laboratory environment enabling to run research and implementation in the area of ground-fault protection of modern unit-connected generators. There are three basic elements in this environment: simulation model of a unit-connected generator for investigating intermittent arc ground-faults in generator stator winding, PC-based system for ground-fault waveforms synthesis and microprocessor-based hardware for implementation of a new protection algorithm developed by authors.

Development and analysis of novel soft-starter∕energy-saver topology for delta-connected induction motors

A thyristorised star/delta switch is proposed as a soft starter and energy saver for delta-connected induction motor drives. A low-cost microprocessor-based hardware is developed and used for the control of the star/delta switch. The use of the star/delta switch for starting is first explained followed by its application as an energy saver. Three schemes of switching transitions are proposed and implemented for the star (delta) to delta (star) changeover process. Extensive simulation and experimental results are presented to show that the proposed circuit is a promising candidate as a starter/energy saver for delta-connected induction motor drives.

ECG data reduction method for medical telemetry systems.

In current medical practice, all transmitters used for monitoring an ECG send data continuously. If transmission could be limited to only the ECG data that requires the attention of a technician, the likelihood of interference and power consumption would be reduced considerably. In this paper, we propose a new ECG telemetry system. The transmitter has a simple ECG analyzer and it only transmits data when abnormal waveforms are detected. As part of this system, we propose a simple algorithm to detect an abnormal ECG. The algorithm is composed of a baseline drift canceller (utilizing a moving average calculation), a waveform detector (using a modified second order derivative) and an ECG analyzer. In order to test the effectiveness and feasibility of the algorithm, computer simulations (with a MIT-BIH ECG database) and experiments (with microprocessor-based hardware) were performed. The results of the simulations show that the detection performance and data compression performance of the algorithm are adequate. The results of the experiment show that the algorithm even performs adequately when used with microprocessor-based hardware that is of limited size or limited power consumption.

Expert Self-Tuning PI(D) Controller

The development of a self-tuning PI(D) controller is discussed in this paper. The controller is based on an expert system approach using the pattern recognition technique. The unique features of the controller developed are :(i) the incorporation of knowledge relating to a simple identification technique for the process characteristic parameter through observation of two closed loop load responses of the process under normal PI(D) control action and (ii) selection of P, I and D settings based on minimum integrated error (IE) criterion. The paper dicusses new theoretical results on the parametrisation of P, I, and D settings for minimum IE criterion in terms of process characteristic ratio, the technique used for the process identification, and the microprocessor-based hardware and software implementation of the self-tuning controller together with the results of tests conducted on the developed controller using a laboratory type pilot process.

High precision phase measurement using reduced sine and cosine tables

A high-precision phase measurement technique, which can accurately determine the phase even when the signals are distorted by harmonics, was presented previously by the author (ibid., vol.38, p.954-60, Oct. 1989). He proposes a microprocessor-based hardware implementation of the technique. The hardware implementation requires two reduced tables: a sine table and a cosine table. If each table has i(i+5)/2 entries, then the phase can be accurately determined even if the signals are distorted by any number of harmonics in the range of second through ith harmonics.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

A microprocessor-based dot matrix display system for Japanese Hiragana syllables

A microprocessor-based 5*7 dot-matrix display system for Japanese Hiragana syllables is proposed. The dot-matrix layout for each of the 68 syllables is shown. The syllable generation or the selective dots to produce a display is accomplished using a column approach, i.e. 7 dots (comprising one column) are displaced at a time with proper multiplexing, the display of each syllable is completed in 5 steps. A complete Hiragana word typically comprises one to four syllables. A four-syllable string (i.e., four 5*7 dot-matrix displays) display system is therefore proposed. The organization of the microprocessor-based hardware for such a display system is discussed and the system flowchart is given. Each character in the string is presented as a 7-bit ASCII code to the microprocessor. A program compares the character string that is input and selects the appropriate Hiragana syllables for display from a look-up table of bit patterns stored in memory. As each Hiragana syllable requires (5*7)+35 dots (or bits), five bytes of data are used to represent one syllable, ignoring the last bit of each byte. To represent the full 68 Hiragana syllables, a total of 340 bytes of memory locations are required.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Parallel processor algorithm for power system simulation

The paper considers real-time simulation over the operational timescales in an electrical power system and presents a mathematical technique for the decomposition of a set of nonlinear algebraic and differential equations, which result from the corresponding dynamic model. It is shown that the resulting algorithm is suitable for implementation on parallel processors with a 32-bit word capability. The results illustrate that the proposed decomposition technique results in a significant saving in simulation elapsed time, and can consequently be applied to the real-time simulation of large power systems, using relatively inexpensive microprocessor-based hardware.

Computer Controlled Pneumatic Servo Drives

This paper describes how microprocessor-based controls can be used to produce low cost pneumatic servo drives which could find wide application in manufacturing industries. The approach incorporates digital compensation for system non-linearities so that, when positioning loads in a ‘point to point’ mode, it is possible to achieve a significant improvement in both the static and dynamic performance of the drive. For the compensation algorithms implemented a theoretical foundation is presented based on a linearized model of pneumatic drives. The paper also describes how microprocessor-based hardware and software have been constructed to evaluate performance criteria. This test facility has allowed the software implementation of the compensation algorithms to be refined so that satisfactory performance can be achieved with both translational and rotational drives utilizing various forms of transmission. The test facility has also allowed various control system elements to be evaluated so that pneumatic drives suitable for industrial application, can be specified.

Computer graphics with computerized tomography for functional neurosurgery.

A computer graphics technique for computer-assisted stereotactic surgery is presented. The program is designed to aid the surgeon by presenting an on-line graphics display of stereotactic probes and electrodes superimposed on cross sections of the human brain stem. This technique simulates an otherwise blind surgical procedure on a graphics screen for use during surgery. An earlier system based around the DEC MINC-11 BA computer system has been used by the authors for the performance of stereotactic surgery with conventional ventriculography. This system has been upgraded and is now configured about an even more compact microprocessor-based hardware system with expanded graphics capabilities, which also allows its use with computerized tomography.

Microprocessor-based controls for drilling — retrofitting aspects

This paper considers the updating of NC (numerical control) machine tools with control systems demonstrating modern features. To illustrate such machine tool retrofitting, the paper describes the structure of microprocessor-based hardware and software which was developed to achieve improved control of a first generation NC drilling machine.