Microelectronics Group Research Articles

Latency study of the High Performance Time to Digital Converter for the ATLAS Muon Spectrometer trigger upgrade

The High Performance Time to Digital Converter (HPTDC), a multi-channel ASIC designed by the CERN Microelectronics group, has been proposed for the digitization of the thin-Resistive Plate Chambers (tRPC) in the ATLAS Muon Spectrometer Phase-1 upgrade project. These chambers, to be staged for higher luminosity LHC operation, will increase trigger acceptance and reduce or eliminate the fake muon trigger rates in the barrel-endcap transition region, corresponding to pseudo-rapidity range 1<|η|<1.3. Low level trigger candidates must be flagged within a maximum latency of 1075 ns, thus imposing stringent signal processing time performance requirements on the readout system in general, and on the digitization electronics in particular. This paper investigates the HPTDC signal latency performance based on a specially designed evaluation board coupled with an external FPGA evaluation board, when operated in triggerless mode, and under hit rate conditions expected in Phase-I. This hardware based study confirms previous simulations and demonstrates that the HPTDC in triggerless operation satisfies the digitization timing requirements in both leading edge and pair modes.

Simulation of the High Performance Time to Digital Converter for the ATLAS Muon Spectrometer trigger upgrade

The ATLAS Muon Spectrometer endcap thin-Resistive Plate Chamber trigger project compliments the New Small Wheel endcap Phase-1 upgrade for higher luminosity LHC operation. These new trigger chambers, located in a high rate region of ATLAS, will improve overall trigger acceptance and reduce the fake muon trigger incidence. These chambers must generate a low level muon trigger to be delivered to a remote high level processor within a stringent latency requirement of 43 bunch crossings (1075 ns). To help meet this requirement the High Performance Time to Digital Converter (HPTDC), a multi-channel ASIC designed by CERN Microelectronics group, has been proposed for the digitization of the fast front end detector signals. This paper investigates the HPTDC performance in the context of the overall muon trigger latency, employing detailed behavioral Verilog simulations in which the latency in triggerless mode is measured for a range of configurations and under realistic hit rate conditions. The simulation results show that various HPTDC operational configurations, including leading edge and pair measurement modes can provide high efficiency (>98%) to capture and digitize hits within a time interval satisfying the Phase-1 latency tolerance.

Triroc: A Multi-Channel SiPM Read-Out ASIC for PET/PET-ToF Application

Triroc is the latest addition to SiPM readout ASICs family developed at Weeroc, a start-up company from the Omega microelectronics group of IN2P3/CNRS. This chip is developed under the framework TRIMAGE European project which is aimed for building a cost effective tri-modal PET/MR/EEG brain scan. To ensure the flexibility and compatibility with any SiPM in the market, the ASIC is designed to be capable of accepting negative and positive polarity input signals. This 64-channel ASIC, is suitable for SiPM readout which requires high accuracy timing and charge measurements. Targeted applications would be PET prototyping with time-of-flight capability. Main features of Triroc includes high dynamic range ADC up to 2500 photoelectrons and TDC fine time binning of 40 ps. Triroc requires very minimal external components which means it is a good contender for compact multichannel PET prototyping. Triroc is designed by using AMS $0.35 ~\mu\hbox{m}$ SiGe technology and it was submitted in March 2014. The detail design of this chip will be presented.

Development of a transparent photon detector for the online monitoring of IMRT beams

Introduction External beam radiotherapy performance has been increased by the emergence of state-of-the-art techniques, which improve local irradiation while preserving surrounding organs. They require consistent Quality Assurance (QA) programs, supported by Electronic Portal Imaging Devices and Dynalog files. Nevertheless, they do not enable accurate dose-monitoring during online delivery sessions. In the framework of the INSPIRA project, the DAMe group, in collaboration with the Radiotherapy Department of CHUG, is developing an innovative Transparent Detector for Radiotherapy (TraDeRa). The beam modulated by the Multileaf Collimator will be monitored ahead of the patient, in real-time, without dead zone. Material and methods Current version of this detector is a 1:4 scale prototype, partially instrumented. Basically, it consists in a matrix of ionization chambers. First, we measured the dose with a PTW 0.3 cc ionization chamber, in standard conditions, with and without embedding TraDeRa, to quantify detector-induced attenuation. Then, the detector was irradiated using a 14 square cm beam. Inhouse front-end electronics allows the amplitude of each pulse to be extracted, providing dose rate at the pulse scale. Finally, TraDeRa was irradiated with a 3 mm sliding slit. A real-time map of the signal every 50 ms is provided. Results The detector induces a 0.6% attenuation of the beam. Global accuracy and stability of TraDeRa was verified. We highlighted dose rate noticeable variations during the irradiation. Amplitudes of delivered pulses vary around 5% of the mean value, and up to 25% for the first pulse. Accurate monitoring of leaf position was obtained. The interleaf leakage appears clearly and represents a non-negligible contribution to the dose. Recently, a specific integrated circuit has been designed by the LPSC microelectronics group. It represents a key-step for the forthcoming embedded electronics. Conclusion The current version of TraDeRa already shows promising results for IMRT-QA. It is quite transparent so that it does not hinder the irradiation, while keeping the beam upstream of the patient under constant control. It will offer both suitable precision on 2D-beam characterization and real-time measurements at the pulse scale or every 50 ms. The development of the final prototype, with all embedded electronics, is in progress and is expected by the end of 2013.

Latest generation of ASICs for photodetector readout

The OMEGA microelectronics group has designed a new generation of multichannel integrated circuits, the “ROC” family, in AustrianMicroSystem (AMS) SiGe 0.35μm technology to read out signals from various families of photodetectors. The chip named MAROC (standing for Multi Anode ReadOut Chip) has been designed to read out MultiAnode Photomultipliers (MAPMT), Photomultiplier ARray In SiGe ReadOut Chip (PARISROC) to read out Photomultipliers (PMTs) and SiPM Integrated ReadOut Chip (SPIROC) to readout Silicon PhotoMultiplier (SiPM) detectors and which was the first ASIC to do so.The three of them fulfill the stringent requirements of the future photodetectors, in particular in terms of low noise, radiation hardness, large dynamic range, high density and high speed while keeping low power thanks to the SiGe technology.These multi-channel ASICs are real System on Chip (SoC) as they provide charge, time and photon-counting information which are digitized internally. Their complexity and versatility enable innovative frontier detectors and also cover spin off of these detectors in adjacent fields such as medical or material imaging as well as smart detectors.In this presentation, the three ASIC architectures and test results will be described to give a general panorama of the “ROC” chips.

Measurement of arrival time of particles in extensive air showers using TDC32

Arrival time of particles in an extensive air shower (EAS) is a key physical parameter to determine its direction. EAS direction is useful for studies of anisotropy and composition of cosmic rays, and search for multi- TeV γ -rays sources. Accurate timing may be used to search exotic phenomena such as production of new particles at extremely high energies available during early stages of development of EAS and also for detecting sub-relativistic hadrons in EAS. Time to digital converters (TDCs) are used to perform this task. Traditional TDCs operate in the START-STOP mode with limited dynamic range and single-hit capability. With the advent of high luminosity collider LHC, need for TDCs with large dynamic range, multi-hit capability and TRIGGERED mode of operation became necessary. A 32 channel TDC was designed for the GRAPES-3 experiment on a CAMAC platform around TDC32, an ASIC developed by micro-electronics group at CERN, Geneva. Four modules were operated in the GRAPES-3 experiment. Here, we present details of the circuit design and their performance over several years. The multi-hit feature of this device was used to study the time structure of particles in the EAS on time scale of ∼1 μs. The distribution of time intervals in the

Study for the LHCb upgrade read-out board

The LHCb experiment envisages to upgrade its readout electronics in order to increase the readout rate from 1 MHz to 40 MHz. This electronics upgrade is very challenging, since readout boards will have to handle a higher number of serial links with an increased bandwidth. In addition, the new communication protocol (GBT) developed by the CERN micro-electronics group mixes data acquisition, slow control and clock distribution on the same link. To explore the feasibility of such a readout system, elementary building blocks have been studied. Their goals are multiple: understand signal integrity when using highly integrated high speed serial links running at 8 - 10 Gbits/s; test the implementation of the GBT protocol within FPGAs; understand advantages and limitations of commercial standard with a predefined interconnection topology; validate ideas on how to control easily such a system. We designed two boards compliant with the xTCA standard which meets an increasing interest in the physics community. The first one is a generic handling 32 high speed serial links. The second one is a communication switch allowing the generic boards to communicate together. In this paper, we present jitter measurements obtained at 8 Gbits/s on serial link. We describe the versatility of this architecture which can be tuned from basic acquisition systems to more high-end complex ones. Finally, we demonstrate the feasibility of a low cost scalable control system based on NIOS core embedded in FPGAs.

A high-throughput, multi-channel photon-counting detector with picosecond timing

High-throughput photon counting with high time resolution is a niche application area where vacuum tubes can still outperform solid-state devices. Applications in the life sciences utilizing time-resolved spectroscopies, particularly in the growing field of proteomics, will benefit greatly from performance enhancements in event timing and detector throughput. The HiContent project is a collaboration between the University of Leicester Space Research Centre, the Microelectronics Group at CERN, Photek Ltd., and end-users at the Gray Cancer Institute and the University of Manchester. The goal is to develop a detector system specifically designed for optical proteomics, capable of high content (multi-parametric) analysis at high throughput. The HiContent detector system is being developed to exploit this niche market. It combines multi-channel, high time resolution photon counting in a single miniaturized detector system with integrated electronics. The combination of enabling technologies; small pore microchannel plate devices with very high time resolution, and high-speed multi-channel ASIC electronics developed for the LHC at CERN, provides the necessary building blocks for a high-throughput detector system with up to 1024 parallel counting channels and 20 ps time resolution. We describe the detector and electronic design, discuss the current status of the HiContent project and present the results from a 64-channel prototype system. In the absence of an operational detector, we present measurements of the electronics performance using a pulse generator to simulate detector events. Event timing results from the NINO high-speed front-end ASIC captured using a fast digital oscilloscope are compared with data taken with the proposed electronic configuration which uses the multi-channel HPTDC timing ASIC.

The firm/territory relationships in the globalisation: towards a new rationale

– The aim of this paper is the presentation of an approach of firms-territories relationships in terms of firms' nomadism and territorial anchorage of technological and industrial activities. Such an approach is founded on the necessity to overcome the “volatile” firm's level of analysis, in which firm's mobility is investigated from the sole point of view of the leaven location. On the contrary, it should be relevant to focus on the firm's dynamics through its connections with the whole set of territories and to conceive the firm-territory relation as a result of the dialectic confrontation of the respectively concerned firm and territory both dynamics, both trajectories. Hence we are led to characterise the localised industrial unit as placed at the crossroad of a triple link: with a firm (or a group), with an industry and with a territory. Such a threefold coupling relies on proximity's effects, alternately from organisational and geographical nature, whose conjunction generates territorial anchoring and leads to the notion of productive encounter, in the sense of a capacity to formulate and give solutions to productive issues, within the context of firm-territory relationship. In terms of formal models, research works are at the very first step. Nevertheless, an approach in terms of “small worlds” seems to present very fruitful perspectives. We develop the foundations of such an approach and expose how it can provide a good framework to explain territorial anchorage and, more widely, the strength of clusters. A concrete illustration is extensively developed about SGS-Thomson Microelectronics group with regard to its productive site in Rousset, in the French Bouches-du-Rhone district. Classification Codes: L23, L63, O18, R3, R58.

HX2: a 16-channel charge amplifier IC for the read-out of X-ray detectors

RAL Microelectronics Group has developed a 16-channel multiplexed charge amplifier IC (HX2) for the read-out of cadmium telluride X-ray detectors. The IC has been incorporated into a prototype X-ray imaging system intended for non-destructive production line monitoring. The HX2 contains an array of 16 integrating amplifiers, each with a 10 pF feedback capacitor, and a dynamic range of 20 pC. The integration period can be varied over the range /spl sim/5 /spl mu/s to /spl sim/100 ms. In order to extend its range of applications, HX2 was designed with two modes of operation. In the first mode, the integration period is followed by the read-out period where the 16 channels are multiplexed onto an analogue output bus. The next integration period starts when this read-out has finished. In the second mode, the read-out of the voltages from one integration period takes place during the subsequent integration period. This overlapping of integration and read-out periods reduces the dead time of the HX2. The IC has a signal-to-noise ratio which is typically above 10000:1, and is suitable for the high-resolution read-out of other detector systems, such as photodiode arrays. The dual-mode operation allows it to work with detectors producing either continuous or pulsed currents.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

VLSI design training and education in the University of Cantabria within EUROCHIP

The VLSI design training program developed at the University of Cantabria is presented. The participation of this University in the EUROCHIP VLSI Design Action has meant incorporating the training in VLSI circuit design and testing into the different curricula taught in the University. This was made possible thanks to the previous experience of the Microelectronics Group in these fields. The changes made to adapt and extend the existing program for undergraduate students are described. These chip involve not only course content and proposals for practical work but also changes to laboratories to make this feasible. >

Evaluation of damage to MOS devices fabricated on dry etched substrates: J C Carter and A G R Evans, Microelectronics Group, Department of Electronics, Southampton University, Southampton, UK

Evaluation of damage to MOS devices fabricated on dry etched substrates: J C Carter and A G R Evans, Microelectronics Group, Department of Electronics, Southampton University, Southampton, UK

Book Review: Microelectronics: Capitalist Technology and the working Class, CSE Microelectronics Group. London: CSE Books

Book Review: Microelectronics: Capitalist Technology and the working Class, CSE Microelectronics Group. London: CSE Books

Word Processing and the Transformation of the Patriarchal Relations of Control in the Office

This paper was initially written in December 1978 for discussion with the CSE Microelectronics Group . It has been expanded and re-written in the light of subsequent discussions and comments from many individuals, and especially the CSE Microelectronics Group and the Capital and Class editorial group . We would like to thank the CSE Microelectronics Group for providing the original impetus for this paper and encouragement to publish it . We are also indebted to both the CSE and the London Microelectronics Group for the wide ranging discussion on research and information presented by other people which has helped in our understanding of what we see as one of the crucual political problems facing the working class today . The word processor is making an impact on offices all over the country in both the public and the private sectors . The introduction of microelectronically controlled word processors constitutes the first major attempt at office rationalisation since the introduction of the typewriter in the 1870s . This paper seeks to chart the shift in office organisation by taking a historical look at the entry of women into the office, the culture of the office and, finally examining the rationale behind the introduction of word processors and their potential impact .