Microcrystalline Silicon Thin Film Transistors Research Articles

P-1.9: Characterization of Self-Aligned Top-Gate Microcrystalline Silicon Thin Film Transistors

P-1.9: Characterization of Self-Aligned Top-Gate Microcrystalline Silicon Thin Film Transistors

Improved microcrystalline silicon and gate insulator interface with a pad/buffer structure

This research proposes an amorphous silicon pad layer to protect a gate insulator from being bombarded by subsequent plasma processing. This potentially improves the fabrication of inverted stagger microcrystalline silicon thin-film transistors (TFTs) at low temperatures (200°C). The pad layer can suppress the gate leakage current effectively. Further, depositing a thin microcrystalline silicon buffer layer on the pad provides seeds for crystallized silicon channel deposition. Following subsequent deposition, it was observed that the buffer layer can induce the pad layer for re-crystallization to produce a microcrystalline silicon TFT with a flat gate insulator/channel interface.

Electrical Stability of High-Mobility Microcrystalline Silicon Thin-Film Transistors

The electrical stability of high-mobility microcrystalline silicon (μc -Si:H) thin-film transistors (TFTs) was investigated and compared to amorphous silicon (a-Si:H) TFTs. Under prolonged bias stress the microcrystalline silicon TFTs exhibit an improved electrical stability compared to amorphous silicon TFTs. The microcrystalline silicon TFTs were prepared by plasma-enhanced chemical vapor deposition at temperatures compatible with flexible substrates. The realized microcrystalline silicon transistors exhibit electron charge carrier mobilities exceeding 30 cm2/V·s. Prolonged operation of the transistors leads to a shift of the threshold voltage towards positive and negative gate voltages depending on the gate biasing conditions (positive or negative gate voltage). The shift of the threshold voltage increases with increasing positive and negative gate bias stress. The behavior is fundamentally different from the behavior of the amorphous silicon TFTs, which exhibit only a shift of the threshold voltage towards positive gate voltages irrespective of the polarity of the gate bias stress. The threshold voltage shift of the microcrystalline silicon TFTs saturates after a few minutes to a few hours, depending on the gate voltage. After prolonged bias stress, a recovery of the initial threshold voltage is observed without any thermal annealing or biasing of the transistors, which is not the case for the measured amorphous silicon TFTs.

(Invited) Similarities between µc-Si TFT with Very Thin Active Layer and FD-SOI FETs

The subthreshold slope of microcrystalline silicon Thin Film Transistor is shown to be highly improved when the thickness of the active layer is enough decreased. In the same manner, the threshold voltage of these TFTs with very thin active layer is shown to be controlled dynamically with high efficiency by a second gate in front of the first one. These behaviours are explained considering the similarities between these TFTs and fully depleted SOI-MOSFETs as well as with dual-gate SOI-MOSFETS.

Highly controllable dual-gate microcrystalline silicon thin film transistor processed at low temperature ( T < 180 °C)

The addition of a top-gate to a bottom gate microcrystalline silicon thin film transistor (TFT) that is processed at a maximum temperature of 180 °C, is shown to lead to a very efficient control of the threshold voltage V TH. A real time control of CMOS pairing is then possible. The value of the coupling coefficient that is the ratio of the variation of V TH on the variation of the voltage of the top-gate control is 0.7. This efficient control is mainly due to the use of very thin, 50 nm thick, active layer and to its electrical quality that leads to a full depletion.

High mechanical and electrical reliability of bottom-gate microcrystalline silicon thin film transistors on polyimide substrate

Bottom-gate microcrystalline silicon thin film transistors (μc-Si:H TFTs) were fabricated by conventional 13.56 MHz RF plasma-enhanced chemical vapor deposition at 200 °C. In the high pressure depletion regime, the deposition rate of the μc-Si:H film is 24 nm/min and the amorphous incubation layer near the μc-Si:H/silicon nitride interface is unobvious. The crystalline fraction of μc-Si:H film with the thickness of 50 nm is 71%. From nano beam electron diffraction, the μc-Si:H film has a better crystalline order within a short-range lattice structure. The lattice parameter was measured to be 3.1 Å, which reflecting the lattice plane has a (111) direction. Finally, the μc-Si:H film was used as the active layer in TFTs structure. The field effect mobility, subthreshold swing and the threshold voltage are 0.95 cm 2/V, 0.85 V/dec. and 2.05 V, respectively. The output characteristic also shows no evidence of current crowing at low drain-source voltage ( V ds), implying good contact properties achieved with the n + a-Si:H source-drain ohmic contact layer. After 70 h 1 μA constant current stress, the threshold voltage shifts are 4.44 V and 0.42 V for the a-Si:H TFT and μc-Si:H TFT, respectively. The μc-Si:H thin film transistors show a better electrical stability than the amorphous silicon thin film transistors because of the lower defect density in the μc-Si:H film.

High On/Off-Current Ratio in Bottom-Gated Microcrystalline-Silicon Thin-Film Transistors With Vertical-Offset Structure

The high on/off-current ratio of microcrystalline-silicon thin-film transistors (TFTs) with vertical offset was demonstrated. These TFTs have a bottom-gate structure and offset regions formed along the side surfaces of the thick interlayer films. Due to a decrease of maximum electric-field intensity and a narrow distribution of high electric field, the on/off current ratio of vertical-offset TFTs is about three orders of magnitude higher than that of conventional TFTs.

Microcrystalline silicon thin-film transistors operating at very high frequencies

The switching behavior of hydrogenated microcrystalline silicon thin-film transistors (TFTs) was examined and switching frequencies exceeding 20 MHz were measured for short channel devices. The microcrystalline silicon TFTs were prepared by plasma-enhanced chemical vapor deposition at temperatures compatible with plastic substrates. The realized microcrystalline silicon transistors exhibit high electron charge carrier mobilities of 130 cm2/V s. The switching frequency is limited by the contact resistances and overlap capacitances between the gate and the drain/source electrodes. Switching frequencies larger than 20 MHz were measured for transistors with a channel length of 5 μm. The high switching frequencies facilitate the realization of radio-frequency identification tags operating at 13.56 MHz.

The feasibility of using an Al-alloy film as the source/drain electrode in a microcrystalline silicon thin-film transistor

An n + -doped-layer-free microcrystalline silicon thin-film transistor (μc-Si TFT) with Al alloy as the source/drain (S/D) electrode was fabricated and investigated. The device showed a field-effect mobility of 0.28 cm 2/V s and a threshold voltage of 5.3 V. The mobility measured in the linear regime was found to be roughly similar to that calculated in the saturation regime for the same device. Compared to a μc-Si TFT with an n + -doped layer, the μc-Si TFT with Al alloy as the S/D electrode exhibited similar electrical performance. This indicated that a good contact exists between the Al-alloy film and microcrystalline silicon. Our result also showed that using Al alloy as the S/D electrode is an effective way to substitute the n + -doped layer in a μc-Si TFT.

Low temperature processed p‐type bottom gate microcrystalline silicon thin film transistors

AbstractWe report on processing of p‐type bottom gate microcrystalline silicon thin film transistors (p‐type BG TFT). In particular, we demonstrate that a thermal annealing at 250 °C is required to get ideal contacts, regardless of the drain‐source met al. We found that aluminium is the best suited metal for source and drain contacts, as in the case of n‐type thin film transistors.The TFTs mobility and sub‐threshold slope (V/dec) are improved when a hydrogen plasma treatment was applied to the a‐SiN:H prior to µc‐Si deposition. Our best p‐type BG TFTs exhibit a field effect mobility of ∼ 1.2 cm2/Vs, a sub threshold slope of ∼1V/dec and an ON/OFF ratio of 105 while keeping a stable threshold voltage (© 2010 WILEY‐VCH Verlag GmbH &amp; Co. KGaA, Weinheim)

Characterization of Microcrystalline Silicon Thin Film Transistors Fabricated by Thermal Plasma Jet Crystallization Technique

The electrical characteristics of thin-film transistors (TFTs) fabricated by thermal plasma jet (TPJ)-crystallized microcrystalline Si (µc-Si) films have been investigated. Amorphous Si (a-Si) films were crystallized with the TPJ under the scanning speed (v) of 350 to 550 mm/s, and µc-Si TFTs were successfully fabricated with a 300 °C process. By reducing v, µFE increases from 3.2 to 17.1 cm2 V-1 s-1, and Vth and S decrease from 9.2 to 5.2 V and 1.3 to 0.6 V/decade, respectively. The variations of µFE, Vth, and S were kept within small values of 1.06 (±4.4%), 0.14 (±1.1%), and 0.04 (±4.0%), respectively. The µc-Si is formed with ∼20-nm-sized randomly oriented small grains, and this isotropic nature results in very small variation of TFT performance. With decreasing v, the fraction of nano sized grains and disordered bonds at the grain boundary decreases, which results in improved TFT performance.

Modelling of contact effects in microcrystalline silicon thin-film transistors

Hydrogenated microcrystalline silicon has recently emerged as a promising material system for large-area electronic applications such as thin-film transistors and solar cells. In this paper, thin-film transistors based on microcrystalline silicon were realized with charge carrier mobilities exceeding 40 cm2/Vs. The electrical characteristics of the microcrystalline silicon thin-film transistors are limited by the influence of contact effects. The influence of the contact effects on the charge carrier mobility was investigated for transistors with different dimensions of the drain and source contacts. The experimental results were compared to an electrical model which describes the influence of the drain and source contact dimension on the transistor parameters. Furthermore, the Transmission Line Method was applied to investigate the contact effects of the thin-film transistors with different drain and source contact dimensions. Finally, optimized device geometries like the channel length of the transistor and dimension of the drain and source contacts were derived for the microcrystalline transistors based on the electrical model.

Issues in Microcrystalline Silicon TFTs Processed at T

Review of results on microcrystalline silicon thin film transistors is given with emphasis on main issues to get both higher stability and mobility TFTs than that of amorphous silicon transistors. High crystalline fraction with columnar structure is shown to lead to high mobility without stability when using silicon dioxide as gate insulator, or stable TFTs with low mobility when using silicon nitride as gate insulator. Un-stability originates from oxygen that diffuses in defected column boundaries. Using denser structure as crystalline grains embedded in amorphous matrix can lead to TFTs with enough stability and mobility.

High-mobility microcrystalline silicon thin-film transistors prepared near the transition to amorphous growth

Thin-film transistors (TFTs) are core elements of novel display media on rigid or flexible substrates, radio-frequency identification tags on plastic foils, and other large area electronic applications. Microcrystalline silicon TFTs prepared at temperatures compatible with flexible substrates (150–200 °C) have gained much attention as potential elements for such applications due to their high charge carrier mobilities. Understanding the relationship between the structural properties and the charge transport is essential in realizing TFTs with high charge carrier mobility at low temperatures. In this study, top-gate staggered microcrystalline silicon TFTs were realized by plasma-enhanced chemical vapor deposition at maximum temperature of 180 °C. We investigated the correlation between the structural properties of the microcrystalline silicon channel material and the performance of the microcrystalline silicon TFTs. Transistors with the highest charge carrier mobility, exceeding 50 cm2/V s, were realized near the transition to amorphous growth. The results reveal that electronic defects at the grain boundaries of the silicon crystallites are passivated by the amorphous phase near the transition to amorphous growth. The crystalline volume fraction of the channel material will be correlated with the transistor parameters such as charge carrier mobility, threshold voltage, and subthreshold slope.

24.3: 32‐inch LCD TV Using Conventional PECVD Microcrystalline‐Silicon TFTs

AbstractA 32‐inch microcrystalline silicon thin film transistor liquid crystal display was manufactured on 1500×1850 mm2 (G6) glass substrate. We have successfully deposited non‐porous and highly crystalline microcrystalline silicon film with interfacial treatment as the active channel layer for TFTs in such large size display. Microcrystalline silicon was deposited by a conventional (13.56 MHz) plasma‐enhanced chemical vapor deposition (PECVD) system, and the crystalline fraction is 60%. Crystalline fraction was successfully improved with optimized gas treatment on SiNx layer before μc‐Si:H film deposition. Microcrystalline silicon TFTs with interfacial modification have about 2.8 times and 4 times more on‐current than μc‐Si:H TFT without interfacial modification measured at room temperature and at −10°C, respectively. The μc‐Si:H film with good crystallinity used as the active channel layer will significantly improve the reliability of the microcrystalline silicon TFTs. Furthermore, during the bias‐temperature‐stress test (BTS), VTH shift for μc‐Si:H TFT with treatment after 3hr BTS test is only 1.3V while μc‐Si:H TFT without treatment has a VTH shift of 13V.

Thin-film inverters based on high mobility microcrystalline silicon thin-film transistors

Thin-film inverters based on high mobility microcrystalline silicon thin-film transistors (TFTs) with different channel lengths were realized. The NMOS enhancement load saturation mode (NELS) inverters were prepared by plasma-enhanced chemical vapor deposition at temperatures below 200°C. The realization of microcrystalline silicon thin-film inverters facilitates the direct integration of column and row drivers and circuitry on display backpanels. The influence of the transistor properties and underlying contact effects on the performance of the inverters will be discussed.

Influence of the deposition temperature on the performance of microcrystalline silicon thin film transistors

Bottom gate microcrystalline silicon thin film transistors (μc-Si:H TFT) have been fabricated at three different deposition temperatures (150, 200 and 250 °C) for the μc-Si layer. We found that the linear field effect mobility increases from 0.1 to 0.44 cm 2/V s by decreasing the temperature from 250 °C to 150 °C, and that the leakage current of TFTs with μc-Si deposited at 150 °C is lower than that of μc-Si:H deposited at 250 °C. Moreover, there is no influence of the deposition temperature on the stability of μc-Si:H TFTs. The improvement of the electrical characteristics at lower deposition temperatures is discussed in terms of a lower concentration of donor active oxygen atoms at lower temperature.

Specific spice modeling of microcrystalline silicon TFTs

In this paper we present a specific spice static and dynamic model of microcrystalline silicon (μc-Si) thin film transistors (TFTs) taking into account the access resistances and the capacitors contributions. The previously existing models of amorphous silicon and polysilicon TFTs were not completely suited, so we combined them to build a new specific model of μc-Si TFTs. The reliability of the model is then checked by the comparison of experimental measurements to simulations and by simulating the characteristics of some electronic devices (OLED pixels, inverters, and so on).

Critical issues in plasma deposition of microcrystalline silicon for thin film transistors

After more than 20 years of research and despite improved transport properties with respect to amorphous silicon, microcrystalline silicon thin film transistors (TFTs) are not yet ready for industrial production. We review here the progress made in the understanding of the growth of this material with particular emphasis on industry relevant aspects such as deposition rate and uniformity. We show that the synthesis of silicon nanocrystals in the plasma offers unique advantages with respect to deposition rate and film properties. In particular, this allows the production of films which are similar to polycrystalline thin films produced by furnace and laser crystallization. The growth process is also discussed with respect to TFT design: top gate or bottom gate. Results on bottom gate TFTs meeting all the necessary requirements in terms of mobility, ON/OFF ratio and stability required for AMOLED applications are also reported.

Microcrystalline silicon thin-film transistors for large area electronic applications

Thin-film transistors (TFTs) based on microcrystalline silicon (µc-Si:H) exhibit high charge carrier mobilities exceeding 35 cm2 V−1 s−1. The devices are fabricated by plasma-enhanced chemical vapor deposition at substrate temperatures below 200 °C. The fabrication process of the µc-Si:H TFTs is similar to the low temperature fabrication of amorphous silicon TFTs. The electrical characteristics of the µc-Si:H-based transistors will be presented. As the device charge carrier mobility of short channel TFTs is limited by the contacts, the influence of the drain and source contacts on the device parameters including the device charge carrier mobility and the device threshold voltage will be discussed. The experimental data will be described by a modified standard transistor model which accounts for the contact effects. Furthermore, the transmission line method was used to extract the device parameters including the contact resistance. The modified standard transistor model and the transmission line method will be compared in terms of the extracted device parameters and contact resistances.