MicroBlaze Soft Processor Research Articles

Radiation-Tolerant Deep Learning Processor Unit (DPU)-Based Platform Using Xilinx 20-nm Kintex UltraScale FPGA

This paper presents a platform and design approach for enabling radiation-tolerant deep learning acceleration on SRAM-based 20nm Kintex UltraScale™ FPGAs, for terrestrial and high-radiation environments. The presented platform is suitable for deep neural network (DNN) implementations with an emphasis on image classification and includes solutions to mitigate both radiation-induced Single Event Functional Interrupts (SEFIs) and network datapath corruptions. The radiation-tolerant deep learning platform combines Xilinx’s Deep Learning Processing Unit (DPU) IP, Triple Modular Redundancy (TMR) MicroBlaze soft processor IP and Soft Error Mitigation (SEM)-IP to mitigate SEFIs. Furthermore, a technique known as Fault Aware Training (FAT) was applied to effectively mitigate single event effects in the datapath. Test results from a high-energy proton beam (> 60 MeV) experiment using the ResNet-18 Convolutional Neural Network (CNN) for image classification are presented. The Single Event Upset (SEU) rate, system-level SEFI rate and neural network classification/datapath performance are compared between the radiation-tolerant platform and a standard, non-mitigated approach. Results show that datapath classification errors dominate the system response (90%) vs. SEFIs (10%). When compared to standard non-mitigated training techniques, the radiation-tolerant platform using fault aware training methods shows dramatic improvements in overall system response: the overall single event cross-section was reduced by half and 40% reduction in misclassification errors were observed. Also, datapath events with classification accuracy degradation larger than 5% were completely mitigated. The SEFI rate was reduced by 100X with implemented solutions and can be further reduced by optimizing the physical separation between TMR modules.

MPSoC design and implementation using microblaze soft core processor architecture for faster execution of arithmetic application

The research paper presents the design methodology with novel task distribution technique on multi-processor system on chip (MPSoC) for speeding up the execution of arithmetic application. Utilisation of multiple soft core processors on field programmable gate array (FPGA) reduces the overload of adding external hardware to a system. Parallel processing of soft core processor with proposed task distribution technique makes any application to execute at faster rate. This task distribution based speed enhancement technique for arithmetic application is very feasible and appealing to the modern applications like neural networks, fuzzy logic, algorithms of machine learning etc. Experimentation on such architecture with arithmetic application shows significant increase in speed of operation with respect to conventional design. This is implemented using Microblaze soft core processor architecture on Xilinx Virtex 5 FPGA board.

MPSoC design and implementation using Microblaze soft core processor architecture for faster execution of Arithmetic application

MPSoC design and implementation using Microblaze soft core processor architecture for faster execution of Arithmetic application

Exploring the Impact of Soft Errors on the Reliability of Real-Time Embedded Operating Systems

The continuous scaling of electronic components has led to the development of high-performance microprocessors that are suitable even for safety-critical applications where radiation-induced errors such as Single Event Effects (SEEs) can have a significant impact on the performance and reliability of the system. This work is dedicated to investigating the reliability of systems based on programmable hardware and Real-time operating Systems (RTOS) in the presence of architectural faults induced by soft errors in the configuration memory of the programmable hardware. We performed a proton radiation test campaigned at PSI radiation facility to identify the fault model affecting the configuration memory of Xilinx Zynq-7020 reconfigurable AP-Soc Device. The identified fault model in terms of SEU and MBU clusters has been used to evaluate the impact of proton-induced faults on applications running within FreeRTOS on a Microblaze soft processor. A Single Event Multiple Upset fault model resulting from a proton test is presented, focusing on characteristics such as shape, size, and frequency of observed cluster of errors. We conduct two fault injection campaigns and analyze the results to assess the effect of cluster size on system reliability. Moreover, we discuss software exceptions caused by faults that can affect the hardware structure of the soft processor.

Implementation of Sensor Precision Mirror Rate using FPGA

The research contribution is increasing in the field of autonomous spacecraft. The major role contributes to the navigation methods for spacecraft. The intended control design is required precision mirror rate sensor (PMRS) to maintain positioning and stability of the satellite. One major drawback of the PMRS resides in the lock in effect, by which the sensor is not capable of sensing the rotation at low inertial angular rates. In the proposed work due to the uniqueness, it is able to sense the rotation even at the low inertial angular rates. The frequency control loop has been designed, it generates the resonance frequency using dither motor. The frequency control loop of the PMRS, is developed using a 32 bit MICROBLAZE soft core processor along with PID algorithm and same is executed using Xilinx Spartan 6 FPGA.

Comparison of AES and DES Algorithms Implemented on Virtex-6 FPGA and Microblaze Soft Core Processor

Encryption algorithms play a dominant role in preventing unauthorized access to important data. This paper focus on the implementations of Data Encryption Standard (DES) and Advanced Encryption Standard (AES) algorithms on Microblaze soft core Processor and also their implementations on XC6VLX240t FPGA using Verilog Hardware Description language. This paper also gives a comparison of the issues related to the hardware and software implementations of the two cryptographic algorithms.

FPGA Prototyping of Micro-Blaze soft-processor based Multi-core System on Chip

The increased demand for processor-level parallelism has many-folded the challenges for SoC designers to design, simulate and verify/validate today’s Multi-core System-On-Chip (SoC) due to the increased system complexity. There is also a need to reduce the design cycle time to produce a complex multi-core SOC system thereby the product can be brought into the market within an affordable time. The Computer-Aided Design (CAD) tools and Field Programmable Gate Arrays (FPGAs) provide a solution for rapidly prototyping and validating the system. This paper presents an implementation of multi-core SoC consisting of 6 Xilinx Micro-Blaze soft-core processors integrated to the Zynq Processing System (PS) using IP Integrator and these cores will be communicated through AXI bus. The functionality of the system is verified using Micro-Blaze system debugger. The hardware framework for the implemented system is implemented and verified on FPGA.

Shared Memory Multicore MicroBlaze System with SMP Linux Support

In this work, we present PolyBlaze, a scalable and configurable multicore platform for FPGA-based embedded systems and systems research. PolyBlaze is an extension of the MicroBlaze soft processor, leveraging the configurability of the MicroBlaze and bringing it into the multicore era with Linux Symmetric Multi-Processor (SMP) support. This work details the hardware modifications required for the MicroBlaze processor and its software stack to enable fully validated SMP operations, including atomic operation support, shared interrupts and timers, and exception handling. New in this work, we present a scalable and flexible memory hierarchy optimized for Field Programmable Gate Arrays (FPGAs), which manages atomic operations and provides support for future flexible memory hierarchies and heterogeneous systems. Also new is an in-depth analysis of key performance characteristics, including memory bandwidth, latency, and resource usage. For all system configurations, bandwidth is found to scale linearly with the addition of processor cores until the memory interface is saturated. Additionally, average memory latency remains constant until the memory interface is saturated; after which, it scales linearly with each additional processor core.

FPGA-based approach for change detection in GTAW welding process

This paper presents the development of an FPGA-based platform for online discontinuity detection in a Gas Tungsten Arc Welding (GTAW) process, through the monitoring of its voltaic arc, using an optical infrared sensor. The FPGA-based platform uses a hardware/software co-design approach, in which the hardware part includes a change detection peripheral, apart from general purpose peripherals (e.g. UART, timer) and several customized ones such as memory for storing discontinuity data, timer and an ADC driver. The change detection peripheral comprises the filtering stage and the stopping rule stage, which include a Kalman filter and a cumulative sum (CUSUM) module, respectively. The overall system includes several processes running concurrently in the Microblaze embedded processor and several customized hardware modules, using floating point representation. In order to validate the FPGA-based platform, several experimental tests in the field have been done by introducing intentional discontinuities in the weld bead. These experimental results have shown a suitable performance of the overall system in the online discontinuity detection task. In this paper, the change detection peripheral is described as well as the synthesis results related to performance and resources consumption. In the overall co-design approach, the software part includes a MicroBlaze soft processor to control and manage the overall platform, including the interface issues.

Distance and Speed Measurements using FPGA and ASIC on a high data rate system

This paper deals with the implementation of FPGA and ASIC designs to calculate the distance and speed of a moving remote object using laser source and echo pulses reflected from that remote object. The project proceeded in three phases for the FPGA implementation: All-in-C design using Xilinx Microblaze soft core processor system, an accelerated design with custom co-processor and Microblaze soft core processor system, and full custom hardware design implemented using VHDL on Xilinx FPGA. Later the complete system was implemented on ASIC. The ASIC implementation optimized the modules for area and timing for a 130nm process technology.

RSA Cryptography using our Designed Processor and MicroBlaze Soft Processor in FPGAs

Some applications such as RSA encryption/decryption need integer arithmetic operations with many bits. However, such operations cannot be performed directly by conventional CPUs, because their instruction supports integers with fixed bits, say, 64 bits. Since the CPUs need to repeat arithmetic operations to numbers with fixed bits, they have considerably overhead to execute applications involving integer arithmetic with many bits. On the other hand, This paper implements hardware algorithms for such applications in the FPGAs for further acceleration. However, the implementation of hardware algorithm is usually very complicated and debugging of hardware is too hard. The main contribution of this paper is to present an intermediate approach of software and hardware using FPGAs. More specifically, this paper presents a processor based on FDFM (Few DSP slices and Few Memory blocks) approach that supports arithmetic operations with flexibly many bits, and implement it in the FPGA. To show the potentiality of designed processor, 128bit RSA encryption/decryption is implemented and compare with soft processor “MicroBlaze” in FPGA. The resulting processor uses only one DSP48E1 slice and four Block RAMs (BRAMs), and RSA encryption software on it runs in 0.42ms. However, MicroBlaze uses three DSP48E1 slices and 170 Block RAMs (BRAMs) and runs in 152.28ms. Hence, the proposed designed processor is significantly efficient in terms of resource used and time complexity in comparison to soft processor “MicroBlaze” in FPGAs. Also the proposed processor can be used efficiently for longer bit arithmetic operation such as 2048-bit without further modifications and hence it is more flexible. General Terms RSA Security Algorithm

RUN TIME DYNAMIC PARTIAL RECONFIGURATION USING MICROBLAZE SOFT CORE PROCESSOR FOR DSP APPLICATIONS

DSP Application requires a fast computations & flex ibility of the design. Partial Reconfiguration (PR) is an advanced technique, which improves the flexibility of FPGAs by allowing portions of a design to be reconfigured at runtime by overwriting parts of the configuration memory. In this paper we are using mi croblaze soft core processor & ICAP Port to reconfi gure the FPGA at runtime. ICAP is accessed through a light-weight custom IP w hich requires bit stream length, go, and done signa l to interface to a system that provides partial bit stream data. The partial bit s tream is provided by the processor system by readin g the partial bit files from the compact flash card. Our targeted DSP application is matrix multiplication; we are reconfiguring design by changing partial modules at run time. To change the partial bit stream we in terfaces a microblaze Soft processor & using a UART interface.ISE13.1 & PlanAhead is used for partial reconfiguration of FP GA .EDK is used for microblaze soft processor desig n & ICAP Interface .The simulation is done using Chip Scope Logic Analyzer & the complete hardware implementation is done on X ilinx VIRTEX -6 ML605 Platform.

A methodology for speeding up edge and line detection algorithms focusing on memory architecture utilization

In this paper, a new methodology for speeding up edge and line detection algorithms is presented, achieving improved performance over the state of the art software library OpenCV (speedup from 1.35 up to 2.22) and other conventional implementations, in both general and embedded processors, by reducing the number of load/store and arithmetic instructions, the number of data cache accesses and data cache misses in memory hierarchy and the algorithm memory size. This is achieved by fully exploiting the combination of the software and hardware parameters which are considered simultaneously as one problem and not separately. Furthermore, the edge and line detection algorithms have been simplified for a computer vision application in a Virtex-5 Xilinx FPGA using Microblaze soft processor (detection and measurement of flow fronts in a microfluid device); it achieves speedup up to 660 times in comparison with conventional software implementations.

Optimizing the use of an SPI Flash PROM in Microblaze-Based Embedded Systems

This paper aims to simplify FPGA designs that incorporate Embedded Software Systems using a soft core Processor. It describes a simple solution to reduce the need of multiple non-volatile memory devices by using one SPI (Serial Peripheral Interface) Flash PROM for FPGA configuration data, software code (Processor applications), and miscellaneous user data. We have thus developed a design based on a MicroBlaze soft processor implemented on a Xilinx Spartan-6 FPGA SP605 Evaluation Kit. The hardware architecture with SPI flash was designed using the Xilinx Platform Studio (XPS) and the software applications, including the bootloader, was developed with Xilinx Software Development Kit (SDK). ISE Design Tools prepared by Xilinx Company, is employed to create the files used to program flash memory which are SREC (S-record) file associated with software code, Hexadecimal file for user data, and bootloader file to configure the FPGA and allows software applications stored in flash memory to be executed when the system is powered on. Reading access to the SPI Flash memory is simplified by the use of Xilinx In-System Flash (ISF) library.

An FPGA Implementation Of Hearing Aids based on Wavelet-Packets

Advances in digital signal processing and microelectronics have led to the development of superior digital hearing aids for ameliorating severe defects of hearing. The progress in field programmable gate arrays (FPGA) technology, especially for miniaturized system applications, allowed increasing sophisticated features to be built for better sound reproduction, keeping small size and low power consumption of the devices. In this paper the recent trend of combining interconnects of FPGAs with embedded microprocessors and related peripherals to form a complete system on a programmable chip is employed for the design of digital hearing aids. Wavelet packet transform is applied for speech compensation of the hearing loss. The wavelet packet module is described in VHDL, implemented on FPGA and then added as a peripheral to the processor system. The embedded software processor used is the MicroBlaze soft core processor. The chip used is Digilent XUP II Virtex-II Pro system FPGA containing audio codec LM4550. The features of the design are small area and fast processing and low cost.

Fuzzy logic path tracking control for autonomous non-holonomic mobile robots: Design of System on a Chip

This paper presents a System on Chip (SoC) for the path following task of autonomous non-holonomic mobile robots. The SoC consists of a parameterized Digital Fuzzy Logic Controller (DFLC) core and a flow control algorithm that runs under the Xilinx Microblaze soft processor core. The fuzzy controller supports a fuzzy path tracking algorithm introduced by the authors. The FPGA board hosting the SoC was attached to an actual differential-drive Pioneer 3-DX8 robot, which was used in field experiments in order to assess the overall performance of the tracking scheme. Moreover, quantization problems and limitations imposed by the system configuration are also discussed.

Analysis and Implementation Hardware-Software of Rijndael Encryption

By means of this study We have optimized the perfamance of the cryptographic algorithm Rijndael in a low cost hardware/software system,in a FPGA Spartan3e board of Xilinx with a MicroBlaze soft-processor. After the study of its execution in six systems with different configurations, the hardware bits rotation of MicroBlaze's optimizes the process of coding and deciphered, and the combination with the implementation of a coprocesador with a Galois field multiplier optimizes the key expansion.

Design and implementation of a MicroBlaze-based warp processor

While soft processor cores provided by FPGA vendors offer designers with increased flexibility, such processors typically incur penalties in performance and energy consumption compared to hard processor core alternatives. The recently developed technology of warp processing can help reduce those penalties. Warp processing is the dynamic and transparent transformation of critical software regions from microprocessor execution to much faster circuit execution on an FPGA. In this article, we describe an implementation of a warp processor on a Xilinx Virtex-II Pro and Spartan3 FPGAs incorporating one or more MicroBlaze soft processor cores. We further provide a detailed analysis of the energy overhead of dynamically partitioning an application's kernels to hardware executing within an FPGA. Considering an implementation that periodically partitions the executing application once every minute, a MicroBlaze-based warp processor implemented on a Spartan3 FPGA achieves average speedups of 5.8× and energy reductions of 49% compared to the MicroBlaze soft processor core alone—providing competitive performance and energy consumption compared to existing hard processor cores.

Implementation of embedded emulated‐digital CNN‐UM global analogic programming unit on FPGA and its application

AbstractThe paper addresses the issue of implementing an embedded global analogic programming unit (GAPU) on the reconfigurable emulated‐digital cellular neural/nonlinear networks universal machine (CNN‐UM) architecture that has been extended by a flexible Xilinx MicroBlaze soft processor core to take full advantage of the joint computing power of high‐speed distributed arithmetics and programmability. The implemented GAPU provides a stand‐alone operation, which is capable of controlling complex sophisticated CNN analogic algorithms similar to various visual microprocessors, such as the ACE4k, ACE16k, and Bi‐i vision systems. The quality of the embedded GAPU implementation is demonstrated by an analogic algorithm, in which sequences of template operations are required. Based on the experiments, several important issues relating to the acceleration efficiency, accuracy, cell size, and area consumption are discussed and compared with different CNN‐UM implementations. Copyright © 2008 John Wiley & Sons, Ltd.

A stream chip-multiprocessor for bioinformatics

Bioinformatics applications such as gene and protein sequence matching algorithms are characterized by the need to process large amounts of data. While uni-processor performance growth is slowing due to an increasing gap between processor and memory speeds and a saturation of processor clock frequencies, Genbank data is doubling every 15 months. With the advent of chip multiprocessor systems, great improvements in processor performance could potentially be achieved by taking advantage of the high interprocessor communication bandwidth and new models of programming. We propose a stream chip multiprocessor micro- architecture customized for bioinformatics applications that takes advantage of the memory bandwidth available in chip multiprocessors by exploiting the data parallelism available in bioinformatics applications. The proposed stream chip multiprocessor micro architecture, on a Xilinx Virtex-5 FPGA with 60 customized MicroBlaze soft processor cores running at 80 MHz with a PCI- bus limited main memory bandwidth of 0.12 GB/s, would achieve a speed-up of 68% for the Smith-Waterman sequence matching algorithm compared to a 2.4 GHz AMD Opteron 250. An extrapolated 60 long stream CMP running at 1 GHz with a memory access rate of 2.7 GB/s would run 41.7 times faster than the 1.2 GHz Sun Niagara processor, 16.5 times faster than the 2.4 GHz AMD Opteron 250 and 12.3 times faster than the 2.4 GHz Intel Xeon processor.