MHz Input Research Articles

Full-Swing Nanosecond Delay Hybrid Level Shifter for Time-Critical Applications

A crucial component of digital integrated circuits with numerous power domains is the level shifter (LS). The traditional topologies are currently the mirror LS and cross-coupled LS. For full-swing level conversions from extremely low voltage to the nominal voltage of the supply, ahybrid LS is proposed in this paper, which is a combination of the current mirror LS and cross-coupled LS with a swing-aware output inverter. The proposed LS circuit is designed to ensure full swing, static current-free, and limited current-contention level conversions by preserving the benefits of the current mirror and cross-coupled LS, and using them to eliminate each other’s shortcomings. The proposed hybrid LS is designed and implemented by using 45-nm technology in Cadence Virtuoso tool. Pass transistors and current limiters with multiple thresholds are included for the suggested LS. The proposed LS provides voltage conversion from 0.10 V to 1.20 V. At alevel-shifting voltage of 0.20 V, the proposed hybrid LS at 1 MHz input frequency demonstrates a delay of 8.38 ns, an average power consumption of 3.81 µW, and an energy per transition of 26.64 fJ. Additionally, the suggested LS has low delay, good supply voltage scaling, and delay scalability.

Input Voltage-Level Driven Split-Input Inverter Level Shifter for Nanoscale Applications

A level shifter (LS) appears to be highly efficient and effective in solving voltage contentions between deep sub-threshold and core voltage levels. An input voltage-level driven split-input inverter that can create common unconnected PMOS and NMOS transistors for the input inverter is proposed, which is powered and used at the input stage to achieve maximum conversion efficiency. Layout and simulation results across different corners have demonstrated that the proposed LS is highly useful for cutting-edge nanoscale applications. It can up-convert voltage from 0.2 V to 1.2 V and down-convert from 1.2 V to 0.2 V @ 1 MHz input pulse, with a level-up or level-down mean switching delay of 1.3 ns, and a power of 9.5 nW. Moreover, the LS occupies an area of 8 μm2, which is a reasonably compact size compared to the typical LS designs. Overall, the proposed voltage LS design is an efficient and effective solution that could have an ample range of applications in IoT and biomedical, wireless sensor networks.

An All-Digital Timing Mismatch Calibration Algorithm Based on Reference Channel for TIADC

This paper proposes an all-digital calibration algorithm that utilizes a reference channel to suppress the timing mismatch in the Time-Interleaved Analog-to-Digital Converter (TIADC). The output of the reference channel is aligned with each sub-channel in turn, therefore enabling the simultaneous sampling and conversion of the same input signal. First, the statistical characteristics across the channels are employed for estimating the timing mismatch; then, by comparing the output difference between the reference channel and the sub-channels that are sampled simultaneously, the deviation of the derivator can be calibrated. Finally, combining both calibration results yields an accurate final output. This proposed algorithm provides an effective solution to improve TIADC performance in high-speed data acquisition systems. The proposed architecture is applied to a 12-bit 2.4 GS/s four-channel TIADC model, and then its effectiveness is verified. The simulation results exhibit that the Effective Number Of Bits (ENOB) at an input signal frequency of 984 MHz shows a remarkable improvement from 6.88 bits to 11.92 bits. The effectiveness of this technique is also demonstrated through the off-chip calibration of a commercial 12-bit four-channel 2 GS/s TIADC using a 680 MHz input signal that is based on the actual chip results.

On Minimizing Charge Injection Error Using Multi-Dummy Switches With Enhanced Linearity

The paper proposes an ameliorated methodology to minimize the effect of charge injection over a wide input common-mode range. Instead of a conventional single dummy switch compensation [1], the multi-dummy switches are proposed and employed to eradicate the injected charge on to the sampling capacitor. A detailed methodology is presented to compensate the charge injection in a MOS switch. The closed-form equations are derived mathematically to substantiate the proposed technique. For the proof-of-concept, a track-and-hold (T/H) stage has been simulated in 0.18μm CMOS technology with the proposed technique for a 10-bit resolution. The proposed technique based T/H stage exhibits the spurious free dynamic range (SFDR) of 62.6 dB, effective number of bits (ENOB) of 9.36, peak input-referred third-order intercept point (IIP3) of 13.02 dBm and an input-referred 1 dB compression point (P1dB) of 3.8 dBm at 1.074 MHz input frequency, sampled at 100 MSa/s. The performance of the proposed method is compared with the existing single dummy switch compensation method where our technique shows 88.8% compensation in minimizing the charge injection error and 272% improvement in dynamic linearity. Moreover, the presented technique quantifies 9× improvement in mean percentage error (MPE) when simulated across the various process corners and rail-to-rail input common-mode voltage.

Driving magnetic oscillation by electric flip in Permalloy/BaTiO3 composite

In this work, the Permalloy/BaTiO3 composite with granule/matrix structure is designed. The theoretical calculation reveals coupling between electric polarization and magnetic anisotropy. As electric polarization is downward and upward in BaTiO3 matrix, the magnetizing orientation tends to be parallel and perpendicular in Permalloy granule respectively. The Landau-Lifshitz-Gilberts model further predicts magnetic oscillation driven by electric flip. Explicitly, as electric polarization flips with low frequency in BaTiO3 matrix, the magnetic moment oscillates with high frequency in Permalloy granule. It results from the anisotropy field altered periodically by polarization flip. Based on the magnetic tunneling model, the moment oscillation can output periodical voltage signal. With the Square-Root circuit, the oscillating amplitude of output voltage becomes stable. Through 4-level connection of this design, the 1.0 MHz input can drive 3.5 GHz output. This work gives a novel strategy for spin torque nano-oscillator. Compared to the spin-transfer torque method, this avenue could avoid the heat influence of current.

An evenly-spaced-phase all-digital DLL using dual-loop SAR control

This study introduces an all-digital delay-locked loop (ADDLL), which generates 20 evenly-spaced-phase clock signals. A successive-approximation register (SAR)-based dual-loop control is used to realize the locking process of the ADDLL. A modified SAR unit combined with a tri-state digital phase detector (TSDPD) is adopted to achieve a closed-loop operation of the ADDLL. A delay matrix, which can significantly reduce the jitter accumulation, is used to generate evenly spaced phases without using a long-cascaded delay line. Additional harmonic-lock detector circuits are added to the two control loops to avoid the harmonic lock issue. The ADDLL is designed and fabricated using a 0.18μm mixed-signal CMOS technology with an active area of 0.109 μm2. The lock range of the ADDLL is 30–230 MHz and the power consumption of the ADDLL is 8.9 mW at 100 MHz. The measured rms jitter is 23.3 ps at 100 MHz, and the results show a good linearity of the multiphase outputs at a 100 MHz input clock where the maximum DNL and INL are 0.08 and -0.22 LSB, respectively. The proposed ADDDLL is highly suitable for low-frequency, low-power, and high-time-resolution applications.

Design and Implementation of a Transmitter for IR-UWB Standard

In wireless communication, the Ultrawide Band (UWB) is a technique for achieving a higher data rate, low power consumption, and less complexity. Impulse Radio - Ultra-Wide Band (IR-UWB) uses the baseband signal technique, reducing circuit complexity and power consumption. This work proposes an IR-UWB transmitter block with low power and tunable bandwidth that meets the UWB regulations of LRP (Low-Rate Pulse) UWB. The transmitter proposed uses a time-interleaved architecture using 0.18um CMOS technology using Cadence Virtuoso, which consists of On Off Keying (OOK) Circuit for the four stages of a pulse generator that operates in 6.17GHz-9.10GHz. The width of the pulse is between 0.096ns to 0.162ns using a current steering inverter. The proposed transmitter block has an output swing of 30 mV at 1MHz input Pulse Repetition Frequency (PRF) and a maximum PRF of 1GHz, at a 1GHz pulse rate, the power consumption was measured to be 8.3 mW.

A VCO-Based ADC With Inherent Mixing Capability and Local Oscillator Suppression in 55-nm CMOS

This brief introduces a new circuit that can be used as a mixer and as a VCO-ADC simultaneously. The power supply nodes of the inverters in a ring oscillator are sorted in two sets, and connected to two different input signals. We prove mathematically that the oscillator frequency of such configuration reacts to the product of the two analog inputs. Therefore, the ring oscillator can be used as an ADC to directly digitize the low pass down converted component. A first system-level approach is made to minimize the non desired beat components by a proper number of taps in the ring oscillator. To confirm the concept of the Mixer VCO-ADC and its performance, a 55nm CMOS chip has been designed and fabricated. Measurements show a SNDR of 51.3 dB in a 100 kHz bandwidth in the down converted signal from a 1.001 MHz input signal mixed with a 1 MHz local oscillator.

Design of RF energy harvester for 700 MHz

Abstract Radio frequency energy harvester is the conversion of ambient radio frequency electromagnetic waves into usable electrical energy, powering low-power devices without traditional power sources. In this paper, a novel RF energy harvester is proposed for 700 MHz frequency band. For the purpose of rectification, a Greinacher voltage rectifier cum multiplier is used in the circuit and Schottky Diode HSMS-2852 is used for implementing a rectifier. The LC impedance matching is implemented to improve the circuit performance of the harvester including conversion efficiency and output voltage. Simulation of the rectifier is done using the PathWave Advanced Design System (ADS) software. The rectifier shows the optimized performance at 5 kΩ load impedance. Simulation results show the highest efficiency of 33.1 % and an output voltage of 3.2 V with 8 dBm RF power at 700 MHz input frequency.

The LiTE-DTU: A Data Conversion and Compression ASIC for the Readout of the CMS Electromagnetic Calorimeter

The High-Luminosity phase of operation of the CERN LHC collider (HL-LHC) will pose new challenges to the detectors and their readout electronics. In particular, the CMS barrel electromagnetic calorimeter will require a full redesign of the electronic readout chain in order to cope with the increase in luminosity and trigger rate. In this framework, a new Application Specific Integrated Circuit (ASIC) integrating A/D conversion, lossless data compression and high speed transmission has been developed and tested. The ASIC, named LiTE-DTU, is designed in a commercial CMOS 65 nm process and embeds two 12-bit, 160 MS/s Analog to Digital Converters (ADCs), a data selection and compression logic, and a 1.28 Gb/s output serial link. The high-speed 1.28 GHz clock is generated internally from the 160 MHz input by a clock multiplication Phase-Locked Loop (PLL). The circuit has been designed implementing radiation tolerant techniques in order to work in the harsh environment of the HL-LHC upgrade. The LiTE-DTU is currently in the pre-production phase. A sample of 600 chips has been tested and incorporated into front end boards for systems performance testing.

An 11-bit 160-MS/s Non-binary C-based SAR ADC with a Partially Monotonic Switching Scheme

This work proposes a single-channel 11-bit successive-approximation register (SAR) analog-to-digital converter (ADC) with an operating speed of 160-MS/s based on a non-binary digital-to-analog converter (DAC) for settling error correction. In the proposed DAC, a non-binary-weighted structure with redundancy is employed for the upper 8-bit capacitor array to reduce the residual voltage settling time requirement, facilitating high-speed operation. The remaining 3-bit capacitor array is composed of three unit capacitors, which are attached to the fractional reference voltages generated from a resistor string (R-string). The proposed partially monotonic switching scheme reduces the switching power consumption and the common-mode voltage variations of the DAC output voltage. The proposed 3D-encapsulated capacitor layout reduces the interference of adjacent signals while securing the high linearity of capacitors. Implemented in a 28 nm CMOS, the proposed ADC consumes 1.67 mW of power with a 1.0 V supply voltage and occupies an active area of 0.026 mm². The prototype ADC achieves a signal-to-noise-and-distortion-ratio (SNDR) and a spurious-free-dynamic-range (SFDR) of 53.5 dB and 67.5 dB, with a 9 MHz input at 160 MS/s, respectively.

A Low-Cost Hardware/Software Platform for Lossless Real-Time Data Acquisition from Imaging Spectrometers.

In real-time data-intensive applications, achieving real-time data acquisition from sensors and simultaneous storage with the necessary performance is challenging, especially if "no-data-lost" requirements are present. Ad hoc solutions are generally expensive and suffer from a lack of modularity and scalability. In this work, we present a hardware/software platform built using commercial off-the-shelf elements, designed to acquire and store digitized signals captured from imaging spectrometers capable of supporting real-time data acquisition with stringent throughput requirements (sustained rates in the boundaries of 100 MBytes/s) and simultaneous information storage in a lossless fashion. The correct combination of commercial hardware components with a properly configured and optimized multithreaded software application has satisfied the requirements in determinism and capacity for processing and storing large amounts of information in real time, keeping the economic cost of the system low. This real-time data acquisition and storage system has been tested in different conditions and scenarios, being able to successfully capture 100,000 1 Mpx-sized images generated at a nominal speed of 23.5 MHz (input throughput of 94 Mbytes/s, 4 bytes acquired per pixel) and store the corresponding data (300 GBytes of data, 3 bytes stored per pixel) concurrently without any single byte of information lost or altered. The results indicate that, in terms of throughput and storage capacity, the proposed system delivers similar performance to data acquisition systems based on specialized hardware, but at a lower cost, and provides more flexibility and adaptation to changing requirements.

A Review of Design of Digital Clock Based on Verilog HDL

With the development of electronic technology, digital clocks have added many functions that facilitate people's lives, Digital electronic clock is a device that uses digital circuits to realize the digital display of time, minutes, and seconds. This paper mainly discusses how to use Verilog HDL to design a simple digital clock and realize the basic functions such as timing and display in the clock, as well as the platform and tools used. The circuit of the digital clock is divided into three modules, namely the frequency division module, counting module, and decoding display module. And the timing process is through the LED display, and the digital tube displays "hours", "minutes", and "seconds" which are displayed in two digits. The frequency division module divides a 50 MHz input signal to obtain a 1 Hz clock signal, and the counting time module can count and adjust the time of the clock, minutes, and seconds, and then display it on the FPGA development board through the decoding display module. After clock simulation, the system realizes the function of the digital clock and meets the design requirements.

A Fast Lock-In Time, Capacitive FIR-Filter-Based Clock Multiplier with Input Clock Jitter Reduction

This paper presents a fast lock-in time clock frequency multiplier without using traditional clock generation circuits such as PLLs and DLLs. We propose a novel technique based on capacitive finite impulse response (FIR) filters to generate clock phases while reducing the input clock phase noise at the same time. A new delay line circuit is also proposed for improving power supply rejection. In addition, to improve the matching quality as well as the end-effects tolerance of the on-chip capacitors, a single-value series/parallel algorithm is proposed. Designed in a 0.18 μm digital CMOS process, with a 20 MHz input clock frequency, the multiplier achieves a multiplication factor of 5 with a lock-in time of less than 4 clock cycles. The input clock jitter is reduced from 7ns RMS to 153 ps RMS after frequency multiplication.

A 12-Bit 1-GS/s Pipelined ADC with a Novel Timing Strategy in 40-nm CMOS Process

This paper presents a 1-GS/s12-bit pipelined analog-to-digital converter (ADC) fabricated in 40-nm CMOS technology that optimizes the settling time, bit error rate, and robustness. This ADC uses an improved timing called pre-quantization timing (PQT), which implements quantization in half the time of the sampling phase to maximize the output-settling time of the operational amplifier (op-amp). A complete clocking scheme along with a delay lock loop (DLL) is proposed to generate an accurate timing no matter how process, voltage, and temperature (PVT) change. Based on PQT, a high-speed comparator circuit is adopted to obtain a bit error rate (BER) below 10−15. Sample and hold amplifier (SHA) is used to guarantee robustness over the wide input frequency. Furthermore, a low-cost automatic calibration is implemented to correct residual curves, and inter-stage gain errors are also corrected. This ADC achieves a signal-to-noise-and-distortion ratio (SNDR) of 57.3 dB and a spurious-free dynamic range (SFDR) of 78.5 dB at a 227 MHz input frequency. The measured differential nonlinearities (DNL) and integral nonlinearities (INL) after calibration are ±0.7 LSB and ±1.50 LSB, respectively. The power consumption of the ADC core is 97.6-mW, and the Walden figure of merit (FoM) is 172.9-fJ/conversion-step.

A complementary high linearity bootstrap switch based on negative voltage bootstrap capacitor

The sample-and-hold (S/H) circuit is an important part of the analog-to-digital converter (ADC). A bootstrap switch with capacitive load can form a basic S/H circuit. A complementary high linearity gate voltage bootstrap switch based on bootstrap capacitor is proposed in this paper. By reducing the size of the key node transistors, the parasitic capacitance is reduced. The sampling metal-oxide-semiconductor field-effect transistor (MOSFET) in this structure is composed of complementary NMOS and PMOS, which reduces the channel charge injection effect and variations in on-resistance (Ron). The simulation results show that the effective number of bits (ENOB), signal-to-noise and distortion ratio (SNDR) and spurious-free dynamic range (SFDR) of the structure are 16.5 bits, 101.11 dB and 101.83 dB respectively at the sampling frequency of 50 MHz and full swing voltage input of 1.8 V based on SMIC 0.18 μm process. Compared with the conventional NMOS switch, ENOB, SDNR, and SFDR are increased by 2.45 bits, 14.73 dB, and 13.38 dB, respectively. In addition, Monte Carlo (MC) and corner simulations of the proposed circuit are performed, and the results show that the proposed circuit has good performance.

Efficient Monolithic SAW Convolver Using Poly(3-Hexylthiophene)

The demonstration of organic semiconductor based monolithic surface acoustic wave (SAW) convolver has been reported. The characteristic low availability of intrinsic free charge in organic semiconducting polymer favors depletion mode of operation, increasing the effective nonlinear interactions. Input signals at different combinations of frequencies were used and the observed convolved signals showed notably high efficiency without the need of an applied bias. The record high efficiency has been -13.2 dBm for 42 MHz input signals at optimum input power of -6 dBm. The experimental results and the convolution mechanism were verified via numerical analysis in MATLAB.

A 16b 120MS/s Pipelined ADC Using an Auxiliary-Capacitor-Based Calibration Technique Achieving 90.5dB SFDR in 0.18 μm CMOS

A 16-bit 120 MS/s sample-hold-amplifier-less(SHA-less) pipelined analog-to-digital converter (ADC) with an on-chip calibration technique in a <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$0.18~\mu \text{m}$ </tex-math></inline-formula> CMOS process is presented. A switched capacitor circuit with an auxiliary unit capacitor in the multiplying-digital-to-analog converter (MDAC) of the first stage is proposed. The auxiliary-capacitor based calibration technique eliminates the need for a dedicated reference buffer to generate the calibration voltages at all the comparator thresholds. By switching the auxiliary capacitor and doing some simple calculation work, all the capacitor mismatches in the first and second stages are corrected in the digital domain, thereby significantly improving the ADC performance. Measurement results show that, with 70.1 MHz input, the signal-to-noise-and-distortion-ratio (SNDR) is improved from 75.5 dB to 77.8 dB, and the spurious-free-dynamic-range (SFDR) is improved from 81.9 dBc to 90.5 dBc with the proposed calibration technique.

Effective Gain Analysis and Statistic Based Calibration for Ring Amplifier With Robustness to PVT Variation

This brief focuses on the robustness of the ring amplifier (RA), an alternative to the operational transconductance amplifier (OTA) in the deep nanoscale CMOS process. The effective gain (EG) of the RA shows diverse characteristics from the DC gain and can be treated as a non-linear gain error (NLGE). The EG shows a notable variation when taking process, supply voltage, and temperature (PVT) into consideration. An improved statistical calibration based on the back-end stage data is proposed to compensate the NLGE. A prototype SAR-assisted pipeline ADC with a quick-start RA is implemented in a 28-nm CMOS process, achieving 60.3 dB SNDR and 76.5 dB SFDR with a 6 MHz input at 625 MS/s. The SNDR and SFDR are 58.6 dB and 70.7 dB with a Nyquist input frequency and consumes 13.2 mW, achieving Walden and Schreier figure-of-merit (FoM) values of 30.4 fJ/conv.-step and 162.2 dB. For a &#x2212;6 dBFS 50 MHz input, the measured SNDR and SFDR are above 55.5 dB and 68.9 dB with supply voltage and temperature fluctuation.

High-Throughput Low Power Area Efficient 17-bit 2’s Complement Multilayer Perceptron Components and Architecture for on-Chip Machine Learning in Implantable Devices

In this manuscript the authors, design new hardware efficient combinational building blocks for a Multi Layer Perceptron (MLP) unit which eliminates the need for hardware generic Digital Signal Processing (DSP) units and also eliminates the need for on-chip block RAMs (BRAMs). The components were designed to minimise power and area consumption without sacrificing throughput. All designs were validated in a Field Programmable Gate Array (FPGA) and compared against unrestricted CPU-MATLAB implementations. Furthermore, a (2,2,2,2) MLP with back propagation was implemented and tested in a FPGA showing a total hardware utilisation of just 3782 LUTs, and no DSP or BRAMs. The MLP was also built in a Application Specific Integrated Circuit (ASIC) using a 130 nm technology by <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">Skywater 130A</i> . The results show that the area occupation was just 0.12 <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">mm</i> <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> and consumed just 100 mW at 100 MHz input stimulus.