MHz Event Rate Research Articles

ALICE Zero Degree Calorimeters. The new readout system in LHC Run 3

The Zero Degree Calorimeters (ZDC) were designed to provide the measurement of the event geometry and luminosity in heavy-ion operation. The readout system was redesigned in order to operate in continuous mode without dead time at 2.5 MHz event rate. The new acquisition chain is based on a commercial 12 bit digitizer with a sampling rate of about 1 GSps, assembled on an FPGA Mezzanine Card. The signals produced by the 26 ZDC channels are digitized, and samples are processed through an FPGA to extract information such as timing, baseline average estimation and luminosity.

EDFLOW: Event Driven Optical Flow Camera With Keypoint Detection and Adaptive Block Matching

Event cameras such as the Dynamic Vision Sensor (DVS) are useful because of their low latency, sparse output, and high dynamic range. In this paper, we propose a DVS+FPGA camera platform and use it to demonstrate the hardware implementation of event-based corner keypoint detection and adaptive block-matching optical flow. To adapt sample rate dynamically, events are accumulated in event slices using the area event count slice exposure method. The area event count is feedback controlled by the average optical flow matching distance. Corners are detected by streaks of accumulated events on event slice rings of radius 3 and 4 pixels. Corner detection takes about 6 clock cycles (16 MHz event rate at the 100MHz clock frequency) At the corners, flow vectors are computed in 100 clock cycles (1 MHz event rate). The multiscale block match size is <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$25\times 25$ </tex-math></inline-formula> pixels and the flow vectors span up to 30-pixel match distance. The FPGA processes the sum-of-absolute distance block matching at 123 GOp/s, the equivalent of 1230 Op/clock cycle. EDFLOW is several times more accurate on MVSEC drone and driving optical flow benchmarking sequences than the previous best DVS FPGA optical flow implementation, and achieves similar accuracy to the CNN-based EV-Flownet, although it burns about 100 times less power. The EDFLOW design and benchmarking videos are available at <uri xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">https://sites.google.com/view/edflow21/home</uri> .

Readout system of the ALICE Fast Interaction Trigger

The Fast Interaction Trigger (FIT) detector will be essential for the operation of the ALICE experiment at CERN during Run 3 and 4 of the LHC . FIT will serve as an interaction trigger, luminometer, the first indicator of the vertex position, and the forward multiplicity counter. It will also provide the precise collision time for the TOF-based particle identification, yield the centrality and interaction plane for flow measurements, and measure cross sections of diffractive processes. In order to cope with an increased interaction rate of up to 1 MHz in proton-proton (pp) collisions and up to 50 kHz in Pb-Pb collisions, a new readout system for the ALICE FIT detector has been designed and implemented. FIT readout system is compatible both with the triggered and continuous (triggers-less) ALICE readout modes. The GBT-FPGA based FIT readout and trigger systems allow to stream data up to 5.5 MHz event rate with 3.2 Gbps data rate. The trigger processing time is only 225 ns. With the additional 200 ns delay along the connecting signal cables, the total latency of the FIT trigger is 425 ns.

A new scheduling algorithm for the LHCb upgrade trigger application

During Run3 of the LHC the LHCb detector will process a 30 MHz event rate with a full detector readout followed by a software trigger. To deal with the increased computational requirements, the software framework is reviewed and optimized on a large scale. One challenge is the efficient scheduling of O(103)-O(104) algorithms in the High Level Trigger (HLT) application. This document describes the design of a new algorithm scheduler which allows for static-order intra-event scheduling with minimum complexity while still providing the required flexibility.

Real-time cluster finding for LHCb silicon pixel VELO detector using FPGA

In the Run-3 of LHCb, the High Level Trigger will have to process events at full LHC collision rate (30 MHz). This is a very challenging goal, and delegating some low-level tasks to FPGA accelerators can be very helpful by saving precious computing time. In particular, the 2D pixel geometry of the new LHCb VELO detector makes the cluster-finding process particularly CPU-time demanding. We realized and tested a highly parallel FPGA-based clustering algorithm, capable of performing this reconstruction in real time at 30 MHz event rate using a modest amount of hardware resources, that can be a viable alternative solution.

On-detector Electronics for the LHCb VELO Upgrade

The LHCb Experiment is designed for precision measurements of CP violation and rare decays of beauty and charm hadrons. The experiment will be upgraded to a trigger-less system reading out the full detector at a 40 MHz event rate with all selection algorithms executed in a CPU farm. The upgraded Vertex Locator will be a hybrid pixel detector read out by the VeloPix ASIC with on-chip zero-suppression. The overview of the system and the design of the VELO on-detector electronics that include the front-end hybrid, the opto-conversion and power distribution boards will be summarised. The results from the evaluation of these prototypes and further enhancement techniques will be discussed.

4D fast tracking for experiments at high luminosity LHC

The full exploitation of the physics potential of the high luminosity LHC is a big challenge that requires new instrumentation and innovative solutions. We present here a conceptual design and simulation studies of a fast timing pixel detector with embedded real-time tracking capabilities. The system is conceived to operate at 40 MHz event rate and to reconstruct tracks in real-time, using precise space and time 4D information of the hit, for fast trigger decisions. This work is part of an R&D project aimed at building an innovative tracking detector with superior time (10 ps) and position (10 μm) resolutions to be used in very harsh radiation environments, for the ultimate flavour physics experiment at the high luminosity phase of the LHC.

Readout electronics of a prototype spectrometer for measuring low-energy ions in solar wind plasma

Readout electronics is developed for a prototype spectrometer for in situ measurement of low-energy ions of 30 eV/e–20 keV/e in the solar wind plasma. A low-noise preamplifier/discriminator (A111F) is employed for each channel to process the signal from micro-channel plate (MCP) detectors. A high-voltage (HV) supply solution based on a HV module and a HV optocoupler is adopted to generate a fast sweeping HV and a fixed HV. Due to limitation of telemetry bandwidth in space communication, an algorithm is implemented in an FPGA (field programmable gate array) to compress the raw data. Test results show that the electronics achieves a 1 MHz event rate and a large input dynamic range of 95 pC. A slew rate of 0.8 V/μs and an integral nonlinearity of 0.7-LSB for the sweeping HV, and a precision of less than 0.8 % for the fixed HV are obtained. A vacuum beam test shows an energy resolution of 12 ± 0.7 % full width at half maximum (FWHM) is achieved, and noise counts are less than 10/sec, indicating that the performance meets the physical requirement.

LHCb VELO upgrade

The upgrade of the LHCb experiment, scheduled for LHC Run-III, scheduled to start in 2021, will transform the experiment to a trigger-less system reading out the full detector at 40MHz event rate. All data reduction algorithms will be executed in a high-level software farm enabling the detector to run at luminosities of 2×1033cm−2s−1.The Vertex Locator (VELO) is the silicon vertex detector surrounding the interaction region. The current detector will be replaced with a hybrid pixel system equipped with electronics capable of reading out at 40MHz. The upgraded VELO will provide fast pattern recognition and track reconstruction to the software trigger. The silicon pixel sensors have 55×55μm2 pitch, and are read out by the VeloPix ASIC, from the Timepix/Medipix family. The hottest region will have pixel hit rates of 900Mhits/s yielding a total data rate of more than 3Tbit/s for the upgraded VELO. The detector modules are located in a separate vacuum, separated from the beam vacuum by a thin custom made foil. The foil will be manufactured through milling and possibly thinned further by chemical etching.The material budget will be minimised by the use of evaporative CO2 coolant circulating in microchannels within 400μm thick silicon substrates. The current status of the VELO upgrade is described and latest results from operation of irradiated sensor assemblies are presented.

The LHCb VELO upgrade

The upgrade of the LHCb experiment, planned for 2019, will transform the experiment to a trigger-less system reading out the full detector at 40MHz event rate. All data reduction algorithms will be executed in a high-level software farm. The upgraded detector will run at luminosities of 2×1033cm−2s−1 and probe physics beyond the Standard Model in the heavy flavour sector with unprecedented precision. The Vertex Locator (VELO) is the silicon vertex detector surrounding the interaction region. The current detector will be replaced with a hybrid pixel system equipped with electronics capable of reading out at 40MHz. The detector comprises silicon pixel sensors with 55×55μm2 pitch, read out by the VeloPix ASIC, based on the TimePix/MediPix family. The hottest region will have pixel hit rates of 900Mhits/s yielding a total data rate more than 3Tbit/s for the upgraded VELO. The detector modules are located in a separate vacuum, separated from the beam vacuum by a thin custom made foil. The detector halves are retracted when the beams are injected and closed at stable beams, positioning the first sensitive pixel at 5.1mm from the beams. The material budget will be minimised by the use of evaporative CO2 coolant circulating in microchannels within 400μm thick silicon substrates.

The LHCb VERTEX LOCATOR performance and VERTEX LOCATOR upgrade

LHCb is an experiment dedicated to the study of new physics in the decays of beauty and charm hadrons at the Large Hadron Collider (LHC) at CERN. The Vertex Locator (VELO) is the silicon detector surrounding the LHCb interaction point.The detector operates in a severe and highly non-uniform radiation environment.The small pitch and analogue readout result in a best single hit precision of 4 μm.The upgrade of the LHCb experiment, planned for 2018, will transform the entire readout to a trigger-less system operating at 40 MHz event rate. The vertex detector will have to cope with radiation levels up to 1016 1 MeVneq/cm2, more than an order of magnitude higher than those expected at the current experiment. A solution is under development with a pixel detector, based on the Timepix/Medipix family of chips with 55 x 55 μm pixels. In addition a micro-strip solution is also under development, with finer pitch, higher granularity and lower mass than the current detector. The current status of the VELO will be described together with recent testbeam results.

A 0.8 ps DNL Time-to-Digital Converter With 250 MHz Event Rate in 65 nm CMOS for Time-Mode-Based $\Sigma \Delta$ Modulator

A time-to-digital converter (TDC) is proposed to replace the multi-bit quantizer and the multi-bit feedback DAC of traditional voltage-mode ΣΔ modulator. Since time-mode systems process analog signals encoded in the time dimension rather than the voltage dimension, the proposed time-mode TDC makes the multi-bit ΣΔ ADC digital friendly and more suitable for nanometric technologies. A pulse-width-modulator (PWM) converts the sampled-and-held voltage-sample to a digital pulse whose width is proportional to the voltage level of the sample. Then, the TDC generates a digital code that corresponds to the pulse width. Simultaneously, the TDC provides a time-quantized feedback pulse for the ΣΔ modulator, emulating the voltage-DAC in a conventional ΣΔ ADC. Linearity, jitter and data-dependent-delay effects on the performance of the proposed architecture are analyzed. A chip prototype is fabricated in TI 65 nm digital CMOS process. THD of 67 dB is achieved which corresponds to a TDC's DNL of less than 0.8 ps without calibration. Measurements show that the ΣΔ-modulator achieves a dynamic range of 68 dB and the TDC consumes 5.66 mW at 250 MHz event rate while occupying 0.006 mm2.

Implementation and performance of the seeded reconstruction for the ATLAS event filter

ATLAS is one of the four major Large Hadron Collider (LHC) experiments that will start data taking in 2007. It is designed to cover a wide range of physics topics. The ATLAS trigger system has to be able to reduce an initial 40 MHz event rate, corresponding to an average of 23 proton-proton inelastic interactions per every 25 ns bunch crossing, to 200 Hz admissible by the Data Acquisition System. The ATLAS trigger is divided in three different levels. The first one provides a signal describing an event signature using dedicated custom hardware. This signature must be confirmed by the High Level Trigger (HLT) which using commercial computing farms performs an event reconstruction by running a sequence of algorithms. The validity of a signature is checked after every algorithm execution. A main characteristic of the ATLAS HLT is that only the data in a certain window around the position flagged by the first level trigger are analyzed. In this work, the performance of one sequence that runs at the Event Filter level (third level) is demonstrated. The goal of this sequence is to reconstruct and identify high transverse momentum electrons by performing cluster reconstruction at the electromagnetic calorimeter, track reconstruction at the Inner Detector, and cluster track matching.

The fast control system for HERA-B

The HERA-B experiment is dedicated to measure CP-violation in decays of neutral B-mesons. The B-mesons are produced in a nearly overwhelming background of inelastic proton-nucleon interactions. To reconstruct a sufficient number of B-decays the experiment has to be operated with multiple interactions at a 10 MHz event rate. A granularity of 540,000 channels is required. The challenge for the DAQ system is deadtimeless readout. This requires unprecedented speed of storing and labeling the data. A 50 kHz first level trigger rate needs a fast distribution of accepted-event identifiers. Ambitious plans for drift time measurements require a high precision time reference for the front end electronics. A fast control system has been developed to fulfil these requirements. The system consists of a VME-accessible mother unit with trigger and command processing logic, a two-stage signal distribution system and one individually configurable daughter module with timing adjustment capabilities in each of more than 200 front end electronics crates.