Abstract
In the Run-3 of LHCb, the High Level Trigger will have to process events at full LHC collision rate (30 MHz). This is a very challenging goal, and delegating some low-level tasks to FPGA accelerators can be very helpful by saving precious computing time. In particular, the 2D pixel geometry of the new LHCb VELO detector makes the cluster-finding process particularly CPU-time demanding. We realized and tested a highly parallel FPGA-based clustering algorithm, capable of performing this reconstruction in real time at 30 MHz event rate using a modest amount of hardware resources, that can be a viable alternative solution.
Highlights
19th International Workshop on Advanced Computing and Analysis Techniques in Physics Research, Saas Fee, Switzerland, 11-15 March 2019
Summary
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