The shrinkage of vertical feature sizes in VLSI allows the shrinkage of deep junctions like CMOS wells and buried subsurface layers. This has resulted in several attractive opportunities for the use of MeV implantation in VLSI and wafer scale integration. The beam current handling capabilities of presently available MeV machines limit these applications to those requiring doses of the order of 5 × 10 13ions/cm 2 or less, while space considerations limit the energies to less than 4 MeV. One set of applications is for the formation of CMOS wells. A few high energy implants can result in significant reduction in thermal annealing cycles for n and p-wells; better control over well dopant profiles can be used to decrease susceptibility to latchup, while simaltaneously increasing packing density. A second set of applications involve the fabrication of buried layers in the silicon substrate. One involves the formation of a buried grid for alpha-particle protection of circuits; a second uses a P-type buried layer in an n-well CMOS process, to reduce latchup. A third set of applications uses the energy of the ion to penetrate several thin film layers, allowing thresholds to be changed in transistors late in the processing sequence.