Signal Temporal Logic (STL) is a variant of Metric Temporal Logic (MTL) which can express intricate temporal requirements over signals, and has found wide adoption for expressing requirements over complex control systems models. A key factor in the success of STL has been that of quantitative robustness, and the development of efficient algorithms for computing the robustness values over traces. The real-valued quantitative robustness of a signal with respect to an STL property quantifies the degree of satisfaction or violation of the property by the signal. In this work we introduce a notion of robustness for a more expressive logic, Timed Signal Temporal Logic (TSTL), which can be seen as Timed Propositional Temporal Logic (TPTL) with predicates defined over real-valued signals. This logic can express many natural engineering requirements that STL cannot. We also develop algorithms for computing this robustness value over traces in the pointwise semantics. While the robustness computation for general TSTL formulae is PSPACEhard due to the PSPACE-hardness of the monitoring problem for TPTL, for the special case of one variable TSTL, a fragment of TSTL which is still more expressive than STL, we develop an optimized algorithm which computes robustness in time linear in the length of the trace. Finally, we experimentally validate the tractability of our algorithms with our prototype tool in Matlab.
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