Metal Interconnects Research Articles

Digital Etching of Molybdenum Interconnects Using Plasma Oxidation

AbstractMolybdenum (Mo) has a high potential of becoming the material of choice for sub‐10 nm scale metal structures in future integrated circuits (ICs). Manufacturing at this scale requires exceptional precision and consistency, so many metal processing techniques must be reconsidered. In particular, present direct wet chemical etching methods produce anisotropic etching profiles with significant surface roughness, which can be detrimental to device performance. Here, it is shown that polycrystalline Mo nanowires can be etched uniformly using a cyclic two‐step “digital” method: the metal surface is first oxidized with isotropic oxygen plasma to form a layer of MoO3, which is then selectively removed using either wet chemical or dry isotropic plasma etching. These two steps are repeated in cycles until the intended metal recess is achieved. High uniformity of plasma oxidation defines the etching uniformity, and small metal recess per cycle (typically 1–2 nm) provides precise control over the etching depth. This method can replace wet etching where high etching precision is needed, enabling the reliable manufacturing of nanoscale metal interconnects.

Selecting alternative metals for advanced interconnects

Interconnect resistance and reliability have emerged as critical factors limiting the performance of advanced CMOS circuits. With the slowdown of transistor scaling, interconnect scaling has become the primary driver of continued circuit miniaturization. The associated scaling challenges for interconnects are expected to further intensify in future CMOS technology nodes. As interconnect dimensions approach the 10 nm scale, the limitations of conventional Cu dual-damascene metallization are becoming increasingly difficult to overcome, spurring over a decade of focused research into alternative metallization schemes. The selection of alternative metals is a highly complex process, requiring consideration of multiple criteria, including resistivity at reduced dimensions, reliability, thermal performance, process technology readiness, and sustainability. This Tutorial introduces the fundamental criteria for benchmarking and selecting alternative metals and reviews the current state of the art in this field. It covers materials nearing adoption in high-volume manufacturing, materials currently under active research, and potential future directions for fundamental study. While early alternatives to Cu metallization have recently been introduced in commercial CMOS devices, the search for the optimal interconnect metal remains ongoing.

Evaluating size effects on the thermal conductivity and electron-phonon scattering rates of copper thin films for experimental validation of Matthiessen’s rule

As metallic nanostructures shrink towards the size of the electronic mean free path, thermal conductivity decreases due to increased electronic scattering rates. Matthiessen’s rule is commonly applied to assess changes in electron scattering rates, although this rule has not been validated experimentally at typical operating temperatures for most of the electronic systems (e.g., near room temperature). In this study, we experimentally evaluate the validity of Matthiessen’s rule in determining the thermal conductivity of thin metal films by measuring the in-plane thermal conductivity and electronic scattering rates of copper (Cu) films with varying thicknesses (27 nm — 5 µm), microstructures, and grain boundary segregation. Comparing total electron scattering rates measured with infrared ellipsometry to infrared ultrafast pump-probe measurements, we find that the electron-phonon coupling factor is independent of film thickness, whereas the total electronic scattering rate increases with decreasing film thickness. Our findings provide experimental validation of Matthiessen’s rule for electron transport in thin metal films at room temperature and also introduce an approach to discern critical heat transfer processes in thin metal interconnects, which holds significance for the advancement of future CMOS technology.

Theoretical study of point defects on transport properties in metallic interconnections

During the line width reduction, electron scattering caused by various defects in metal interconnects increases dramatically, which causes leakage or short circuit problems in the device, reducing device performance and reliability. Point defects are one of the important factors. Here, using density functional theory and non-equilibrium Green's function methods, we systematically study the effects of point defects on the transport properties of metals Al, Cu, Ag, Ir, Rh, and Ru, namely vacancy defects and interstitial doping of C atom. The results show that the conductivity of all systems decreases compared to perfect systems, because defects cause unnecessary electron scattering. Since the orbital hybridization of the C atom with the Al, Cu and Ag atoms is stronger than that metals Ir, Rh and Ru, the doping of C atom significantly reduces the conductivity of metals Al, Cu and Ag compared to vacancy defects. In contrast, vacancy defects have a greater impact than doping on the transport properties of metals Ir, Rh and Ru, which is mainly attributed to the larger charge transfer of the host atoms around the vacancies caused by lattice distortion. In addition, metal Rh exhibits excellent conductivity in all systems. Therefore, in order to optimize the transport properties of interconnect metals, our work points out that the doping of impurity atoms should be avoided for metals Al, Cu and Ag, while the presence of vacancy defects should be avoided for metals Ir, Rh and Ru, and Rh may be an excellent candidate material for future metal interconnects.

Impact of Elongation Stress on Island-Bridge Shaped Oxide Thin-Film Transistors with Metal Interconnects for Stretchable Electronics Applications

Impact of Elongation Stress on Island-Bridge Shaped Oxide Thin-Film Transistors with Metal Interconnects for Stretchable Electronics Applications

Stiffness and Interface Engineered Soft Electronics with Large-Scale Robust Deformability.

Skin-like stretchable electronics emerge as promising human-machine interfaces but are challenged by the paradox between superior electronic property and reliable mechanical deformability. Here, a general strategy is reported for establishing robust large-scale deformable electronics by effectively isolating strains and strengthening interfaces. A copolymer substrate is designed to consist of mosaic stiff and elastic areas with nearly four orders of magnitudes modulus contrast and cross-linked interfaces. Electronic functional devices and stretchable liquid metal (LM) interconnects are conformally attached at the stiff and elastic areas, respectively, through hydrogen bonds. As a result, functional devices are completely isolated from strains, and resistances of LM conductors change by less than one time when the substrate is deformed by up to 550%. By this strategy, solar cells, wireless charging antenna, supercapacitors, and light-emitting diodes are integrated into a self-powered electronic skin that can laminate on the human body and exhibit stable performances during repeated multimode deformations, demonstrating an efficient path for realizing highly deformable energy autonomous soft electronics.

First-principles study of CoMn2O4-Cr2O3 coherent interface analysis

The CoMn2O4 coating can effectively protect the metallic interconnect of solid oxide fuel cells, which come into direct contact with the naturally occurring Cr2O3 on the matrix surface. However, the properties of CoMn2O4-Cr2O3 interface remain unclear. In this study, the first-principles calculations are utilized to investigate the atom staking, stability, and electronic properties of the CoMn2O4(101)-Cr2O3(001) interface, along with examining the diffusion behavior of Cr atom at the interface. By comparing the adhesion work, the most stable model is determined. Based on the most stable model, the results of electronic structure analysis show that Mn atoms providing vacant orbitals near the conduction band minimum, enhancing the overall conductivity of the interface. The projected density of states metal atoms validates the formation priority of Cr-O bonds. The climbing image nudged elastic band (CI-NEB) method is used to simulate the interstitial diffusion properties of Cr atom at the interface, revealing that the energy barrier is about 3.05 eV. The diffusion coefficients of Cr atom are calculated accordingly. The obtained results can provide theoretical support for relevant experiments and deepen the understanding of the protective effects of spinel coatings on metallic interconnects of solid oxide fuel cells.

Study of selective etching of TaN with respect to SiOCH dielectrics using SiF4 plasma processes

TaN is used as a Cu diffusion barrier during metal interconnect formation to enable modern chip fabrication. In this study, the selective removal of TaN with respect to SiOCH dielectrics is explored using neutral dominant plasmas containing pure SiF4 or with O2 or H2 additives. SiF4 is studied because the Si-containing gas has been historically used to deposit Si-based films, but the gas also contains F capable of volatilizing Ta. This work explores the possibility of enabling both selective etching of TaN and selective deposition on SiOCH. SiF4 discharges are impacted by the addition of O2 and H2 gases; exhibiting significantly different deposition and etching regimes. The substrate temperature plays a critical role in modulating the TaN etching versus deposition window compared to SiOCH. Through this work, selective etching of TaN with respect to SiOCH is achieved.

Powder Bed Fusion Techniques in Metal 3D Printing: A Review

The use of 3D printing (additive manufacturing) with metal has grown significantly in demand recently, greatly reducing the time and expense required to produce complex interconnected metal components. This method minimizes material wastage, facilitates material recycling, and eliminates the need for support materials. Among the various Metal Additive Manufacturing techniques, Powder Bed Fusion (PBF) processes stands out as the most prevalent for manufacturing parts. Within the realm of PBF, electron beam melting technique, selective laser sintering technique, and selective laser melting technique are the primary methods employed. Selective laser melting and selective laser sintering operate without the need for any special conditions, unlike EBM, which necessitates a vacuum environment. Regarding the choice of materials, laser melting/sintering processes are suitable for almost all types of metals except those which surpasses beam melting capabilities. While electron beam melting is constrained to a few materials such as titanium alloys, cobalt and chromium alloys, and nickel alloys, whereas selective laser melting and sintering allows for a broad range of materials, including iron and steel alloys. However, electron beam melting exhibit the ability to process brittle materials that would typically be challenging for melting and sintering through laser. Nevertheless, the ductility, yield testing, and ultimate testing of materials created through EBM are inferior to those processed by laser methods. Although all PBF techniques excel at creating complex structures, finishing products to have a smooth surface directly over a rough surface remains a subject of ongoing research. To attain suitable mechanical properties such as hardness, tensile strength, and endurance, critical process factors include power of laser or beam, speed for scanning, density for powder bed, thickness of laser or beam, and material characteristics. Inadequate material selection coupled with incorrect process settings can lead to issues such as porosity, slag formation, and other flaws.

Coupled Electrical – Thermal – Electrochemical Model of a Battery Module

A battery module comprises of several lithium-ion cells connected in series and parallel configuration to obtain the desired voltage, current and power specifications. The overall response of a module can be affected by (i) the electrical topology, (ii) the thermal topology and (iii) the cell-to-cell variations. The distribution of current depends on the series/parallel assembly and variation in interconnect resistance in the module. Operation of a cell is accompanied by an increase in temperature. In a module, the thermal environment seen by a cell is different depending on whether it is an interior cell or a cell at the boundary of module exposed to environment. There is additional thermal cross talk between cells through heat conduction in metallic interconnects. Finally, there can be several reasons for cell-to-cell variation in a module. The cells used for building a module can have variable state of charge and internal resistance at the manufacturing level. As the module is cycled, the ageing of cells in a module can differ due to variation in current, evolution of range of lithiation of electrodes and the temperature of the cell.In this research work, we develop a coupled electrical, thermal, and electrochemical model to simulate the charge and discharge of a battery module with the overall aim of identifying the cell with largest performance degradation and most likelihood of failure. This physics-based modeling approach comprises of a simplified electrochemical and lumped thermal model of an individual cell. At the module level, the modeling framework is extended to include the electrical and thermal connectivity along with the electrochemical response.

Moore's Law Scaling and Chemical Mechanical Planarization (CMP)

Since the invention of the first integrated circuit in 1958, chemistry and materials have played a critical role in semiconductor process technologies, which has led to an exponential growth of transistors packed into circuits. Decades ago, Gordon Moore posited there would be a doubling of components every two years (revised from his original doubling every one-year prediction). This observation became known as Moore’s law.As Denard scaling took on more complexity, the number of new materials used to build semiconductors increased at a torrid pace. The number of elements in the periodic table, used to fabricate devices, increased roughly five-fold from the 1980’s to the 2000’s.In the earlier years, lithography, etch, thin films, implant, and diffusion were foundational technologies used to fabricate a silicon wafer into hundreds of microchips. In the late 1980’s a new technology Chemical Mechanical Planarization (CMP) was invented. It was developed out of necessity to reduce topography, critical for lithography’s depth of focus requirements. Without this key invention, patterning and building layer upon layer from front end transistors to back-end interconnects would not have been possible.Intel implemented CMP into manufacturing in the early 1990’s on the 0.8 micron technology node which manufactured the 486 microprocessor. CMP was required to planarize dielectric oxide used to insulate the aluminum metal interconnects. Since then, the number of CMP applications over the last three decades has exploded, enabling the scaling of Moore’s Law.CMP is not only used to improve lithography depth of focus. CMP also enables a method of metal interconnect and contact formation called damascene. Planarization is used to create dielectric isolation trenches, discrete plugs for insulation, aid advanced patterning architectures, build through silicon vias (TSVs), and enable complex wafer and chip bonding for die-to-die interconnects for disaggregated products.Transistor scaling alone is no longer sufficient to meet device performance, power, and cost requirements. Complex material and architectural changes are required. And novel CMP applications continue to be added at each new technology node. This author will make an argument that CMP is critical to push scaling and enable future process nodes. Figure 1

Next Generation Heterogeneous 3D IC Chip Packaging

The demand for a faster and more efficient IC has been steadily increasing more than ever to accommodate the trend of Artificial Intelligence, Industry 4.0, Machine Learning, and Big Data. Traditionally, the semiconductor industry has kept up with demand of faster and more efficient IC by shrinking the size of transistor. As we approach a 1 nm transistor the technological challenge will be challenging to overcome as quantum tunneling becomes more pronounced and would decrease the reliability of the chip. To overcome this technological challenge, an advance packaging of 3D IC chip technology has been developed and delivered to market such as CoWoS (Chip-on-Wafer-on-Substrate) and InFO (Integrated Fan-Out). However, the aforementioned technology have their drawbacks with CoWoS uses interposer and TSV (through-silicon substrate via) which make it costly, time consuming, and wastes a lot of energy and InFO is limited in the number of layers it can accommodate for chiplets. Both of those technology are currently limited to 2 or 3 layer of IC and difficult to be modularize. In this study, we aim to develop a heterogeneous 3D IC package that can overcome the aforementioned problem which is modular, cost-effective, able to integrate chip from different manufacturers, and capable to stack more than 3 layers of ICs. This study has successfully completed the first stage of development by employing an advanced package consisting of Epoxy substrate with 200Å Ti/500Å Pt/1000Å Au metal interconnects, previously fabricated as a base for 3D stacking. Keywords : 3D IC Package, Advance Packaging, Modulable IC Packaging, Heterogeneous Integration Figure 1

Investigation of Cu Corrosion Defects Induced by Humidity Imbalance in the Cu Damascene Process of Semiconductors

As integrated circuit design rules shrink in semiconductor, Copper (Cu) has been employed as the back end of line (BEOL) interconnect metal to enhance device performance through reduced resistivity and resistive-capacitive delay.[1] However, Cu metal lines are prone to degradation caused by Cu oxidation-induced defects, including extrusions and voids, owing to their inherent properties.[2] Consequently, it becomes essential to regulate the oxidation rate during the chip fabrication process, particularly when the Cu metal line is exposed during the Damascene process. This control is crucial for ensuring long-term reliability and achieving a higher yield.[3]From the learning of earlier technological nodes, we are aware to and already precisely controlling both process queue time and wafer surface humidity. We must exercise control over the queue time, addressing both inter-process intervals and in-process queuing. [4] This underscores the importance of managing queue time and maintaining low environmental humidity to mitigate wafer surface defects when the FOUP (Front Opening Unified Pod) is opened at the EFEM (Equipment Front End Module).[5] Those humidity and queue times related Cu corrosion defects have been mitigated by N2 purge in FOUP and reducing the wafer quantity. However, dividing the lot, typically consisting of 25 wafers, by half or less to reduce queue times leads to an imbalance in low humidity due to N2 purging. This occurs when the FOUP is opened in EFEM.This paper examines Cu corrosion under low humidity conditions in a FOUP with a small quantity of wafers, specifically examining the influence of queue time during N2 purging in the EFEM. Through simulation of the interaction between the inlet air entering the EFEM and the purged N2 gas, a vulnerable area is identified where copper oxidation takes place. In addition, we propose an arrangement to mitigate high humidity, supported by experiments conducted under real equipment conditions.Fig. 1 shows Cu corrosion defects after ILD etching at around 20% RH in the FOUP. This defect is only observed in the lower slot of the FOUP on the N2 purged load port. Figure 2 illustrates a chart depicting the humidity inside the FOUP under various conditions. The humid region within the FOUP when opened on the N2 purged load port without wafers. (Fig.2a) While the extent of the humid area is contingent upon the flow rate of the N2 purge and the intake of air through the Fan Filter Unit (FFU), the vortex of the inlet air from the cleanroom (<42% RH) is notably observed at the bottom and front side of the FOUP. Therefore, wafers stored in the lower slot of the FOUP face an increased risk of Cu corrosions when subjected to elevated humidity levels during processes like ILD etching and subsequent cleaning. Specifically, an extended queue time amplifies the probability of Cu defects occurring in this high-humidity slot compared to slots with lower humidity. We observed an unintended increase to 28.2% RH in specific configurations when reducing the quantity of wafers to minimize queue time. (Fig. 2b)Hence, we propose an arrangement for wafers that maintains low humidity with small quantity. When placing 12 wafers in the FOUP, an arrangement with equal spacing from the first slot to the 25th slot ensures uniform N2 flow, thereby reducing the highest humidity from 28.2% RH to 14.0% RH by half. (Fig.3a) Alternatively, positioning all wafers on the upper section is another method. (Fig.3b) Therefore, by halving the quantity of wafers and reducing the process wait time by half, and applying the optimal wafer arrangement that maintains low humidity balance even with a small number of wafers, we confirmed the absence of Cu corrosion.

Leveraging Adsorption Kinetics and Thermodynamics in a Channel-Pore Interconnected Metal–Organic Framework for Stepwise Splitting Hexanes

Leveraging Adsorption Kinetics and Thermodynamics in a Channel-Pore Interconnected Metal–Organic Framework for Stepwise Splitting Hexanes

Simulation-Guided Analysis towards Trench Depth Optimization for Enhanced Flexibility in Stretch-Free, Shape-Induced Interconnects for Flexible Electronics.

In this paper, we present an optimization of the planar manufacturing scheme for stretch-free, shape-induced metal interconnects to simplify fabrication with the aim of maximizing the flexibility in a structure regarding stress and strain. The formation of trenches between silicon islands is actively used in the lithographic process to create arc shape structures by spin coating resists into the trenches. The resulting resist form is used as a template for the metal lines, which are structured on top. Because this arc shape is beneficial for the flexibility of these bridges. The trench depth as a key parameter for the stress distribution is investigated by applying numerical simulations. The simulated results show that the increase in penetration depth of the metal bridge into the trench increases the tensile load which is converted into a shear force Q(x), that usually leads to increased strains the structure can generate. For the fabrication, the filling of the trenches with resists is optimized by varying the spin speed. Compared to theoretical resistance, the current-voltage measurements of the metal bridges show a similar behavior and almost every structural variation is capable of functioning as a flexible electrical interconnect in a complete island-bridge array.

A review of emerging trends in photonic deep learning accelerators

Deep learning has revolutionized many sectors of industry and daily life, but as application scale increases, performing training and inference with large models on massive datasets is increasingly unsustainable on existing hardware. Highly parallelized hardware like Graphics Processing Units (GPUs) are now widely used to improve speed over conventional Central Processing Units (CPUs). However, Complementary Metal-oxide Semiconductor (CMOS) devices suffer from fundamental limitations relying on metallic interconnects which impose inherent constraints on bandwidth, latency, and energy efficiency. Indeed, by 2026, the projected global electricity consumption of data centers fueled by CMOS chips is expected to increase by an amount equivalent to the annual usage of an additional European country. Silicon Photonics (SiPh) devices are emerging as a promising energy-efficient CMOS-compatible alternative to electronic deep learning accelerators, using light to compute as well as communicate. In this review, we examine the prospects of photonic computing as an emerging solution for acceleration in deep learning applications. We present an overview of the photonic computing landscape, then focus in detail on SiPh integrated circuit (PIC) accelerators designed for different neural network models and applications deep learning. We categorize different devices based on their use cases and operating principles to assess relative strengths, present open challenges, and identify new directions for further research.

Utilizing H2S to sulfurize transition metal and oxide barriers for suppressing resistivity scaling of ruthenium metallization

Ruthenium is of great potential for use as next-generation interconnect metallization but still suffers from resistivity scaling at nanoscale linewidths due to the severe interface scattering of electrons. In this study, a thin sulfurized layer was hence formed on titanium-tantalum and titanium-tantalum oxide barriers by utilizing hydrogen sulfide gas for interface modification. The microstructure, chemical composition, bonding configuration and interfacial adhesion of the sulfurized barriers and ruthenium films were investigated, and the resistivity scaling of the ruthenium films on the barriers was evaluated. Experimental results indicate that an amorphous sulfide layer of only several nanometers thick was uniformly formed on the top surface of the barriers and changed the resistivity and binding state of the metal and oxide barriers. Attributed to the formation of the sulfide layer, the specular scattering of electrons at the ruthenium/barrier interface was enhanced, effectively suppressing the resistivity scaling of the ruthenium films, and the interfacial adhesion strength was also markedly improved.

Unveiling niobium pentoxide and cerium oxide-dispersed ferritic stainless steel for solid oxide fuel cells interconnects

Herein, the effect of niobium pentoxide (Nb2O5) and nano-sized cerium oxide (CeO2) on oxidation behavior and area specific resistance (ASR) of the ferritic stainless steel has been investigated for the development of robust metallic interconnects. An oxide-dispersed ferritic stainless steel alloy is fabricated using the powder metallurgy (PM) process. The morphologies of the alloy before and after oxidation are observed through Scanning Electron Microscope (SEM), Scanning Transmission Electron Microscopy (STEM) and Secondary Ion Mass Spectrometry (SIMS) analyses. Addition of Nb2O5 in the alloy formed a C14 Laves phase of (Fe, Cr)2(Nb, Si). The Laves phase and CeO2 controlled the oxidation behavior of the ferritic stainless steels, consequently reducing the oxide scale thickness and improving the ASR. An alloy with 1 wt% Nb2O5 and 3 wt% CeO2 showed an ASR value of 27.1 mΩ cm2 at 800 °C for 1000 h, which is similar to the ASR value of the commercial Fe–Cr alloy. The results of this study indicate that Nb2O5 and CeO2-dispersed ferritic stainless steel using the PM process can be more advantageous than the conventional process for manufacturing metallic interconnects with complex shapes and reducing production costs.

Highly robust and porous cathode current collecting layer for flat-tubular solid oxide fuel cell stack applications

Solid oxide fuel cells (SOFCs) have gained great attention as a stationary power generation application due to their high efficiency, fuel flexibility and environmental friendliness. The devices and power age could be revolutionized with the commercialization of these technologies. The SOFC-based stationary power generator is one step closer to commercialization however, it is delayed due to the inherent bottleneck of insufficient long-term durability. The cathode current collecting layer (CCCL) is crucial in stack applications to minimize the contact loss between cell and metallic interconnects. Herein, we report an easy-to-fabricate and highly robust CCCL to boost electrochemical performance and long-term durability of flat tubular (FT) short stack. The tailored structure of the CCCL was employed in the fabrication of the FT short-stack. The G/Ag porous structure exhibited increased porosity of 61.2 %, thereby enhancing the mass transport and improving the overall performance and long-term durability. The four-cell FT stack was manufactured without an interconnect and open air-gas channel. Subsequently, the FT short-stack is tested for performance and long-term durability for elapsed 5000 h at a chronopotentiometry test. The porous layer of graphite/Ag on the cathode layer maintained structural integrity without defects and mechanical failure. Consequently, the stack voltage remains stable throughout operation owing to improved structural stability and uniform temperature distribution across four FT cell stack.

Stretch-tolerant interconnects derived from silanization-assisted capping layer lamination for smart skin-attachable electronics

Flexible strain sensor arrays hold great promise in on-skin monitoring of human signals and activities. Despite the development of strain-sensitive materials and patterning technologies for improved performance and device integration, the metal film serving as interconnects is always vulnerable upon stretch, which hinders the operation under large strains. Herein, a novel strategy is developed for achieving stretch-tolerant interconnects within a sensor array. Through introducing a high-modulus capping layer for the deposition of Ag interconnects, followed by silanization-assisted lamination onto the stretchable substrate where strain-sensitive graphene patches are inkjet-printed, the deformation of Ag interconnects is largely suppressed upon the global strain of the device, and a high working range of 40 % strain is achieved. Moreover, the chemical bonding between the capping layer and the stretchable substrate ensures a stable contact between the electrode and the sensitive layer under vigorous bending. The as-prepared sensor array demonstrates high sensitivity (gauge factor (GF) > 100) within a wide range (18 %), and could reliably monitor various physiological signals and human activities. A machine learning-assisted wearable gesture recognition system is developed based on the sensor array and a convolutional neural network (CNN), which could distinguish from 10 defined gestures with 100 % accuracy after 14 training processes. The facile and effective strategy could be universally applied for metal interconnects protection under stretch, and dramatically facilitate the design of smart flexible electronics.