Metal Oxide Semiconductor Field Transistors Research Articles

Stress Impact of the Annealing Procedure of Cu-Filled TSV Packaging on the Performance of Nano-Scaled MOSFETs Evaluated by an Analytical Solution and FEA-Based Submodeling Technique.

Stress-induced performance change in electron packaging architecture is a major concern when the keep-out zone (KOZ) and corresponding integration density of interconnect systems and transistor devices are considered. In this study, a finite element analysis (FEA)-based submodeling approach is demonstrated to analyze the stress-affected zone of through-silicon via (TSV) and its influences on a planar metal oxide semiconductor field transistor (MOSFET) device. The feasibility of the widely adopted analytical solution for TSV stress-affected zone estimation, Lamé radial stress solution, is investigated and compared with the FEA-based submodeling approach. Analytic results reveal that the Lamé stress solution overestimates the TSV-induced stress in the concerned device by over 50%, and the difference in the estimated results of device performance between Lamé stress solution and FEA simulation can reach 22%. Moreover, a silicon–germanium-based lattice mismatch stressor is designed in a silicon p-type MOSFET, and its effects are analyzed and compared with those of TSV residual stress. The S/D stressor dominates the stress status of the device channel. The demonstrated FEA-based submodeling approach is effective in analyzing the stress impact from packaging and device-level components and estimating the KOZ issue in advanced electronic packaging.

Al passivation effect at the HfO2/GaAs interface: A first-principles study

III–V semiconductor interfacing with high-k dielectrics is critical for the high mobility metal oxide semiconductor field transistor (MOSFET) device. In this work, we utilize first-principles method to explore the electronic structures of the interface GaAs/HfO2 with the presence of Al interfacial defects. The simulation results indicate that Al substitutions & interstitials tend to increase the thermal stability of the interface. Meanwhile, this substitution removes the lower-half gap states of GaAs, partially passivating the interface and consequently suppressing the gap states. Also, we find that the band offset displays a dependence on the point defects of Al replacements of interfacial Hf and Ga.

Drain-induced barrier-lowering effect in surrounding-gate schottky barrier metal-oxide semiconductor field transistor

Based on surrounding-gate schottky barrier metal-oxide semiconductor field transistor (MOSFET) structure, the distribution of surface potential is obtained by solving two-dimensional Poisson equation in cylindrical coordinates, and the threshold voltage model of surrounding-gate schottky barrier NMOSFET which is applicable to the low voltage of drain is built. According to the calculation results, the dependences of threshold voltage and drain-induced barrier-lowering on voltage of drain, channel radius and channel length are studied in detail, which can provide some reference for the design of surrounding-gate schottky barrier MOSFET device and circuit.

Mechanical tensile strain induced gate and substrate currents change in n and p-channel metal-oxide-semiconductor field-effect transistors

To investigate and understand the reliability behavior of strained silicon devices, the changes of gate currents (Ig) and substrate currents (Isub) in n and p-channel metal-oxide-semiconductor field-transistors (MOSFETs) under different types of mechanically applied tensile stresses have been studied. It has been observed that, under the uniaxial tensile stress, both Ig and Isub of pMOSFETs increase with the increase of applied stress under the inversion and the accumulation conditions. However, an opposite stress dependence in nMOSFETs has been observed for Ig and Isub in both the inversion and the accumulation regimes. Similar changes have been found for Ig and Isub of nMOSFETs under biaxial tensile stress. The observations are explained by the strain induced band structure modulation and the repopulation of carriers.

Drain-induced barrier-lowering effects on threshold voltage in short-channel strained Si metal-oxide semiconductor field transistor

Based on strained silicon metal-oxide semiconductor field transistor (MOSFET) structure, the distribution of surface potential is obtained by solving two-dimensional Poisson equation, and the threshold voltage model is built. According to calculation results, the dependence of threshold voltage on germanium content of relaxed Si1－βGeβ, channel length, voltage of drain, doping content of substrate and channel are studied in detail, and the influence of drain-induced barrier-lowering on scaled strained silicon MOSFET is obtained, which can provide important reference for the design of strained silicon MOSFET device and circuit.

Charge trapping and detrapping characteristics in hafnium silicate gate dielectric using an inversion pulse measurement technique

Threshold voltage (VTH) instability in metal oxide semiconductor field transistors (MOSFETs) with high dielectric constant (k) gate dielectrics has been investigated with an inversion pulse measurement technique, which can detect fast dielectric charging/discharging within microseconds (μs). The results indicate that VTH instability can be significantly underestimated by conventional VTH measurement techniques. Based on temperature-dependent stress data, it is suggested that charging and discharging are determined by direct tunneling and thermally assisted processes, respectively.

The effect of transition region on the direct tunneling current and Fowler–Nordheim tunneling current oscillations in ultrathin MOS structures

The effects of transition region on direct tunneling and Fowler–Nordheim (FN) tunneling in ultrathin metal–oxide–semiconductor field transistors are investigated by numerical analysis. Direct tunneling current in ultrathin gate oxide is shown to increase with the width of transition region. The applied voltage across the oxide at the maximum and minimum of FN tunneling current oscillations is observed to increase with the width of the transition region, and its relative increase also strongly depends on the width. Furthermore, the amplitude of FN tunneling current oscillations descends with the width of transition region, however, its attenuation factor trends to increase with the width. Usually the amplitude and its attenuation factor decrease with the ordinal number of current oscillation increasing. So the effect of the transition region on FN tunneling current oscillations may be used to extract the information about the transition region.

Numerical analysis for the effects of SiO 2/Si interface roughness on quantum oscillations in ultrathin MOSFETs

Interface roughness effects on quantum oscillations in ultrathin metal-oxide-semiconductor field transistors (MOSFETs) are investigated by numerical analysis. The interface roughness is described in terms of Gauss distribution. Quantum oscillations in ultrathin gate oxides are shown to be little damped by SiO 2/Si interface roughness. The applied voltage shift at the extreme of quantum oscillations increases linearly with SiO 2/Si interface roughness increasing. This means that this shift may be used to obtain the information about the interface roughness as an inexpensive and simple tool.

Miniaturization of an electron device using inverse problem methodology

The miniaturization of electron devices has its advantages in dense circuits and high frequency devices. As can be seen in the current literature, considerable effort is devoted on the problem miniaturizing modern electronic devices to allow high speed and high density. Considering the effects in short channel metal oxide semiconductor field transistors (MOSFET), in practice the device is scaled to preserve the long-channel characteristics after miniaturization. Several parameters are chosen and their sensitivity analysis is used for the miniaturization of a MOSFET. The objective is to miniaturize the device in such away to avoid the break down effects at high bias. A finite element based constrained inverse problem methodology is used for the first time for the miniaturization of a MOSFET device.