Gate Metal Oxide Semiconductor Field Effect Transistor Research Articles

Design and Analysis of Heavily Doped n+ Pocket Asymmetrical Junction-Less Double Gate MOSFET for Biomedical Applications

The Complementary Metal-Oxide Semiconductor (CMOS) technology has evolved to a great extent and is being used for different applications like environmental, biomedical, radiofrequency and switching, etc. Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET) based biosensors are used for detecting various enzymes, molecules, pathogens and antigens efficiently with a less time-consuming process involved in comparison to other options. Early-stage detection of disease is easily possible using Field-Effect Transistor (FET) based biosensors. In this paper, a steep subthreshold heavily doped n+ pocket asymmetrical junctionless MOSFET is designed for biomedical applications by introducing a nanogap cavity region at the gate-oxide interface. The nanogap cavity region is introduced in such a manner that it is sensitive to variation in biomolecules present in the cavity region. The analysis is based on dielectric modulation or changes due to variation in the bio-molecules present in the environment or the human body. The analysis of proposed asymmetrical junctionless MOSFET with nanogap cavity region is carried out with different dielectric materials and variations in cavity length and height inside the gate–oxide interface. Further, this device also showed significant variation for changes in different introduced charged particles or region materials, as simulated through a 2D visual Technology Computer-Aided Design (TCAD) device simulator.

Impact of strained channel on electrical properties of Junctionless Double Gate MOSFET

Application of strained channel in Metal-oxide-semiconductor Field Effect Transistors (MOSFET) technology influences the electrical properties due to the significant changes in the energy band structure of silicon lattices. Thus, in this paper, a comprehensive analysis is conducted to investigate the impact of strained channel towards several electrical properties of junctionless double-gate MOSFET. The comparative analysis is carried out by simulating two different sets of device structure which are JLDGM device (without strain) and junctionless double-gate strained MOSFET (JLDGSM) device. The results show that the strained channel has improved the on-state current (ION), on-off ratio, transconductance (gm) and transconductance generation factor (TGF) by approximately 58 %, 98%, 98%, and 44% respectively. The significant improvement is mainly attributed to the presence of biaxial strain boosting the electron mobility in the channel. The intrinsic gate delay (τint) has significantly reduced by approximately 52% as the strained channel is applied. Since the variation of intrinsic gate capacitances (Cint) is very minimal (4%) as the strained channel is applied, the gate delay is dominantly governed by the drain current. However, the application of strain channel has increased the dynamic power dissipation (Pdyn) for approximately 19% mainly due to slightly increased intrinsic gate capacitances.

Surface Potential modeling of Dual Metal Gate-Graded Channel-Dual Oxide Thickness with two dielectric constant different of Surrounding Gate MOSFET

An Analytical study for the surface potential, threshold voltage and Subthreshold swing (SS) of Dual-metal Gate Graded channel and Dual Oxide Thickness with two dielectric constant different cylindrical gate surrounding-gate (DMG-GC-DOTTDCD) metal–oxide–semiconductor field-effect transistors (MOSFETs) is proposed to investigate short-channel effects (SCEs). The performance of the modified structure was studied by developing physics-based analytical models for the surface potential, threshold voltage shift, and Subthreshold swing. It is shown that the novel MOSFET could significantly reduce threshold voltage shift and Subthreshold swing, can also provides improved electron transport and reduced short channel effects (SCE). Results reveal that the DMG-GC-DOTTDCD devices with different dielectric constant offer superior characteristics as compared to DMG-GC-DOT devices. The derived analytical models agree well with simulation by ATLAS.

Mathematical Modeling and Simulation of Junction less Dual Material Double Gate MOSFET with Various Work Functions

In view of the 2-Dimensional game plan of Poisson's condition, a material science-based model of Double Gate Dual Material Junction less (DGDMJNL) Metal-Oxide-Semiconductor Field Effect Transistor (MOSFET) is made. The advantages of different work capacities connected to the metals in DMDGJNL MOSFET are exhibited and the potential at the inside and qualities of the electric field is uncovered. The proposed model exhibits explicitly demonstrates the effect of the work in electrostatic potential and electric field. It is exhibited that the execution of DMDGJNL MOSFET can be changed by adjusting the channel length extents of control door and shield entryway. The model is assessed by its figured results and those got from a 3D TCAD test system for numerical outcomes.

Hybrid OpenMP-CUDA parallel implementation of a deterministic solver for ultrashort DG-MOSFETs

The simulation of ultrashort two-dimensional double gate metal-oxide semiconductor field-effect transistors and similar semiconductor devices through a deterministic mesoscopic, hence accurate, model can be very useful for the industry: It can provide reference results for macroscopic solvers and properly describe weakly charged zones of the device. For the scope of this work, we use a Boltzmann–Schrödinger–Poisson model. Its drawback is being particularly costly from the computational point of view, and a purely sequential code may take weeks to simulate high voltages. In this article, we develop a hybrid parallel solver for a graphics processing unit (GPU)-based platform. In order to accelerate the simulations, the Boltzmann transport equations are solved on GPU using the CUDA programing model, while the Schrödinger–Poisson block is performed on multicore CPUs using OpenMP. We have adapted the costliest computing phases to the GPU in an efficient manner, achieving high performance and drastically reducing the simulation time. We give details about the parallel-design strategy and show the performance results.

Design Consideration and Impact of Gate Length Variation on Junctionless Strained Double Gate MOSFET

Aggressive scaling of Metal-oxide-semiconductor Field Effect Transistors (MOSFET) have been conducted over the past several decades and now is becoming more intricate due to its scaling limit and short channel effects (SCE). To overcome this adversity, a lot of new transistor structures have been proposed, including multi gate structure, high-k/metal gate stack, strained channel, fully-depleted body and junctionless configuration. This paper describes a comprehensive 2-D simulation design of a proposed transistor that employs all the aforementioned structures, named as Junctionless Strained Double Gate MOSFETs (JLSDGM). Variation in critical design parameter such as gate length (Lg ) is considered and its impact on the output properties is comprehensively investigated. The results shows that the variation in gate length (Lg ) does contributes a significant impact on the drain current (ID), on-current (ION), off-current (IOFF), ION/IOFF ratio, subthreshold swing (SS) and transconductance (gm). The JLSDGM device with the least investigated gate length (4nm) still provides remarkable device properties in which both ION and gm(max) are measured at 1680 µA/µm and 2.79 mS/µm respectively

Gate Length Effect on Gallium Nitride Based Double Gate Metal-Oxide-Semiconductor Field-Effect Transistor

We have investigated the performance of Gallium Nitride (GaN) based Double-Gate (DG) Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET). Atlas Device Simulation Framework -Silvaco has been used to access Non-Equilibrium Green Function to distinguish the transfer characteristics curve, ON state current (ION), OFF-state current (IOFF), Drain Induced Barrier Lowering (DIBL), Subthreshold Swing, Electron Current Density, Conduction Band Energy and Electric Field. The concept of Solid state device physics on the effect of gate length studied for the next generation logic applications. GaN-based DG MOSFETs shows better performance than Si-based Single gate MOSFETs. The proposed device has drawn the attention over conventional SG-MOSFET due to fas switching performance. The device turn on and turn off voltage is respectively VGS=1V(On state) and VGS-0V(OFF State). To validate our simulation tool and model results, previous research model has been investigated using Silvaco Atlas and the results obtained are compared to the previous results.

Two-Dimensional Potential and Threshold Voltage Modeling of Work Function Engineered Double Gate High-k Gate Stack Schottky Barrier MOSFET

Following the ongoing research trend towards the development of nonconventional metal–oxide–semiconductor field-effect transistor (MOSFET) structures to reduce the detrimental influence of various short-channel effects associated with the continual miniaturization of device dimensions through several technology nodes, we have explored a Schottky barrier symmetric double gate (DG) MOSFET incorporating the concepts of gate engineering and dielectric engineering, viz. a work function engineered double gate Schottky barrier MOSFET with high-k gate stack. The study primarily addresses issues related to the source–channel and drain–channel junctions of highly scaled devices by considering metallic source and drain regions to benefit from the barrier height lowering at the metal–semiconductor junctions along with reduced contact resistances, which improves the performance of the proposed device in terms of surface potential, electric field, threshold voltage roll-off, drain-induced barrier lowering, etc. The results obtained from detailed two-dimensional threshold voltage modeling are found to be in excellent agreement with the simulation results, validating the presented analytical model.

Understanding the Impact of Time-Dependent Random Variability on Analog ICs: From Single Transistor Measurements to Circuit Simulations

Advanced scaling and the introduction of new materials in the metal–oxide–semiconductor field-effect transistor (MOSFET) raise concerns about its reliability. Several degradation mechanisms, depending on operating conditions and time, can cause a significant change of the transistor parameters. The transistor area plays a large role when it comes to aging. In large-area MOSFETs, aging appears deterministic, while in small-area devices it is stochastic and convoluted with random telegraph noise. This is analogous to the time-zero random variability, which also reduces as the transistor gate area increases. The scope of this paper is to extend the knowledge of the time-dependent random variability as a function of MOSFET gate area scaling. The goal is to aid the designers in transistor sizing toward a more reliable design. As an example, the impact of time-dependent random variability is illustrated for an analog-to-digital converter.

Comprehensive Characterization of the 4H-SiC Planar and Trench Gate MOSFETs From Cryogenic to High Temperature

In this article, the static, dynamic, and short-circuit properties of 1.2-kV commercial 4H-SiC planar and trench gate metal–oxide–semiconductor field-effect transistors (MOSFETs) are compared and analyzed in a wide temperature range from 90 to 493 K. The temperature-dependent specific ON-resistance ( ${R}_{\text {sp}- \mathrm{\scriptscriptstyle ON}}$ ) and threshold voltage ( ${V}_{\text {th}}$ ) are analyzed in relation to the density of the interface state. The turn-on rise and turn-off fall times ( ${T}_{r}$ and ${T}_{f}$ ) and the corresponding energy loss ( ${E}_{r}$ and ${E}_{f}$ ) are extracted from a double-pulse test from cryogenic to high temperature and analyzed. The short-circuit capability of the two structures is studied at low temperature for the first time. The comprehensive comparison and analysis of the planar and trench gate MOSFET versus temperature in this work show the importance to study applications with SiC MOSFETs in a wide temperature range, especially for the cryogenic temperatures.

Threshold Voltage Characteristics for Silicon Nanowire Field-Effect Transistor With a Double-Layer Gate Structure

In this paper, the threshold voltage characteristics of silicon nanowire metal–oxide–semiconductor field-effect transistor (MOSFET) with a double-layer gate structure are presented. This type of device is considered to be the most promising application of nanodevice in ultralarge-scale integration, due to several advantages such as similar operation principle as the junctionless nanowire transistor, the screening effect of the upper gate (UG) to shield the lower gate MOSFETs from external electromagnetic disturbance, the tradeoff between the short channel and the thick-gate oxide layer, and the compatible fabrication process with the conventional MOS technology. In this paper, the relations of threshold voltage versus the gate length, the UG bias, the substrate bias, the drain bias, and the temperature are measured and analyzed. Moreover, the penetration effect of the UG electric field is proposed to interpret the short-channel characteristics of the device, and a piecewise curve model is presented to reveal the underlying physics of the relation of the threshold voltage versus the drain bias. The double-layer gate structure technology enables the design of many devices, such as small-signal analog circuit units, single-electron devices, and quantum bit cells.

(Keynote) Silicon-Germanium: Enabler of Moore's Law

Exponential growth in the number and capability of computing and communication devices over the past several decades has led to the proliferation of information technology, with transformative impact on society. Key to this rapid growth has been transistor miniaturization (“scaling”), which enables ever higher levels of integration on a silicon chip following Moore’s Law, to provide for improved integrated circuit (IC) performance and functionality per unit area. As the incremental benefits of classic (Dennard) scaling diminished due to fundamental limits for transistor operation, the industry resorted to the incorporation of the semiconductor alloy silicon-germanium (SiGe) to steadily improve the performance of complementary metal-oxide-semiconductor (CMOS) transistors and thereby enable Moore’s Law to be sustained. The application of doped polycrystalline SiGe as an alternative MOSFET gate material was first proposed and demonstrated in 1990; subsequently it was shown to provide for reduced gate depletion effect and reduced dopant penetration into the underlying gate dielectric layer, resulting in improved CMOS transistor performance and scalability as well as superior transistor reliability at deep-submicron gate lengths. The first report of using epitaxial SiGe in the source and drain regions of a metal-oxide-semiconductor field-effect transistor (MOSFET) to enhance p-channel transistor performance was in 1999. Intel Corporation was the first company to adopt this innovation in high-volume manufacturing, beginning at the 90 nm generation of CMOS technology (“node”) in 2004. The benefit of using a thin epitaxially grown layer of SiGe in the channel region to enhance the performance of sub-100 nm CMOS transistors was first demonstrated in 2000. Samsung Electronics was the first company to manufacture CMOS products with epitaxial SiGe as the (p-)channel material, beginning at the 32 nm node in 2011. The adoption of the three-dimensional (3-D) fin-shaped MOSFET design (“FinFET”) facilitated continued transistor miniaturization to gate lengths below 25 nm, beginning at the 22 nm node in early 2012. Further transistor evolution not only to facilitate continued scaling but also to achieve high on/off current ratio with lower operating voltage for improved energy efficiency will be necessary to sustain the rapid growth of the semiconductor industry beyond the next decade. Due to lighter carrier tunneling effective mass (which results in degraded subthreshold swing) and larger dielectric permittivity (which results in greater drain-induced barrier lowering), as well as the difficulty of growing a thick/tall layer of SiGe with low defect density on a silicon wafer (the substrate of choice for high-volume chip manufacturing), nanoscale SiGe FinFET performance superior to that of state-of-the-art Si FinFETs has proven to be elusive. To overcome this challenge, we recently proposed a novel hybrid-channel FinFET design that is compatible with a conventional FinFET manufacturing process flow. 3-D device simulations indicate that the hybrid-channel design can achieve than 20% larger on-state drive current for the same operating voltage, as compared against a Si-channel design, at sub-15 nm gate length. In this paper, hybrid-channel FinFET design optimization and sensitivity to process-induced variations will be discussed, to demonstrate that SiGe can continue to be an enabler of Moore’s Law beyond the 5 nm node. Figure 1

Improved Switching Speed of a CMOS Inverter Using Work-Function Modulation Engineering

This paper presents a detailed numerical analysis of work-function modulated cylindrical gate metal–oxide–semiconductor field-effect transistor (MOSFET)-based CMOS inverter. Introduction of work-function modulation in the control gate of dual-material cylindrical gate MOSFET exhibits significant reduction in short-channel effects (SCEs) and threshold voltage. The analytic potential-based model of this device is developed by considering 2-D Poisson’s equation in the cylindrical coordinate system. Development of the numerical model is based on certain boundary conditions to study the electrostatic behavior effectively. The results thus obtained from the analytical model are in good agreement with the model developed in the TCAD simulator. Improved drain current, reduced threshold voltage, immunity against SCEs, lower circuit delay, and high-speed switching have made this device a leader in CMOS logic family.

Effect of varying Indium concentration of InGaAs channel on device and circuit performance of nanoscale double gate heterostructure MOSFET

The detailed numerical analysis is performed to study and evaluate the impact of Indium (In) concentrations of the Indium gallium arsenide (InGaAs) channel on different device performances of InGaAs/In phosphide double gate metal–oxide–semiconductor field-effect transistor using TCAD software. The RF/analogue figures of merits under investigation are transconductance (gm ), transconductance-to-current ratio (gm/I d), cut-off frequency (fT ), maximum frequency of oscillations (f max) etc. A cascode amplifier is then designed using the device under study and its voltage transfer characteristics and differential gain are plotted to estimate the device performance in circuits. It is seen that with higher Indium content, the analogue/RF performance of the device significantly improves.

Design and Analysis of Logic Gates using GaN based Double Gate MOSFET (DG-MOS)

The double gate MOSFET, where two gates are fabricated along the length of the channel one after another. Design of logic gates is one of the most eminent application of Double Gate MOSFET. Gallium nitride (GaN) based metal-oxide semiconductor field-effect transistors (MOSFETs) are shown to be promising for digital logic applications. This paper describes the design and analysis of different types of logic gates using GaN based DG-MOSFET. The gate length (LG) is kept constant at 10.6 nm. The gate voltage varies from 0 to 1 V for the device switching from turn OFF to turn ON-state. For the device with HfO2 as gate oxide, the ON-state current (ION) and OFF-state current (IOFF) are found 8.11×10-3 and 6.38605×10-9A/μm respectively. The leakage current is low for the device with HfO2 as compared to that for the device with ZrO2. The subthreshold swing (SS) is 68.7408 mV/dec for the device with HfO2.

Radio frequency/analog and linearity performance of a junctionless double gate metal–oxide–semiconductor field-effect transistor

The analog/radio frequency (RF) and linearity performance of a junctionless double gate metal–oxide–semiconductor field-effect transistor (JL DGMOS) is investigated using the numerical TCAD device simulator. JL DGMOSs have shown great promise for high-performance digital applications due to their superior short channel effect performance and ease of fabrication. In analog and RF circuit applications, linearity testing and RF performance is a major issue that is encountered due to non-linear behavior of the devices. Therefore, in this paper, different RF/analog and linearity performance figures of merits such as transconductance, intrinsic gain, the transconductance generation factor, the cut off frequency, the maximum frequency of oscillation, the gain bandwidth product, the variable intercept point of second order, the variable intercept point of third order, inter modulation distortion, the third-order intercept point, and 1-dB compression have been presented. Moreover, the effect of gate-length downscaling on these performance parameters has been carried out. The results indicate that the down scaled JL DGMOS shows great promise to become a competitive contender for analog/mixed signal system on chip applications by demonstrating a significant improvement in its RF performance with gate-length downscaling.

Projected Performance of Sub-10 nm GaN-based Double Gate MOSFETs

GaN-based double gate metal-oxide semiconductor field-effect transistors (DG-MOSFETs) in sub-10 nm regime have been designed for the next generation logic applications. To rigorously evaluate the device performance, non-equilibrium Green’s function formalism are performed using SILVACO ATLAS. The device is turn on at gate voltage, VGS =1 V while it is going to off at VGS = 0 V. The ON-state and OFF-state drain currents are found as 12 mA/μm and ~10-8 A/μm, respectively at the drain voltage, VDS = 0.75 V. The sub-threshold slope (SS) and drain induced barrier lowering (DIBL) are ~69 mV/decade and ~43 mV/V, which are very compatible with the CMOS technology. To improve the figure of merits of the proposed device, source to gate (S-G) and gate to drain (G-D) distances are varied which is mentioned as underlap. The lengths are maintained equal for both sides of the gate. The SS and DIBL are decreased with increasing the underlap length (LUN). Though the source to drain resistance is increased for enhancing the channel length, the underlap architectures exhibit better performance due to reduced capacitive coupling between the contacts (S-G and G-D) which minimize the short channel effects. Therefore, the proposed GaN-based DG-MOSFETs as one of the excellent promising candidates to substitute currently used MOSFETs for future high speed applications.

Study of proton radiation effects among diamond and rectangular gate MOSFET layouts

This paper describes an experimental comparative study of proton ionizing radiation effects between the metal-oxide-semiconductor (MOS) Field Effect Transistors (MOSFETs) implemented with hexagonal gate shapes (diamond) and their respective counterparts designed with the classical rectangular ones, regarding the same gate areas, channel widths and geometrical ratios (W/L). The devices were manufactured by using the 350 nm bulk complementary MOS (CMOS) integrated circuits technology. The diamond MOSFET with α angles higher or equal to 90° tends to present a smaller vulnerability to the high doses ionizing radiation than those observed in the typical rectangular MOSFET counterparts.

Fabrication and characterisation of Al gate n ‐metal–oxide–semiconductor field‐effect transistor, on‐chip fabricated with silicon nitride ion‐sensitive field‐effect transistor

In the present study, temperature drift analysis of metal–oxide–semiconductor field-effect transistor (MOSFET) is carried out using silicon nitride/SiO2 as dielectric film. An n-channel depletion-mode MOSFET was fabricated with silicon nitride ion-sensitive field-effect transistor (ISFET) on the same wafer. The study presents the fabrication, simulation and characterisation of MOSFET. The gate of the ISFET is stacked with silicon nitride/SiO2 sensing membrane that was deposited using low pressure chemical vapour deposition. Output and transfer characteristics of on-chip fabricated Al gate MOSFET were obtained in order to study the fabricated ISFET behaviour to be used as pH sensor. Silicon nitride is preferred over SiO2 sensing film/dielectric (in case of MOSFET) which has better sensitivity and low drift. Process and device simulations were performed using Silvaco® TCAD tool.

Triple Material Surrounding Gate MOSFET for Suppression of SCES

Continuous downscaling of conventional MOSFETs suffers from various detrimental shortchannel effects (SCEs). A combination of novel device structures and material property improvement can overcome the SCEs in order to sustain the historical cadence of scaling. In this paper, a comprehensive analysis on the effect of downscaling in the performance of a novel gate-engineered Triple Material (TM) Surrounding Gate (SRG) Metal Oxide Semiconductor Field Effect Transistor (MOSFET) is presented. With the help of device simulator Silvaco ATLAS, the effect of variation of the radius (R) and the channel length (L g ) on the surface potential, the Electric Field and the drain current is reported in order to provide an enticement for future theoretical studies and experimental researches of the critical aspects of the gate-engineered surrounding gate MOSFET. Results indicate that a trade-off between gate length L g and channel radius R is necessary to achieve higher immunity against SCEs with a lower OFF-state leakage current to find its usage in ultra low-power applications.