Metal Oxide Semiconductor Field Effect Transistor Devices Research Articles

A Brief Review of Single-Event Burnout Failure Mechanisms and Design Tolerances of Silicon Carbide Power MOSFETs

Radiation hardening of power MOSFETs (metal oxide semiconductor field effect transistors) is of the highest priority for sustaining high-power systems in the space radiation environment. Silicon carbide (SiC)-based power electronics are being investigated as a strong alternative for high power spaceborne power electronic systems. SiC MOSFETs have been shown to be most prone to single-event burnout (SEB) from space radiation. The current knowledge of SiC MOSFET device degradation and failure mechanisms are reviewed in this paper. Additionally, the viability of radiation tolerant SiC MOSFET designs and the modeling methods of SEB phenomena are evaluated. A merit system is proposed to consider the performance of radiation tolerance and nominal electrical performance. Criteria needed for high-fidelity SEB simulations are also reviewed. This paper stands as a necessary analytical review to intercede the development of radiation-hardened power devices for space and extreme environment applications.

An investigation into the short-circuit characteristics of Sic MOSFET power devices

Silicon carbide (SiC) metal-oxide-semiconductor field-effect transistor (MOSFET) devices exhibit substantial prospects for application under extreme operational conditions, including elevated temperatures, high voltages, and high frequencies. Nevertheless, owing to their distinctive material and structural attributes, SiC MOSFET devices are not devoid of challenges, with the short-circuit phenomenon constituting a pivotal avenue of inquiry. The short-circuit effect pertains to the abrupt escalation of leakage current that these devices might undergo under elevated voltage conditions, thereby exerting a perturbing influence on their stability and reliability. Investigations into the short-circuit effect predominantly revolve around two dimensions: one involves comprehending its underlying physical mechanisms, while the other centers on identifying commensurate remedial approaches.With respect to the underlying physical mechanisms, researchers have discerned that the elevated breakdown field strength and augmented carrier mobility intrinsic to SiC materials engender an augmentation in leakage current, consequently giving rise to the short-circuit effect. Furthermore, factors such as oxide layer anomalies and surface states are also conceivable catalysts for the surge in leakage current. To rectify this predicament, scholars have proffered a panoply of stratagems, encompassing the optimization of material synthesis processes, enhancement of oxide layer quality, refinement of device structural designs, and incorporation of protective circuitry, among others. In summation, the investigation of the short-circuit effect in silicon carbide MOSFET devices is fundamentally aimed at attaining an in-depth comprehension of its causative mechanisms. Moreover, it endeavors to proffer efficacious resolutions conducive to augmenting the reliability and steadfastness of these devices within high-temperature and high-voltage environments, thereby facilitating their widespread integration within the ambit of high-performance power electronics.

Synaptic Characteristics of Fully Depleted Silicon‐on‐Insulator Metal‐Oxide‐Semiconductor Field‐Effect Transistors and Synapse‐Neuron Arrayed Neuromorphic Hardware System

A fully depleted silicon‐on‐insulator (FDSOI) metal‐oxide‐semiconductor field‐effect transistors (MOSFETs) device is investigated as for an electronic synapse emulating the synaptic functions of the human brain with stable characteristics. Gate‐last processed FDSOI MOSFET with a high‐k/metal gate stack features a memory window of 103. Synaptic conductance is stably regulated by utilizing the FDSOI MOSFET, which offers the advantage of mitigating leakage current when compared to bulk Si MOSFET. Short‐ and long‐term plasticity are investigated by applying engineered pulse, verifying the long‐term synaptic properties of pattern recognition processes. With controllable synaptic conductance, the trade‐off between conductance change and linearity regarding the recognition rate is evaluated, attaining a recognition rate of 0.83. To verify the pre‐ and post‐synaptic weights within a real hardware‐based neuromorphic system, 5 × 6 FDSOI field‐effect transistor (FET) synapse array is interconnected to 10 × 10 leaky integrate‐and‐fire (LIF) neuron array. The synaptic plasticity of FDSOI MOSFET in post‐neurons following neuron firing in the neuron device is successfully demonstrated. These results indicate that FDSOI MOSFET devices could be applicable as synapse devices due to controllability and capability to realize signal transmissions and self‐learning processes simultaneously and used to mimic a synapse neuron network system by configuring a hardware system interconnected with the LIF neuron.

Modeling of non-intrinsic noise in nanometer metal oxide semiconductor field effect transistors

With the proportional reduction of metal–oxide–semiconductor field effect transistor (MOSFET) devices, the short channel effect, the parasitic effect, and the field strength effect are significantly enhanced, the proportion of parasitic resistance increases, and the non-intrinsic noise also increases, which seriously affects the working efficiency of the device. However, existing research mainly focuses on the intrinsic noise of MOSFET, and there is little research on the non-intrinsic noise; furthermore, the models describing the relationship between non-intrinsic noise, device structure, and bias have not yet been addressed. Therefore, in this paper, 90, 65, 32, 10, and 5 nm MOSFETs are studied. The rate of the intrinsic ballistic parameter is introduced to set up the source–drain current model and the non-intrinsic noise model. The source–drain current model is consistent with the theoretical model, numerical simulation, and experimental results in the literature. Finally, the relationship between the non-intrinsic noise and the bias and the device parameters are analyzed, and the conclusion is helpful to improve the working efficiency, lifetime, and response speed of nanoscale MOSFET devices.

A Two-Dimensional Computer-Aided Design Study of Unclamped Inductive Switching in an Improved 4H-SiC VDMOSFET.

Due to its high thermal conductivity, high critical breakdown electric field, and high power, the silicon carbide (SiC) metal-oxide-semiconductor field-effect transistor (MOSFET) has been generally used in industry. In industrial applications, a common reliability problem in SiC MOSFET is avalanche failure. For applications in an avalanche environment, an improved, vertical, double-diffused MOSFET (VDMOSFET) device has been proposed. In this article, an unclamped inductive switching (UIS) test circuit has been built using the Mixed-Mode simulator in the TCAD simulation software, and the simulation results for UIS are introduced for a proposed SiC-power VDMOSFET by using Sentaurus TCAD simulation software. The simulation results imply that the improved VDMOSFET has realized a better UIS performance compared with the conventional VDMOSFET with a buffer layer (B-VDMOSFET) in the same conditions. Meanwhile, at room temperature, the modified VDMOSFET has a smaller on-resistance (Ron,sp) than B-VDMOSFET. This study can provide a reference for SiC VDMOSFET in scenarios which have high avalanche reliability requirements.

Engineering DyCrO3 ceramics toward room-temperature high-κ dielectric applications

The search for a high-κ dielectric material that combines a high dielectric constant (ϵ′) and low dielectric loss is very crucial because of its widespread use in gate dielectrics to avoid the leakage current that arises due to continued miniaturization of present SiO2-based metal-oxide semiconductor field-effect transistor devices. RCrO3 (R is a rare-earth ion) materials have been at the center of interest because of their intriguing ferroelectric and magnetic properties, as well as their room-temperature colossal dielectric constant (CDC) values. Although CDC (ϵ′∼104) in RCrO3 materials is quite common, it is unsuitable for device applications since it is associated with a larger dielectric loss value (tan δ∼7 at 11 kHz). Here we have focused on polycrystalline DyCrO3, prepared using multiple synthesis techniques, and thoroughly investigated the origin and tuning of the various dielectric relaxations that give rise to CDC and large dielectric loss values. A clear understanding of the origin of dielectric relaxations enables us to design a specially synthesized DyCrO3 (SPS-DCO) in which the extrinsic dielectric relaxations driven large dielectric loss values can be completely suppressed and which is found to be associated with optimized high-κ dielectric properties [ϵ′∼130, tan δ∼0.06, and temperature coefficient of dielectric constant (TCϵ) ∼ 2280 ppm/K at 11 kHz, 300 K]. The only remaining intrinsic Debye-type dielectric relaxation in SPS-DCO arises due to electric-field-assisted charge hopping among various valences of Cr (investigated using x-ray photoelectron spectroscopy) that presently limits the lowest attainable loss value.

Controlling Electron Mobility of Strongly Coupled Organic Semiconductors in Mirrorless Cavities

AbstractRecent experiments on the strong light‐matter coupling between an organic semiconductor and a plasmonic mode propose an unconventional way to enhance conductivity. Herein, it is shown that mirrorless cavities can boost conductivity by simply structuring the refractive indices of the multilayers in a commercially available metal oxide semiconductor field effect transistor (MOSFET). Perylene diimide (an organic semiconductor dye) molecules are deposited on a MOSFET device. The refractive index mismatch between the silicon/silicon dioxide/dye/air results in light confinement. The frequency of this confined light is tuned by changing the thickness of the organic semiconductor layer. Interestingly, an increase in electron mobility was observed once the electronic transition of the dye molecules and the second‐order cavity mode enter into the strong coupling regime. Whereas resonance tuning to the first‐order mode does not affect the electron transport. Here, the system is still in a weak coupling regime. These results are further correlated by experimental dispersion measurements and supported with transfer matrix simulations. The increase in electron mobility is not large due to high dissipation or low‐quality factors of the cavity modes. However, the mirrorless configuration presented here may offer a simpler way of boosting the properties of functional materials.

New Methodology for the Design of Nanostructured Integrated Circuits

Background: A metal oxide semiconductor field effect transistor (MOSFET) is widely used to make integrated circuits (ICs). MOSFET devices are reaching the practical limitations for further scaling in the nanoscale regime. It motivates the researchers to explore and develop new ways to advance the electronics industry. Quantum-dot cellular automata (QCA) is a potential way to replace the MOSFET devices in the nanoscale regime. QCA nanotechnology not only solves the issue of scalability but also degrades the leakage current. It has numerous benefits, such as a highly dense design, fast speed, and energy efficiency compared to complementary metal-oxide-semiconductor (CMOS) technology. Objective: An extensive study of QCA nanotechnology is needed to quickly understand the field. Optimizing the QCA designs is the mandatory requirement to minimize the occupied cell area, latency and quantum cost. The preliminary knowledge of QCA nanotechnology boosts the idea of generating different logic functions. This review paper presents the methodology for making the fundamental logic gates using QCA nanotechnology. XOR gate is commonly used to implement popular circuits such as adders, subtractors, comparators, code converters, reversible gates etc. The various available QCA-based 2-input XOR gate designs are discussed and compared for the different performance metrics. Methods: Columbic interaction causes logical operations, and data is transferred from one cell to another cell using cell-to-cell interaction. A specific arrangement of QCA cells produces a specific logic. QCA Designer tool using a Bi-stable simulation engine is used to design different digital circuits. Results: This review paper deals with the design of the 2-input XOR gate. The considered performance metrics for the comparison purpose are cell count, occupied area, clock cycle, and quantum cost. Existing works on 2-input XOR gates show that a minimum of 8 QCA cells are needed for a 2-input XOR gate using QCA nanotechnology. A single clock cycle-based 2-input XOR gate requires at least 9 QCA cells. The quantum cost can be minimized by reducing the number of QCA cells and clock cycles. Conclusion: This review paper helps the circuit designers to select the appropriate 2-input XOR gate for the design of complex circuits. Circuit designers can use the fundamental concepts detailed in the paper to implement any Boolean function and optimize it for the existing designs. A researcher had developed a 2-input XOR gate using only 8 QCA cells with 0.50 clock cycles. Therefore, designers can start from here to further optimize the 2-input XOR gate with a single clock cycle.

Sound isolation via temporal modulation material based on piezoelectric elements

The temporal modulation material is investigated to be used as lightweight sound isolation material. This smart composite material consists of a lightweight structure attached with shunted piezoelectric ceramic (PZT) patches. The shunt circuits are connected to the two poles of PZT patches to act as some local electrical resonators to improve the sound isolation. The circuit is composed of operational amplifiers and passive analog circuit elements, so the system is always stable, and the power consumption is low. The metal-oxide-semiconductor field-effect-transistor (MOSFET) is added in the shunt circuit connected to the PZT patches, so the time sequence of the working circuit is controlled with the MOSFET devices in each resonant shunt. The motivation of this study is to improve the sound isolation in the low-to-middle frequency range. The temporal modulation material proposed in this study has many potential applications in environmental acoustics, precise instrument, automotive sector, and aerospace technologies.

Simulation of heavy ion irradiation effect on 3D MOSFET

Single event upset effect is an important factor that causes performance degradation and functional failure of aerospace equipment components in space radiation environment. When high-energy particles incident on semiconductor devices in working state, they will induce functional errors of devices and even cause permanent damage. Based on the finite element method, the three-dimensional simulation of Metal-oxide-semiconductor field-effect transistor (MOSFET) is carried out. The single event upset effect of MOSFET under heavy ion irradiation and the influence of heavy ion irradiation on transient drain current are investigated. The results show that the transient drain current of MOSFET devices will increase rapidly when heavy ions are incident, and then the logic state of the devices will change. With the increase in linear energy transfer density, the peak value of the transient drain current pulse increases and the pulse width decreases. With the increase in the incident angle, the peak value of the pulse first increases and then decreases. The maximum value is obtained when the incident angle is vertical, the pulse width first decreases and then increases, and the minimum value is obtained when the incident angle is vertical. With the increase in MOSFET size, the difference of transient drain current formed by symmetrical heavy ion incidence is becoming smaller and smaller. When the incident track is completely in the drain region, the simulation results are the same.

Analysis of thermal noise characteristics in 10 nm metal oxide semiconductor field effect transistor

<sec>Small size metal-oxide-semiconductor field effect transistor (MOSFET), owing to their high theoretical efficiency and low production cost, have received much attention and are at the frontier of transistors. At present, their development is bottlenecked by physical limits due to equal scaling down of devices, which requires further improvement in terms of materials choice and device fabrication. As the MOSFET devices scale down to nanometer scale, on the one hand, the resulting short channel effect affects severely the thermal noise property; on the other hand, it makes the ratio of thermal noise in the gate, source, drain and substrate regions become higher and higher. However, the traditional thermal noise model mainly considers thermal noise of large-size devices, and its model does not consider the channel saturation region. In view of this, it is necessary to establish a small size MOSFET thermal noise model and analyze its characteristics.</sec><sec>At present, there are some researches on MOSFET thermal noise, but they mainly focus on the thermal noise in channel region of large size nanoscale MOSFET. In the present work, according to the device structure and inherent thermal noise characteristics, we establish a thermal noise model for MOSFETs of 10 nm feature size. The model includes contributions of substrate region, gate-source-drain region, and channel region. In the channel region is also included the thermal noise related to the device saturation regime. Using such a model, the dependence of channel thermal noise and total thermal noise on the device bias condition and device parameters are investigated, evidencing the existence of thermal noise in the device saturation regime, which are consistent with the experimental results in the literature. The thermal noise increases with the gate voltage and source-drain voltage rising as the device structure shrinks. In a temperature range of 100–400 K, the thermal noise is basically on the order of 10<sup>21</sup>, indicating that the temperature has a great influence on the thermal noise. The thermal noise model established in this work can be applied to analyzing the noise performances of small size MOSFET devices, and the conclusions drawn from the present study are beneficial to improving the efficiency, lifetime, and response speed of MOSFETs on a nanometer scale.</sec>

Recent Advances in Short Circuit Protection Methods for SiC MOSFET

Due to its high efficiency, low switching losses, and high temperature stability, Silicon Carbide (SiC) Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET) has been widely used in various fields. Therefore, the protection of SIC MOSFET devices is crucial. The significance of this research topic lies in comparing the existing short-circuit protection methods and technologies for SiC MOSFET, pointing out the advantages and shortcomings of each method, and providing suggestions. Firstly, the principles and impacts of HSF and FUL in short-circuit faults are introduced. Secondly, this article elaborates on shortcircuit protection methods from two aspects: hardware protection and software protection, concentrating mostly on recently researched hardware protection methods. Finally, a comparison between the two protection methods is made, and potential improvement solutions are proposed. Based on the research conducted, the author believes that the current hardware protection method based on current detection is the optimal solution for SiC MOSFET short-circuit protection. Future research can be focused on integrating other solutions for further optimization on this basis.

Research of Single-Event Burnout in 1.2-kV Rated CoolSiC Trench MOSFET

This paper presents the two-dimensional (2-D) numerical simulation results of heavy-ion induced reverse drain current degradation and single-event burnout (SEB) in the 1.2-kV rated CoolSiC Trench metal-oxide-semiconductor field-effect transistor (MOSFET). The physics models employed in simulations and critical failure conditions were validated by the heavy-ion irradiation experiments of the commercially available 1.2-kV rated SiC planar-gate MOSFET devices. The CoolSiC Trench MOSFET was proven to behave comparative SEB performance compared with the SiC planar-gate MOSFET. The robustness of the CoolSiC Trench MOSFET with different single buffer layer (SBL) designs against a heavy ion was simulated. Furthermore, the SBL-CoolSiC Trench MOSFET with low carrier lifetime control was investigated. According to the simulation results, the severe degeneration failure tolerance increased to 800 V; the SEB failure tolerance could reach 900 V.

Electrical characteristics of normally off hydrogen-terminated diamond field effect transistors with lanthanum oxide gate dielectric

A normally off hydrogen-terminated diamond (H-diamond) metal-oxide-semiconductor field effect transistor (MOSFET) is realized by using lanthanum oxide (La2O3) gate dielectric. The threshold voltage is demonstrated to be −0.797 V, indicating that the La2O3-gated H-diamond MOSFET has normally off characteristics. The normally off mode could be greatly ascribed to the low work function of La2O3. Based on the capacitance–voltage (C–V) curves, the dielectric constant of La2O3 is calculated to be as high as 25.6. Moreover, the small hysteresis voltage extracted from the C–V curves exhibits low trapped charge density in the La2O3 layer. The maximum drain–source current, maximum transconductance, subthreshold swing, effective mobility, current on/off ratio, and sheet hole density of La2O3-gated MOSFET with a gate length of 2 μm are calculated to be −13.55 mA/mm, 4.37 mS/mm, 161 mV/dec, 202.2 cm2/V·s, 108, and 6.53 × 1012 cm−2, respectively. This work will significantly promote the development of normally off H-diamond MOSFET devices.

Failure quantitative assessment approach to MOSFET power device by detecting parasitic parameters

With the emerging wide bandgap (WBG) semiconductor development, the increasing power density and efficiency of power electronic converters may cause more switching oscillation, electromagnetic interference noise, and additional power loss, further increasing the probability of device failure. Therefore, determining and quantifying the failure of a metal-oxide-semiconductor-field-effect transistor (MOSFET), which assembled using WBG semiconductor in some applications, is crucial to improving the reliability of a power converter. This study proposes a novel failure quantitative assessment approach based on MOSFET parasitic parameters. According to the two-port network theory, MOSFET is equivalent to some second-order RLC circuits composed of independent inductances, capacitances, and resistances in series. Then, the frequency-domain impedance associated with the physical failure of MOSFET is identified through frequency domain reflectometry. Accelerated aging and bond wires cut-off experiments are employed to obtain various quality states of the MOSFET device. Result shows that the MOSFET quality level and its number of bond wire lift-offs can be quantified effectively. Drain-to-source on-resistance (RDS(on)) that normally represents the MOSFET quality shows a positive linear function relationship on drain-to-source parasitic resistance (RD + RS) during the quality degradation proceeding. This finding matches with the correlation established between RDS (on) and RD + RS in theory. Meanwhile, source parasitic inductance (LS) increases with the severity of bond wires faults, and even the slight fault shows a high sensitivity. The proposed approach would be an effective quality screening technology for power semiconductor devices without power on treatment, which can effectively avoid the impact of junction temperature and test conditions (current and voltage) on test results, and does not need to design additional test circuits. The test frequency range we used in this approach was 10–300 MHz, which to some extent is suitable for providing an on-line quality monitoring technology for high-frequency WBG power devices manufacturing.

An Online Junction Temperature Monitoring Correction Method for SiC MOSFETs at Different Parasitic Parameters

Due to the remarkable performance of silicon carbide (SiC) metal–oxide–semiconductor field-effect transistor (MOSFET) on high temperature, it is promising in future applications in various applications. The accurate online junction temperature based on dynamic temperature-sensitive electrical parameters (TSEPs) is significant for the protection and condition monitoring, which can prolong or monitor the lifetime of SiC MOSFET devices. In this article, four different dynamic TSEPs, including turn-on delay time, turn-off delay time, and maximum current turn-on and turn-off switching rates, are theoretically analyzed taking the parasitic parameters into consideration. The experimental analysis of the influence of parasitic parameters ’ dynamic TSEPs is carried on using a buck converter test setup. Based on the theoretical and experimental analyses, a junction temperature correction method is proposed for SiC MOSFET. The online junction temperature monitoring experiments are used to verify the accuracy and effectiveness of the proposed method. The results show that the proposed correction method can largely eliminate the junction temperature monitoring error at different parasitic parameters. The maximum measurement error is reduced from 147 °C to 4.7 °C after correction.

Cryogenic Performances Comparisons Among Si MOSFET, SiC MOSFET, Cascode GaN, and GaN Devices

Cryogenic power electronics is an emerging technology to achieve high efficiency and high power density. As the key element of the power electronics system, the device performance should be evaluated under cryogenic temperatures. To demonstrate the differences between different materials and technologies, cryogenic temperature performance comparisons among silicon (Si) metal–oxide–semiconductor field-effect transistor (MOSFET), Si insulated-gate bipolar transistor (IGBT), silicon carbide (SiC) MOSFET, Cascode gallium nitride (GaN), and GaN high-electron-mobility transistor (HEMT) from different perspectives are made, which includes on-state resistance, threshold voltage, turn-on and turn-off times, turn-on and turn-off switching losses. The normalized values are adopted and results are drawn in the same pictures to demonstrate the differences. The results demonstrate that traditional Si devices have better performances under low temperatures. The SiC MOSFET is not suitable for cryogenic applications due to its increased on-state resistance and switching loss. Cascode GaN and GaN HEMT are promising candidates for cryogenic applications with reduced conduction loss and switching loss.

A novel approach for designing of variability aware low‐power logic gates

Metal-oxide-semiconductor field-effect transistors (MOSFETs) are continuously scaling down in the nanoscale region to improve the functionality of integrated circuits. The scaling down of MOSFET devices causes short-channel effects in the nanoscale region. In nanoscale region, leakage current components are increasing, resulting in substantial power dissipation. Very large-scale integration designers are constantly exploring different effective methods of mitigating the power dissipation. In this study, a transistor-level input-controlled stacking (ICS) approach is proposed for minimizing significant power dissipation. A low-power ICS approach is extensively discussed to verify its importance in low-power applications. Circuit reliability is monitored for process and voltage and temperature variations. The ICS approach is designed and simulated using Cadence's tools and compared with existing low-power and high-speed techniques at a 22-nm technology node. The ICS approach decreases power dissipation by 84.95% at a cost of 5.89 times increase in propagation delay, and improves energy dissipation reliability by 82.54% compared with conventional circuit for a ring oscillator comprising 5-inverters.

Enhancement-Mode Heterojunction Vertical β-Ga2O3 MOSFET with a P-Type Oxide Current-Blocking Layer

The vertical heterojunction Ga2O3 MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) with the p-type oxide as the current-blocking layer (CBL) is investigated for the first time using SILVACO simulation software. The results show that the threshold voltage of the device is easily positive, which means that the device works in the enhancement mode. By adjusting the doping concentration (from 2 × 1017 cm−3 to 2 × 1018 cm−3) and thickness (from 0.4 um to 2 um) of p-SnO CBL, the threshold voltage is around from 2.4 V to 2.8 V and the breakdown voltage of the device can be increased from 361 V to 518 V. Compared with the original homojunction Ga2O3 vertical MOSFET with CBL, the p-SnO CBL can greatly improve the performance of the device. Other p-type oxides are also investigated as the CBL and show promising performances. This work has a certain guiding significance for the design of a vertical enhanced current-blocking layer MOSFET device and for the development of a Ga2O3 heterojunction power device.

Study on a novel vertical enhancement-mode Ga 2 O 3 MOSFET with FINFET structure

A novel enhanced mode (E-mode) Ga2O3 metal–oxide–semiconductor field-effect transistor (MOSFET) with vertical FINFET structure is proposed and the characteristics of that device are numerically investigated. It is found that the concentration of the source region and the width coupled with the height of the channel mainly effect the on-state characteristics. The metal material of the gate, the oxide material, the oxide thickness, and the epitaxial layer concentration strongly affect the threshold voltage and the output currents. Enabling an E-mode MOSFET device requires a large work function gate metal and an oxide with large dielectric constant. When the output current density of the device increases, the source concentration, the thickness of the epitaxial layer, and the total width of the device need to be expanded. The threshold voltage decreases with the increase of the width of the channel area under the same gate voltage. It is indicated that a set of optimal parameters of a practical vertical enhancement-mode Ga2O3 MOSFET requires the epitaxial layer concentration, the channel height of the device, the thickness of the source region, and the oxide thickness of the device should be less than 5 × 1016 cm−3, less than 1.5 μm, between 0.1 μm − − 0.3 μm and less than 0.08 μm, respectively.