Metal Oxide Semiconductor Devices Research Articles

Interface States in Gate Stack of Carbon Nanotube Array Transistors.

A deep understanding of the interface states in metal-oxide-semiconductor (MOS) structures is the premise of improving the gate stack quality, which sets the foundation for building field-effect transistors (FETs) with high performance and high reliability. Although MOSFETs built on aligned semiconducting carbon nanotube (A-CNT) arrays have been considered ideal energy-efficient successors to commercial silicon (Si) transistors, research on the interface states of A-CNT MOS devices, let alone their optimization, is lacking. Here, we fabricate MOS capacitors based on an A-CNT array with a well-designed layout and accurately measure the capacitance-voltage and conductance-voltage (C-V and G-V) data. Then, the gate electrostatics and the physical origins of interface states are systematically analyzed and revealed. In particular, targeted improvement of gate dielectric growth in the A-CNT MOS device contributes to suppressing the interface state density (Dit) to 6.1 × 1011 cm-2 eV-1, which is a record for CNT- or low-dimensional semiconductors-based MOSFETs, boosting a record transconductance (gm) of 2.42 mS/μm and an on-off ratio of 105. Further decreasing Dit below 1 × 1011 cm-2 eV-1 is necessary for A-CNT MOSFETs to achieve the expected high energy efficiency.

Tuning of interface quality of Al/CeO2/Si device by post-annealing of sol-gel grown high-k CeO2 layers

A comprehensive study has been done on the influence of post-deposition annealing temperature on high-k cerium oxide (CeO2) layer grown on n-type silicon (Si) substrate and its resultant interface states have been studied for Al/CeO2/Si metal-oxide-semiconductor (MOS) devices. The high-k CeO2 thin films were deposited by spin-coating and sintered at different annealing temperatures (Ta) in the range of 400–900 °C. The parameters such as fixed charge density (Qeff), dielectric constant (k) of the layers, flat-band voltage (VFB), interface defect density (Dit), etc., of the MOS device were evaluated from CV and I-V measurements. A minimum value of flat band shift (∼0.05 V) with lower Qeff (−4.81 × 1011 C/cm2) have been achieved for the Ta of 600 °C. The k and Dit were evaluated to be 22 and 1.29 × 1012 cm−2, respectively at the Ta of 600 °C. In addition, the CV measurements showed a very small hysteresis and very low frequency dispersion for the Ta of 600 °C sample. Energy distribution of defect states was evaluated and it was maximum towards the bottom of the conduction band. This shows that the 600 °C is the optimum annealing temperature, which results in high quality interface, and the electron affinity of the corresponding CeO2 layers was found to be 3.29 eV as evaluated from ultraviolet photoelectron spectroscopy (UPS). Further, a maximum value of minority carrier lifetime (147 μs) has been achieved for the samples annealed at Ta of 400 °C, indicating that the post-annealing temperature plays a significant role on the properties of CeO2 films deposited by sol-gel process. Thus, the present study demonstrates the possibility of sol-gel grown high k-CeO2 layers suitable for MOS like devices.

Spin coating high‐k multicomponent (Al,Ti,V,Zr,Hf)Ox films with sub‐nm EOT for MOS‐based electronic devices

AbstractThe facile spin coating fabrication of high‐dielectric‐constant (high‐k) multicomponent (Al,Ti,V,Zr,Hf)Ox films with an equivalent oxide thickness of ≈0.95 nm and the investigation of their thermal stability and dielectric and electrical properties of the resulting advanced metal–oxide–semiconductor (MOS)‐based electronic devices are reported in this study. Various heating conditions, including drying following spin coating, annealing after drying, and forming gas annealing, were investigated to optimize the quality of the films and reduce film defects. The favorable film‐based MOS devices exhibited robust capacitance–voltage (C–V) and current–voltage (I–V) characteristics with a remarkable k value of approximately 62 at 1 kHz. The thermal stability of the films was affirmed through a rapid thermal annealing treatment at 900°C for 5 s and observation of nondegraded C–V and I–V curves. The electrical performance of the resulting MOS field‐effect transistors (MOSFETs), including a threshold voltage of 0.4 V, an on/off ratio of 106, a saturated mobility of 40.1 cm2 V−1 s−1, and a subthreshold swing of 66.7 mV dec−1, was obtained. Moreover, hole‐ and electron‐trapping measurements through negative and positive gate bias stress instabilities, respectively, indicate the reliable performance of our MOSFETs. Our results imply that solution‐based processes are promising for fabricating fundamental semiconductor devices.

Hydrogen-like impurities in Si and Ge quantum dots in connection with 5 nm and beyond metal-oxide-semiconductor technologies

The industrial drive towards smaller semiconductor devices is at less than 10 nano-meters. In the next few years a three-dimensional quantum confined device structure is expected. We have studied the electronic structure of hydrogen-like donor impurities in Si and Ge quantum dots with varied shape of the confinement potential. These calculations are carried out within the Density-Functional-Effective-Mass Theory (DF-EMT). We have paid particular attention to the electron-electron interaction energy in a negative charge state of the donor impurity. The effect of electron correlation on the binding energy has been explored. In addition to these, we show that the second order correction to the ground state energy obtained through perturbative approach agrees well with the DF-EMT based numerical results, down to very small sizes of the quantum dots when the depth of the confinement is moderate or small. A non-monotonic shallow-deep transition of the binding energy of neutral and charged donors of hydrogen-like impurities is expected to occur with the reduction in the size of the quantum dot. A similar effect is expected for hydrogen-like acceptor impurities as well. Furthermore, the optical gap also shows non-monotonic shallow-deep behaviour with the quantum dot size reduction. Deepening of shallow donor or acceptor level implies that the carriers will freeze out at small sizes of the dot. We believe this is quite important in the context of metal-oxide-semiconductor (MOS) devices beyond 5 nm technologies, based on Si, Ge or a combination (SiGe). We also point out possible variabilities in the binding energy of donors and acceptors if there are variations in the size of host quantum dots in a large assembly of devices in future integrated circuits. This will lead to the variabilities in the characteristics from device to device. These results should be incorporated in the Technology Computer Aided Design (TCAD) simulation of less than or equal to 5 nm MOS devices.

CMOS Compatible Hydrogen Sensor Using Platinum Gate and ALD-Aluminum Oxide.

In this study, a p-Si/ALD-Al2O3/Ti/Pt MOS (metal oxide semiconductor) device has been fabricated and used as a hydrogen sensor. The use of such a stack enables a reliable, industry-compatible CMOS fabrication process. ALD-Al2O3 has been chosen as it can be integrated into the back end of the line (BEOL) or in CMOS, post processing. The device response and recovery are demonstrated with good correlation between the capacitance variation and the hydrogen concentration. Detection down to 20 ppm at 140 °C was obtained and a response time of 56 s for 500 ppm was recorded.

NBTI Effect Survey for Low Power Systems in Ultra-Nanoregime

Background: Electronic device scaling with the advancement of technology nodes maintains the performance of the logic circuits with area benefit. Metal oxide semiconductor (MOS) devices are the fundamental blocks for building logic circuits. Area minimization with higher efficiency of the circuits motivates the researchers of very large-scale integration (VLSI) design. Moreover, the reliability of digital circuits is one of the biggest challenges in VLSI technology. A major issue in reliability is negative bias temperature instability (NBTI) degradation. NBTI affects the efficiency and reliability of electronic devices Methods: This paper presents a review of NBTI physical-based mechanisms. NBTI's impact on VLSI circuits and techniques has been studied to mitigate and compensate for the effect of NBTI. Results: This review paper presents an idea to relate the NBTI and leakage mitigation techniques. This study gives an overview of the efficiency, complexity, and overhead of NBTI mitigation techniques and methodologies. Conclusion: This survey provides a brief idea about NBTI degradation by using reliability simulation. Moreover, the extensive aging effect is discussed in the paper.

Performance improvements in complementary metal oxide semiconductor devices and circuits based on fin field-effect transistors using 3-nm ferroelectric Hf0.5Zr0.5O2

In this work, a conventional HfO2 gate dielectric layer is replaced with a 3-nm ferroelectric (Fe) HZO layer in the gate stacks of advanced fin field-effect transistors (FinFETs). Fe-induced characteristics, e.g., negative drain induced barrier lowering (N-DIBL) and negative differential resistance (NDR), are clearly observed for both p- and n-type HZO-based FinFETs. These characteristics are attributed to the enhanced ferroelectricity of the 3-nm hafnium zirconium oxide (HZO) film, caused by Al doping from the TiAlC capping layer. This mechanism is verified for capacitors with structures similar to the FinFETs. Owing to the enhanced ferroelectricity and N-DIBL phenomenon, the drain current (IDS) of the HZO-FinFETs is greater than that of HfO2-FinFETs and obtained at a lower operating voltage. Accordingly, circuits based on HZO-FinFET achieve higher performance than those based on HfO2-FinFET at a low voltage drain (VDD), which indicates the application feasibility of the HZO-FinFETs in the ultra-low power integrated circuits.Graphical abstract

Design of power efficient and reliable hybrid inverter approach based 11 T SRAM design using GNRFET technology

Designing a power efficient and high-speed static random-access memory (SRAM) cell with improved noise stability using traditional complementary metal oxide semiconductor (CMOS) devices is an arduous task. Owing to balanced electrical properties of graphene nanoribbon field-effect transistor (GNRFET), its capability to realize high performance SRAM cells need a keen exploration. This article proposes an 11-transistor GNRFET SRAM cell which deploys hybrid inverter scheme. The hybrid inverter scheme encompasses two distinct inverters, based on stacked transistors and Schmitt trigger (ST) techniques. The simulations conducted using 16 nm GNRFET model in HSPICE simulator show that proposed SRAM cell has write power, hold power, read power, write static noise margin, hold static noise margin, read static noise margin, write delay and read delay of 0.445 nW, 0.978 µW, 1.8 nW, 225 mV, 222.8 mV, 225.1 mV, 24 pS and 49.6 pS, respectively. The results obtained for proposed SRAM cell have been found to be encouraging in contrast to previously reported SRAM cells implemented using 16 nm GNRFET model. Besides this, the effect of variation in various parameters of GNRFET on performance of proposed SRAM cell has been investigated in this article. The outstanding performance results of SRAM makes its suitable for developing high performance memories devices for biomedical digital gadgets, internet of things (IoT), artificial intelligence (AI) and smart agricultural applications.

Optimizing interface properties of HfO2/Si0.73Ge0.27 gate stacks through sulfur passivation and post-deposition annealing

This paper presents a comprehensive exploration of low interface trap density (Dit) in HfO2/Si0.73Ge0.27 metal-oxide semiconductor (MOS) capacitors achieved through sulfur passivation and post-deposition annealing (PDA). Our investigation revealed that devices subjected to sulfur passivation and PDA exhibit noteworthy reductions in Dit and hysteresis. Specifically, a low Dit value of 1.2 × 1011 eV−1 cm−2 has been achieved at Ei–0.1 eV for the SiGe MOS device. The observed enhancement in interface properties can be attributed to two key factors: the reduction of the GeOx concentration in the interfacial layer (IL) by sulfur passivation on the SiGe surface and the IL densification with stoichiometric oxygen during PDA.

The impact of sputtering pressure on the TiO2/p-Si interface and its implications for hole-blocking and photodetection

One convenient approach to minimize the surface recombination loss in Si is to passivate the surface dangling bonds by depositing a thin TiO2 layer on the bulk Si. Besides, the p-Si/TiO2 interface can initiate hole-blocking and facilitate efficient electron transport through the TiO2 layer; thereby, promoting the extraction of electrons for efficient onward utilization. In this context, the current investigation involves studying how the Ti3+ donor states, produced by deliberately introducing O-vacancies controlled by changing the plasma pressure in the RF-magnetron sputtering chamber during the growth of the TiO2 thin films, can change the material's Fermi level and work function and modify the band bending and band offset as well as the fixed oxide charge density in the p-Si/TiO2 heterojunction interface. The TiO2/p-Si interface has been studied through capacitance-voltage (C-V) analysis to determine the interface parameters such as fixed oxide charge, the density of interface traps, and the dielectric constant of TiO2. The studied hole-blocking property of the interface has been correlated to the photoresponsivity of the metal-oxide-semiconductor (MOS) structure. The MOS device fabricated at a pressure of 30 mTorr displays a large saturation current (15.95 μA cm–2) when subjected to a positive gate bias, facilitated by the relatively low conduction band offset (ΔEC ∼0.20 eV), significant positive fixed oxide charge (+1.18 ×1011 cm–2) and the interface trap density (1.03 ×1012 cm–2), which enhanced the transport of minority carrier electrons from the p-Si to the metal, resulting in a good photo responsivity ∼0.158 AW–1 and photo gain of ∼37.5 under white light illumination. Optimum hole-blocking and surface passivation characteristics of the TiO2/p-Si interface together may facilitate fabricating improved heterojunction Si solar cells.

Investigation of dual work function metal (DWFM) gate stacks with ALD TaAlN and TaAlC for multi threshold voltages (VTHs) engineering in MOS device integration

This study investigates methods to modulate the effective work function (EWF) and control the multiple threshold voltages (VTHs) of metal-oxide-semiconductor (MOS) devices by applying metal electrodes with different work function materials (WFMs), including a single layer of n-type (TaAlC) and p-type (TaAlN) as well as their stacked structures, through atomic layer deposition (ALD). Dual-Work-Function-Metal (DWFM) gate is a crucial aspect of confirming the feasibility of metal gate stacks in MOS devices for a complementary metal-oxide-semiconductor (CMOS) integration scheme. The gate stack structure of p-Si/IL (Inter layer)/HfO2/DWFM (p/n-type compatible metal stack)/W exhibits good adhesion and even chemical composition distribution, as evidenced by transmission electron microscope (TEM) and energy dispersive spectrometer (EDS) analysis. By fabricating MOS capacitors using this WFM structure and extracting EWF from the measured capacitance-voltage (C–V) characteristics, EWF values of 4.62 eV and 4.99 eV were identified both before and after annealing using forming gas, indicating pWFM-like properties. These properties are attributed to the strengthened Al–O bonds and reduced CO peaks seen in x-ray photoelectron spectroscopy (XPS) analysis. The use of different Ta precursor from Tris(diethylamido)(tert-butylimido)tantalum(V) (TBTDET) as well as TaCl5 resulted in the increase of the EWF following the unique p-WFM like feature. As candidates for WFM electrode in metal-oxide-semiconductor field effect transistor (MOSFET) with the DWFMs (n/p stacks) were evaluated, resulting in a VTH of 0.84 V that places in the middle of the VTH shift range from 0.6 V (nWFM) to 1.16 V (pWFM), approximately. The DWFMs allow for modulation of the EWF, which in turn reduces ambiguity in addressing replacement metal gate (RMG) challenges and opens up new avenues for achieving multi-VTH solutions in CMOS integration schemes.

Characterization of nitrided SiC(1 [formula omitted] 00) MOS structures by means of electrical measurements and X-ray photoelectron spectroscopy

Interface nitridation in nitric oxide is a standard technique for improving the performance of silicon carbide (SiC) metal-oxide-semiconductor (MOS) devices. In this study, we focused on m-face SiC MOS structures and investigated the impact of nitridation by means of electrical measurements and X-ray photoelectron spectroscopy (XPS). Gate leakage characteristics were measured in a wide temperature range of about −150 – 100 °C, which clarified that nitridation leads to an unwanted increase in the Fowler-Nordheim leakage current. Scanning XPS measurements revealed that the amount of nitrogen incorporated at the m-face MOS interface could reach about 2.3 times higher than the Si-face MOS interface. The incorporation of nitrogen likely reduces the conduction band offset at the SiO2/SiC interface, thereby increasing the gate leakage. This conclusion was further corroborated in an analysis of band alignment based on synchrotron radiation XPS measurements. Therefore, while nitrided m-face SiC MOS devices exhibit superior on-state performances, they have a limitation in terms of reliability.

Relaxation kinetics of interface states and bulk traps in atomic layer deposited ZrO2/β-Ga2O3 metal-oxide-semiconductor capacitors

The study of interface states and bulk traps and their connection to device instability is highly demanded to achieve reliable β-Ga2O3 metal-oxide-semiconductor (MOS) devices. However, a comprehensive analysis of the capture/emission behavior of interface states and bulk traps can be challenging due to widespread time constant distribution. In this study, using capacitance transient measurement tools, trap states of the ZrO2/β-Ga2O3 MOS gate stack were explicitly investigated, particularly its bias- and temperature-dependent relaxation kinetics. As forward bias is enlarged, it is observed that the interface state density (Dit) increases by 12.6%. Two bulk traps with discrete levels identified as 0.43 eV (E1) and 0.74 eV (E2) below the conduction band minimum were extracted by deep-level transient spectroscopy. It is further revealed that the emission processes of E1 and E2 are thermally enhanced, while the capture processes remain insensitive to temperature. The electric-field dependence of E1 indicates that the dominant mechanism follows the rule of Poole–Frenkel emission. The capacitance–voltage (C–V) hysteresis deteriorated at a higher forward bias due to the higher trap density and increased population of trapped charges. These findings provide an important framework for future device optimization to improve the reliability and performance of β-Ga2O3 MOS devices.

VO2 memristor-based frequency converter with in-situ synthesize and mix for wireless internet-of-things

Wireless internet-of-things (WIoT) with data acquisition sensors are evolving rapidly and the demand for transmission efficiency is growing rapidly. Frequency converter that synthesizes signals at different frequencies and mixes them with sensor datastreams is a key component for efficient wireless transmission. However, existing frequency converters employ separate synthesize and mix circuits with complex digital and analog circuits using complementary metal-oxide semiconductor (CMOS) devices, naturally incurring excessive latency and energy consumption. Here we report a highly uniform and calibratable VO2 memristor oscillator, based on which we build memristor-based frequency converter using 8×\\documentclass[12pt]{minimal} \\usepackage{amsmath} \\usepackage{wasysym} \\usepackage{amsfonts} \\usepackage{amssymb} \\usepackage{amsbsy} \\usepackage{mathrsfs} \\usepackage{upgreek} \\setlength{\\oddsidemargin}{-69pt} \\begin{document}$$\ imes$$\\end{document}8 VO2 array that can realize in-situ frequency synthesize and mix with help of compact periphery circuits. We investigate the self-oscillation based on negative differential resistance of VO2 memristors and the programmability with different driving currents and calibration resistances, demonstrating capabilities of such frequency converter for in-situ frequency synthesize and mix for 2 ~ 8 channels with frequencies up to 48 kHz for low frequency transmission link. When transmitting classical sensor data (acoustic, vision and spatial) in an end-to-end WIoT experimental setup, our VO2-based memristive frequency converter presents up to 1.45× ~ 1.94× power enhancement with only 0.02 ~ 0.21 dB performance degradations compared with conventional CMOS-based frequency converter. This work highlights the potential in solving frequency converter’s speed and energy efficiency problems in WIoT using high crystalline quality epitaxially grown VO2 and calibratable VO2-based oscillator array, revealing a promising direction for next-generation WIoT system design.

Broadband Tunable Infrared Light Emission from Metal-Oxide-Semiconductor Tunnel Junctions in Silicon Photonics.

Broadband near-infrared light emitting tunnel junctions are demonstrated with efficient coupling to a silicon photonic waveguide. The metal oxide semiconductor devices show long hybrid photonic-plasmonic mode propagation lengths of approximately 10 μm and thus can be integrated into an overcoupled resonant cavity with quality factor Q ≈ 49, allowing for tens of picowatt near-infrared light emission coupled directly into a waveguide. The electron inelastic tunneling transition rate and the cavity mode density are modeled, and the transverse magnetic (TM) hybrid mode excitation rate is derived. The results coincide well with polarization resolved experiments. Additionally, current-stressed devices are shown to emit unpolarized light due to radiative recombination inside the silicon electrode.

Review on remote phonon scattering in transistors with metal-oxide-semiconductor structures adopting high-k gate dielectrics

One main obstacle to obtaining high carrier mobility in transistors with metal-oxide-semiconductor (MOS) structures is carrier scattering, which has been systematically investigated. In the past few decades, much attention was preferentially paid to the scatterings arising from the region near the semiconductor/oxide interface because they can affect the carrier transport in the semiconductor channel more directly and effectively, e.g., polaronic effect, Coulomb scattering, surface-roughness scattering, and intrinsic phonon scattering resulted from the thermal vibration of the semiconductor channel. However, scattering originated from hybrid interface plasmon/optical-phonon excitations, so-called remote phonon scattering, has been neglected to some extent, but is especially severe for gate oxides with high dielectric constants due to the easy vibrations of their atoms. On the other hand, plasmons generated from the oscillations of majority carriers in the gate electrode can couple with the remote phonons to suppress the remote phonon scattering, which is called the gate screening effect. However, when the frequency of the gate-electrode plasmon is close/equal to that of the gate-dielectric phonon, the resonance between the gate electrode and the gate dielectric greatly enhances the remote phonon scattering to severely degrade the carrier mobility (so-called gate antiscreening effect). This work intends to give a comprehensive review on the origins, effects, suppression methods, and recent advances of the remote phonon scattering, with a view to achieving high-mobility MOS devices (including those based on two-dimensional semiconductors) with high-k gate dielectrics for future high-speed electronic applications.

Design of SiO2/4H–SiC MOS interfaces by sputter deposition of SiO2 followed by high-temperature CO2-post deposition annealing

Oxidation of silicon carbide (SiC) is known to induce defects at the interface of the SiO2/SiC system. NO-annealing is a standard industrial method of nitridation, but oxidation may progress during NO-nitridation, which may generate interface defects. Here, we propose a new method of fabricating SiO2/SiC metal-oxide-semiconductor (MOS) devices: sputter deposition of SiO2 in an Ar/N2 gas mixture followed by high-temperature CO2-post deposition annealing to form SiO2 and incorporate nitrogen at the interface while suppressing oxidation of the SiC. We obtained the nitrogen depth profile by performing x-ray photoelectron spectroscopy and confirmed that most of the nitrogen atoms exist at the abrupt interface. While maintaining a low interface state density and good insulating property, we demonstrated much improved reliability of MOS devices compared to conventional NO-annealed samples, thanks to the well-designed SiO2/SiC interface by the proposed method.

A Process Optimization Method of the Mini-LOCOS Field Plate Profile for Improving Electrical Characteristics of LDMOS Device

In this work, the effects of the mini-local oxidation of silicon (LOCOS) field plate’s bottom physical profile on the devices’ breakdown performance are analyzed through technology computer-aided design simulations. It is indicated that the “abrupt” bottom profile could certainly do with an optimization. This paper introduces an effective process improvement method by etching bias power adjustment and time reduction. The upgradation of the field plate physical profile has been proved by transmission electron microscope cross-section analysis. The angle for the bottom surface of mini-LOCOS field plate θ2 is improved from 11.9° to 12.6°, and the thickness ratio of Hup/Hbottom (field plate oxide thickness for the upper and bottom, respectively) is increased from 71.8% to 76.6%. Finally, the optimized laterally diffused metal oxide semiconductor devices have been fabricated, and both figure of merit curves and safe operation area curves are measured. The specific on-resistance Ron,sp could achieve as low as 11.3 mΩ mm2, while breakdown voltage BVds,max arrives at 37.4 V, which is nearly 19.3% improved.

Engineering DyCrO3 ceramics toward room-temperature high-κ dielectric applications

The search for a high-κ dielectric material that combines a high dielectric constant (ϵ′) and low dielectric loss is very crucial because of its widespread use in gate dielectrics to avoid the leakage current that arises due to continued miniaturization of present SiO2-based metal-oxide semiconductor field-effect transistor devices. RCrO3 (R is a rare-earth ion) materials have been at the center of interest because of their intriguing ferroelectric and magnetic properties, as well as their room-temperature colossal dielectric constant (CDC) values. Although CDC (ϵ′∼104) in RCrO3 materials is quite common, it is unsuitable for device applications since it is associated with a larger dielectric loss value (tan δ∼7 at 11 kHz). Here we have focused on polycrystalline DyCrO3, prepared using multiple synthesis techniques, and thoroughly investigated the origin and tuning of the various dielectric relaxations that give rise to CDC and large dielectric loss values. A clear understanding of the origin of dielectric relaxations enables us to design a specially synthesized DyCrO3 (SPS-DCO) in which the extrinsic dielectric relaxations driven large dielectric loss values can be completely suppressed and which is found to be associated with optimized high-κ dielectric properties [ϵ′∼130, tan δ∼0.06, and temperature coefficient of dielectric constant (TCϵ) ∼ 2280 ppm/K at 11 kHz, 300 K]. The only remaining intrinsic Debye-type dielectric relaxation in SPS-DCO arises due to electric-field-assisted charge hopping among various valences of Cr (investigated using x-ray photoelectron spectroscopy) that presently limits the lowest attainable loss value.

Passivation of hole traps in SiO2/GaN metal-oxide-semiconductor devices by high-density magnesium doping

A major challenge in GaN-based metal-oxide-semiconductor (MOS) devices is significant hole trapping near the oxide/GaN interface. In this study, we show that the density and energy level of the hole traps depends crucially on the concentration of magnesium (Mg) dopants in GaN layers. Although the surface potential of a conventional SiO2/p-GaN MOS device is severely pinned by hole trapping, hole accumulation and very low interface state densities below 1011 cm−2 eV−1 are demonstrated for MOS capacitors on heavily Mg-doped GaN epilayers regardless of the degree of dopant activation. These findings indicate the decisive role of Mg atoms in defect passivation.