Metal Oxide Semiconductor Circuits Research Articles

A Drosophila-inspired intelligent olfactory biomimetic sensing system for gas recognition in complex environments

The olfactory sensory system of Drosophila has several advantages, including low power consumption, high rapidity and high accuracy. Here, we present a biomimetic intelligent olfactory sensing system based on the integration of an 18-channel microelectromechanical system (MEMS) sensor array (16 gas sensors, 1 humidity sensor and 1 temperature sensor), a complementary metal‒oxide‒semiconductor (CMOS) circuit and an olfactory lightweight machine-learning algorithm inspired by Drosophila. This system is an artificial version of the biological olfactory perception system with the capabilities of environmental sensing, multi-signal processing, and odor recognition. The olfactory data are processed and reconstructed by the combination of a shallow neural network and a residual neural network, with the aim to determine the noxious gas information in challenging environments such as high humidity scenarios and partially damaged sensor units. As a result, our electronic olfactory sensing system is capable of achieving comprehensive gas recognition by qualitatively identifying 7 types of gases with an accuracy of 98.5%, reducing the number of parameters and the difficulty of calculation, and quantitatively predicting each gas of 3–5 concentration gradients with an accuracy of 93.2%; thus, these results show superiority of our system in supporting alarm systems in emergency rescue scenarios.

Flexible printed three dimensional (3D) integrated carbon nanotube complementary metal oxide semiconductor (CMOS) thin film transistors and circuits

Flexible printed three dimensional (3D) integrated carbon nanotube complementary metal oxide semiconductor (CMOS) thin film transistors and circuits

Dynamic Power Saving for CMOS Circuits

With more functionalities being integrated into a microchip today, higher processing power is drawn. As a result of this, clock and logic power consumption has turned out to be a critical issue to be coped with by chip designers. In this paper, we present various power-saving approaches employed in complementary metal oxide semiconductor (CMOS) circuit designs. The approaches involve restructuring the logic circuits, performing clock gating, and selecting the appropriate circuits for counters and frequency divisions. In order to show their efficacies in power optimization, the approaches were applied to a phase-locked loop (PLL), clock divider (CD), full adder (FA), counter, arithmetic logic unit (ALU), and microprocessor without interlocked pipelined stages (MIPS) circuits and validated using Intel Quartus Prime Lite and Mentor Graphics Modelsim. The following conclusions can be drawn from the results: Firstly, the efficacy of minimizing power dissipation using logic restructuring is found to be in direct proportion with the rate of the switching activity (SA); secondly, a maximum of 3.5% of thermal power dissipation can be saved using clock gating; thirdly, gray counters give the lowest power consumption; and, finally, the thermal power estimation for the phase-locked loop (PLL) is relatively higher than that for the clock divider (CD) when both of them are implemented for dividing frequencies.

Enhancement noise margin and delay time performance of novel punch-through nMOS for single-carrier CMOS

In this paper, we propose the use of punch-through nMOS (PTnMOS) as an alternative to pMOS in complementary metal oxide semiconductor (CMOS) circuits. According to the TCAD simulation results, PTnMOS exhibit sub-threshold characteristics similar to those of pMOS and can be formed by simply changing the doping concentration of the source and drain. Without the need for sizing, which solves the area occupation problem caused by the need to increase the width of pMOS due to insufficient hole mobility. In addition, we compose a PTnMOS and nMOS without sizing to form a single-carrier CMOS in which only electrons are transmitted, and We extract its performance for comparison with conventional CMOS (Wp/Wn = 1). The results indicate that single-carrier CMOS has symmetric noise margin and 29% faster delay time compared to conventional CMOS (Wp/Wn = 1). If III–V or II–VI group materials could be applied to single-carrier CMOS, not only could costs be reduced and wafer area occupancy minimized, but also significant improvements in the performance and bandwidth application of microwave circuits could be achieved.

High-performance of low temperature solution-processed P-channel CuGaO thin film transistors

The exploration of p-type metal-oxide semiconductors (MOS) has garnered growing interest, particularly for their potential applications in next-generation optoelectronic devices, display backplanes, and low-power consumption complementary MOS (CMOS) circuits. Here, we introduced low-temperature solution-processed copper gallium oxide (CuGaO) films for p-channel thin-film transistors (TFTs). Hall Effect measurements confirmed the p-type conduction of CuGaO, revealing a conductivity and mobility of 3.76 ×10−2 S/cm and 7.89 cm2V–1s–1, respectively. The p-channel CuGaO-250 TFT demonstrated a field-effect mobility (μFE) of 1.24 cm2V–1s–1, the lowest subthreshold swing (SS) of 519 mV/dec, and an ON/OFF current ratio (ION/IOFF) of ∼104 at a low operating voltage. The notable improvement in TFT performance can be attributed to the quality of the CuGaO-250 film, a smooth surface morphology, and a reduction of interfacial traps between the semiconductor and the gate insulator. Hence, low-temperature fabrication of the p-channel CuGaO TFT holds promise for implementing metal oxide-based TFT and complementary metal oxide semiconductor (CMOS) circuits in next-generation displays.

Performance improvements in complementary metal oxide semiconductor devices and circuits based on fin field-effect transistors using 3-nm ferroelectric Hf0.5Zr0.5O2

In this work, a conventional HfO2 gate dielectric layer is replaced with a 3-nm ferroelectric (Fe) HZO layer in the gate stacks of advanced fin field-effect transistors (FinFETs). Fe-induced characteristics, e.g., negative drain induced barrier lowering (N-DIBL) and negative differential resistance (NDR), are clearly observed for both p- and n-type HZO-based FinFETs. These characteristics are attributed to the enhanced ferroelectricity of the 3-nm hafnium zirconium oxide (HZO) film, caused by Al doping from the TiAlC capping layer. This mechanism is verified for capacitors with structures similar to the FinFETs. Owing to the enhanced ferroelectricity and N-DIBL phenomenon, the drain current (IDS) of the HZO-FinFETs is greater than that of HfO2-FinFETs and obtained at a lower operating voltage. Accordingly, circuits based on HZO-FinFET achieve higher performance than those based on HfO2-FinFET at a low voltage drain (VDD), which indicates the application feasibility of the HZO-FinFETs in the ultra-low power integrated circuits.Graphical abstract

Exploring Terahertz COMPLEMENTARY METAL OXIDE SEMICONDUCTOR Integrated Circuits: Advancements and Obstacles

The text provides a description of the characteristics of several NMOS and CMOS circuit approaches, as well as an explanation of the limitations associated with each technology. Next, the CMOS domino circuit, a novel form of circuit, is explained. This entails interconnecting dynamic CMOS gates in a manner that enables the activation of all gates in the circuit simultaneously using a single clock edge. Consequently, there is no need for intricate clocking methods, allowing the dynamic gate to operate at its maximum speed. This circuit features a basic mode voltage-controlled oscillator operating at 135 GHz in 80-nm COMPLEMENTARY METAL OXIDE SEMICONDUCTOR, a 405 GHz push-push voltage controller in 38-nm COMPLEMENTARY METAL OXIDE SEMICONDUCTOR with an on-chip patch antenna, a 128 GHz Schottky diode frequency doubler, a 170 GHz Schottky diode detector, a 600 GHz plasma wave detector in 122-nm COMPLEMENTARY METAL OXIDE SEMICONDUCTOR and a 40 GHz phase-locked loop with a frequency doubled output at 110 GHz. Given this and the trends in performance of n METAL OXIDE SEMICONDUCTOR transistors and Schottky diodes produced in complementary metal-oxide semiconductors, we lay out a plan for terahertz COMPLEMENTARY METAL OXIDE SEMICONDUCTOR systems and circuits, highlighting critical challenges that need to be addressed. With the advent of terahertz COMPLEMENTARY METAL OXIDE SEMICONDUCTOR

Ultra-fast switching memristors based on two-dimensional materials

The ability to scale two-dimensional (2D) material thickness down to a single monolayer presents a promising opportunity to realize high-speed energy-efficient memristors. Here, we report an ultra-fast memristor fabricated using atomically thin sheets of 2D hexagonal Boron Nitride, exhibiting the shortest observed switching speed (120 ps) among 2D memristors and low switching energy (2pJ). Furthermore, we study the switching dynamics of these memristors using ultra-short (120ps-3ns) voltage pulses, a frequency range that is highly relevant in the context of modern complementary metal oxide semiconductor (CMOS) circuits. We employ statistical analysis of transient characteristics to gain insights into the memristor switching mechanism. Cycling endurance data confirms the ultra-fast switching capability of these memristors, making them attractive for next generation computing, storage, and Radio-Frequency (RF) circuit applications.

In-sensor nonlinear convolutional processing based on hybrid MTJ/CMOS arrays

In-sensor computing implemented by novel neuromorphic devices has been regarded as the potential technology to break the acquisition wall. Moreover, the nonlinear convolution inspired by the biological neural system outperforms the traditional linear convolution. Therefore, realizing the in-sensor nonlinear convolutional processing with the intrinsic nonlinearity of novel neuromorphic devices would be exciting and hardware friendly. Here, a new type of in-sensor nonlinear convolutional processing architecture is proposed based on STT-MTJ (spin transfer torque-magnetic tunnel junction) devices and simple peripheral circuits. The nonlinear dynamic characters of the STT-MTJ device are regulated by bias currents and magnetic fields. Meanwhile, the hybrid STT-MTJ/CMOS (complementary metal oxide semiconductor) circuit exhibits nonlinear dependence of the output voltage on bias currents and magnetic fields. In this way, a nonlinear convolutional unit is developed by the inherent property of hardware. Based on the in-sensor nonlinear convolutional unit, a convolutional network is simulated to perform the classification task, and a high accuracy is realized. This work indicates that the in-sensor nonlinear convolution offers a promising way to develop in-sensor computing at the edge intelligence devices.

Design and Assessment of Hybrid MTJ/CMOS Circuits for In-Memory-Computation

Hybrid magnetic tunnel junction/complementary metal oxide semiconductor (MTJ/CMOS) circuits based on in-memory-computation (IMC) architecture is considered as the next-generation candidate for the digital integrated circuits. However, the energy consumption during the MTJ write process is a matter of concern in these hybrid circuits. In this regard, we have developed a novel write circuit for the contemporary three-terminal perpendicular-MTJs that works on the voltage-gated spin orbit torque (VG+SOT) switching mechanism to store the information in hybrid circuits for IMC architecture. Investigation of the novel write circuit reveals a remarkable reduction in the total energy consumption (and energy delay product) of 92.59% (95.81) and 92.28% (42.03%) than the conventional spin transfer torque (STT) and spin-Hall effect assisted STT (SHE+STT) write circuits, respectively. Further, we have developed all the hybrid logic gates followed by nonvolatile full adders (NV-FAs) using VG+SOT, STT, and SHE+STT MTJs. Simulation results show that with the VG+SOT NOR-OR, NAND-AND, XNOR-XOR, and NV-FA circuits, the reduction in the total power dissipation is 5.35% (4.27%), 5.62% (3.2%), 3.51% (2.02%), and 4.46% (2.93%) compared to STT (SHE+STT) MTJs respectively.

Three-dimensional sensing of surfaces by projection of invisible electroluminescence from organic light-emitting diodes.

Organic light-emitting diodes (OLEDs) that efficiently emit near-infrared (NIR) light and consume little power will create valuable applications for OLEDs beyond just displays. Here, we report such a NIR-OLED with high operational stability that can be used as a light source for three-dimensional sensing of object's surfaces. Using a narrow-energy-gap material as a host for producing NIR hyperfluorescence system, we fabricated a NIR-OLED exhibiting intense emission at 930 nm with a high external electroluminescence quantum efficiency of more than 1% at a current density of 100 milliamperes per square meter without any degradation even after more than 300 hours of operation. The NIR-OLEDs were integrated with dense complementary metal-oxide semiconductor circuits to make a micro-NIR-OLED projector (0.21 inch, 230,400 pixels). By actively driving the projector on a pixel by pixel and projecting their emission onto objects, we successfully scanned and sensed the surfaces in three dimensions with invisible NIR.

Hierarchies in Visual Pathway: Functions and Inspired Artificial Vision.

The development of artificial intelligence has posed a challenge to machine vision based on conventional complementary metal-oxide semiconductor (CMOS) circuits owing to its high latency and inefficient power consumption originating from the data shuffling between memory and computation units. Gaining more insights into the function of every part of the visual pathway for visual perception can bring the capabilities of machine vision in terms of robustness and generality. Hardware acceleration of more energy-efficient and biorealistic artificial vision highly necessitates neuromorphic devices and circuits that are able to mimic the function of each part of the visual pathway. In this paper, wereview the structure and function of the entire class of visual neurons from the retina to the primate visual cortex within reach (Chapter 2) are reviewed. Based on the extraction of biological principles, the recent hardware-implemented visual neurons located in different parts of the visual pathway are discussed in detail in Chapters 3 and 4. Furthermore, valuable applications of inspired artificial vision in different scenarios (Chapter 5) are provided. The functional description of the visual pathway and its inspired neuromorphic devices/circuits are expected to provide valuable insights for the design of next-generation artificial visual perception systems.

An Optimal DPM Based Energy-Aware Task Scheduling for Performance Enhancement in Embedded MPSoC

Minimizing the energy consumption to increase the life span and performance of multiprocessor system on chip (MPSoC) has become an integral chip design issue for multiprocessor systems. The performance measurement of computational systems is changing with the advancement in technology. Due to shrinking and smaller chip size power densities on-chip are increasing rapidly that increasing chip temperature in multi-core embedded technologies. The operating speed of the device decreases when power consumption reaches a threshold that causes a delay in complementary metal oxide semiconductor (CMOS) circuits because high on-chip temperature adversely affects the life span of the chip. In this paper an energy-aware dynamic power management technique based on energy aware earliest deadline first (EA-EDF) scheduling is proposed for improving the performance and reliability by reducing energy and power consumption in the system on chip (SOC). Dynamic power management (DPM) enables MPSOC to reduce power and energy consumption by adopting a suitable core configuration for task migration. Task migration avoids peak temperature values in the multi-core system. High utilization factor ( on central processing unit (CPU) core consumes more energy and increases the temperature on-chip. Our technique switches the core by migrating such task to a core that has less temperature and is in a low power state. The proposed EA-EDF scheduling technique migrates load on different cores to attain stability in temperature among multiple cores of the CPU and optimized the duration of the idle and sleep periods to enable the low-temperature core. The effectiveness of the EA-EDF approach reduces the utilization and energy consumption compared to other existing methods and works. The simulation results show the improvement in performance by optimizing 4.8% on 9%, 16%, 23% and 25% at 520 MHz operating frequency as compared to other energy-aware techniques for MPSoCs when the least number of tasks is in running state and can schedule more tasks to make an energy-efficient processor by controlling and managing the energy consumption of MPSoC.

A nanomagnets majority logic gate based on heterogeneous multiferroic structure global strain clock

<sec>In the post-Moore era, nanomagnetic logic circuits have shown great potential to replace complementary metal oxide semiconductor (CMOS) circuits. A majority logic gate, as the core of a nanomagnetic logic circuit, is equivalent to the inverter in the CMOS circuit. A nanomagnetic logic majority gate generally has four nanomagnets arranged in a “T” shape. The nanomagnets in the three corners of the “T” (<i>I</i><sub>1</sub>, <i>I</i><sub>2</sub>, <i>I</i><sub>3</sub>) are the three inputs, and the middle nanomagnet is the output (<i>O</i>).</sec><sec>This paper proposes a nanomagnet majority logic gate based on the global strain clock of heterogeneous multiferroic structure, by utilizing the difference in response to the same strain between positive magnetostrictive coefficient material (Terfenol-D) and negative magnetostrictive coefficient material (Ni). From bottom to top, the device is mainly composed of a silicon substrate, a piezoelectric layer, and four elliptical cylindrical nanomagnets. PMN-PT is used as the piezoelectric layer’s material, and three Ni-based nanomagnets (<i>I</i><sub>1</sub>, <i>I</i><sub>2</sub>, and <i>I</i><sub>3</sub>) are utilized as input, while Terfenol-D is used as the material for the output nanomagnet (<i>O)</i>.</sec><sec>Besides, a two-step calculation mode of “high-stress start-low-stress calculation” is designed, that is, the <i>O</i> is first switched to the “Null” with a stress of –30 MPa, and then the stress decreases to –15 MPa, so that the <i>O</i> can realize majority calculation under the coupling of <i>I</i><sub>1</sub>, <i>I</i><sub>2</sub>, and <i>I</i><sub>3</sub>. The micromagnetic simulation software MuMax3 is adopted to simulate the performance of the device. The results reveal that the device can successfully perform continuous majority calculation through any three-terminal input combination. By using the two-step calculation mode, the calculation accuracy of the device can reach 100%, its cycle of continuous calculation is 2.75 ns, and the cycle energy consumption is about 64 aJ. It is found that the change of energy potential well, caused by the change of stress anisotropy energy and dipole coupling energy, is the main reason that determines the magnetization dynamic behavior of the device. Therefore, the results of this paper can provide important guidance for designing nanomagnetic logic circuits.</sec>

Energy-Efficient Scheduling Based on Task Migration Policy Using DPM for燞omogeneous MPSoCs

Increasing the life span and efficiency of Multiprocessor System on Chip (MPSoC) by reducing power and energy utilization has become a critical chip design challenge for multiprocessor systems. With the advancement of technology, the performance management of central processing unit (CPU) is changing. Power densities and thermal effects are quickly increasing in multi-core embedded technologies due to shrinking of chip size. When energy consumption reaches a threshold that creates a delay in complementary metal oxide semiconductor (CMOS) circuits and reduces the speed by 10%–15% because excessive on-chip temperature shortens the chip’s life cycle. In this paper, we address the scheduling & energy utilization problem by introducing and evaluating an optimal energy-aware earliest deadline first scheduling (EA-EDF) based technique for multiprocessor environments with task migration that enhances the performance and efficiency in multiprocessor system-on-chip while lowering energy and power consumption. The selection of core and migration of tasks prevents the system from reaching its maximum energy utilization while effectively using the dynamic power management (DPM) policy. Increase in the execution of tasks the temperature and utilization factor on-chip increases that dissipate more power. The proposed approach migrates such tasks to the core that produces less heat and consumes less power by distributing the load on other cores to lower the temperature and optimizes the duration of idle and sleep times across multiple CPUs. The performance of the EA-EDF algorithm was evaluated by an extensive set of experiments, where excellent results were reported when compared to other current techniques, the efficacy of the proposed methodology reduces the power and energy consumption by 4.3%–4.7% on a utilization of 6%, 36% & 46% at 520 & 624 MHz operating frequency when particularly in comparison to other energy-aware methods for MPSoCs. Tasks are running and accurately scheduled to make an energy-efficient processor by controlling and managing the thermal effects on-chip and optimizing the energy consumption of MPSoCs.

Method of simulating hybrid STT-MTJ/CMOS circuits based on MATLAB/Simulink

The spin-transfer-torque (STT) magnetic tunneling junction (MTJ) device is one of the prominent candidates for spintronic logic circuit and neuromorphic computing. Therefore, building a simulation framework of hybrid STT-MTJ/CMOS (complementary metal–oxide–semiconductor) circuits is of great value for designing a new kind of computing paradigm based on the spintronic devices. In this work, we develop a simulation framework of hybrid STT-MTJ/CMOS circuits based on MATLAB/Simulink, which is mainly composed of a physics-based STT-MTJ model, a controlled resistor, and a current sensor. In the proposed framework, the STT-MTJ model, based on the Landau–Lifshitz–Gilbert–Slonczewsk (LLGS) equation, is implemented using the MATLAB script. The proposed simulation framework is modularized design, with the advantage of simple-to-use and easy-to-expand. To prove the effectiveness of the proposed framework, the STT-MTJ model is benchmarked with experimental results. Furthermore, the pre-charge sense amplifier (PCSA) circuit consisting of two STT-MTJ devices is validated and the electrical coupling of two spin-torque oscillators is simulated. The results demonstrate the effectiveness of our simulation framework.

Design and implementation reversible multiplexer using quantum-dot cellular automata approach

Rapid progress in the field of nanotechnology includes using quantum dot-cellular automata (QCA) as a replacement for conventional transistor-based complementary metal oxide semiconductor (CMOS) circuits in the construction of nano-circuits. Due to ultra low thermal dissipation, rapid clocking, and extremely high density, the QCA is a rapidly growing field in the nanotechnological field to inhibit the field effect transistor (FET)-based circuit. This paper discusses and evaluates two multiplexer (MUX) architectures: an innovative and effective 4×1 MUX structure and an 8×1 MUX structures using QCA technology. The suggested architectural designs are constructed using the Fredkin and controlled-NOT (CNOT) gates. These constructions were designed to simulate using tool QCA designer 2.0.3. The 591 and 1,615 cells would be used by the 4×1 and 8×1 QCA MUX architectures, respectively. The simulation results demonstrate that, when compared to the previous QCA MUX structures, the suggested QCA MUX designs have the best clock latency performance and use of different gate types.

Cost-effective Programmable Logic Arrays Using Multilayer Structures of Decoders in QCA Framework

The emerging nanotechnology paradigm, Quantum Dot Cellular Automata (QCA) in particular, is gaining a wide recognition due to its high speed, nano feature size and considerably low power consumption. The QCA architecture not only provide potential alternative for Complementary Metal Oxide Semiconductor (CMOS) circuits but its multilayer topology facilitates an added benefit of cost efficacy and immunity towards random interference. Moreover, design of programmable logic devices in QCA is vital to promote the multi-utility and resiliency of the computing circuits. This paper presents the multilayer designs of 2×4 and 3×8 decoder circuits in QCA framework with 55.1% and 51.17% better cost efficiency respectively, over the earlier reported designs. The presented 3×8 decoder circuit is further utilized to implement Programmable Logic Array (PLA) to realize Boolean functions of adder and subtractor. The presented circuits are cost effective and showcase the significance of programmable devices in nano-computing.

Dynamic electrostatic-discharge path investigation relied on different impact energies in metal–oxide–semiconductor circuits

Gate-grounded n-channel metal–oxide–semiconductor (GGNMOS) devices have been widely implemented as power clamps to protect semiconductor devices from electrostatic discharge stress owing to their simple construction, easy triggering, and low power dissipation. We present a novel I–V characterization of the GGNMOS used as the power clamp in complementary metal–oxide–semiconductor circuits as a result of switching the ESD paths under different impact energies. This special effect could cause an unexpected latch-up or pre-failure phenomenon in some applications with relatively large capacitances from power supply to power ground, and thus should be urgently analyzed and resolved. Transmission-line-pulse, human-body-modal, and light-emission tests were performed to explore the root cause.

Soft error mechanism in SOI D flip-flop induced by space electrostatic discharge

This study investigates the characteristics, sensitive regions, and failure mechanism of 'soft errors' caused by Spacecraft charging induced Electrostatic Discharge (SESD) in a full custom 130 nm Fully Depleted Silicon-On-Insulator (FD-SOI) D flip-flop (DFF) device through SPICE simulation and SESD experiment at room temperature. The results showed that the main characteristic of the soft errors caused by the SESD was manifested in bit '1' upset in the DFF cells, and the SESD sensitive regions were located at the reset and power pins. The possible failure mechanism in the DFF circuit was the misrecognition of the reset signal and the recoverable breakdown of its inner P-channel Metal Oxide Semiconductor (PMOS) circuit induced by the SESD transients.