Metal Oxide Resistive Random Access Research Articles

A cold-electrode metal–oxide resistive random access memory

To reduce the leakage and power consumption of metal–oxide resistive random access memory (RRAM), we propose and fabricate a cold-electrode (CE) RRAM (CE-RRAM) by extending the mechanism of cold-source FETs. First-principles calculations show that the n-Si/TiN composite CE can filter electrons with energy within the Si bandgap, which contribute to leakage current. A n-Si/TiN/HfOx/Pt CE-RRAM with low leakage current and large on/off current ratio was designed and fabricated. Comparative analysis with conventional RRAM demonstrates over a 100-fold reduction in leakage current in a high resistance state and a tenfold improvement in the Ion/Ioff ratio. Additionally, the CE-RRAM effectively suppresses the overshoot effect in terminal I–V characteristics and exhibits good endurance, maintaining a 100 Ion/Ioff ratio after 104 cycles. Furthermore, even after 104 s at 100 °C, the state remains unchanged. Moreover, the CE-RRAM demonstrates its multi-level storage capability.

A Study on Unified Modelling Approach for Memristor: Next Generation Semiconductor Devices

This research investigates the voltage-current (V-I) characteristics of three distinct memristor models, each representing a unique composition and behaviour. The model, denoted as TiN-TiOx-HfOx-Pt-Bilayered Memristor model, is a compact representation designed for Metal–Oxide Resistive Random Access Memory (RRAM). Matlab tool is used for the simulation to analyse V-I characteristics of Memristor. Through comprehensive analysis and simulations, we aim to provide a detailed insight into the intrinsic behaviours of the memristor models. Understanding the V-I characteristics of these models is crucial for their potential applications in emerging memory technologies. This Study elaborate the mathematical modelling of memristor with the outcome untuned V-I Characteristics - DC Switching characteristics. The findings contribute to the broader field of memristor research, fostering advancements in electronic memory devices and computational systems

Optimization of Bilayer Resistive Random Access Memory Based on Ti/HfO2/ZrO2/Pt.

In this paper, the electrothermal coupling model of metal oxide resistive random access memory (RRAM) is analyzed by using a 2D axisymmetrical structure in COMSOL Multiphysics simulation software. The RRAM structure is a Ti/HfO2/ZrO2/Pt bilayer structure, and the SET and RESET processes of Ti/HfO2/ZrO2/Pt are verified and analyzed. It is found that the width and thickness of CF1 (the conductive filament of the HfO2 layer), CF2 (the conductive filament of the ZrO2 layer), and resistive dielectric layers affect the electrical performance of the device. Under the condition of the width ratio of conductive filament to transition layer (6:14) and the thickness ratio of HfO2 to ZrO2 (7.5:7.5), Ti/HfO2/ZrO2/Pt has stable high and low resistance states. On this basis, the comparison of three commonly used RRAM metal top electrode materials (Ti, Pt, and Al) shows that the resistance switching ratio of the Ti electrode is the highest at about 11.67. Finally, combining the optimal conductive filament size and the optimal top electrode material, the I-V hysteresis loop was obtained, and the switching ratio Roff/Ron = 10.46 was calculated. Therefore, in this paper, a perfect RRAM model is established, the resistance mechanism is explained and analyzed, and the optimal geometrical size and electrode material for the hysteresis characteristics of the Ti/HfO2/ZrO2/Pt structure are found.

Effects of Ambient and Annealing Temperature in HfO2 Based RRAM Device Modeling and Circuit-Level Implementation

This article focuses on the relevance of the effect of ambient temperature and annealing in the context of compact modeling of metal oxide resistive random access memory (RRAM) devices. The ambient temperature affects the conduction characteristic of resistive switching memories, so it becomes an essential factor to include when adjusting the experimental data. Reported the fabricated results and memory switching parameters with the defined set (Vset) and reset (Vreset) transition voltages for the fabricated annealed HfO2-based RRAM. Additionally, to illustrate the importance of this characteristic in the form of the I-V curve, the Stanford model (SFM) for RRAM devices is enhanced by incorporating the annealing temperature as an additional parameter in the script of the Verilog-A model. Stanford and modified Stanford model (MSFM) are analyzed at the device level using cadence circuit simulator and implemented in the nonvolatile memory circuit (3 *3 memory arrays). Results confirmed that the experimental switching voltages, Vset, Vreset are 1.7 V, −0.8 V. These values are well suited along the simulated MSFM switching voltages of, Vset, Vreset (1.8 V, −0.7 V). The mean error percentage of the MSF is 18.42%.

Oscillatory Circuits With a Real Non-Volatile Stanford Memristor Model

Stanford memristor model is a widely used model that accurately characterizes real non-volatile metal-oxide resistive random access memory (RRAM) devices with bipolar switching characteristics. The paper studies for the first time the dynamics and bifurcations in a class of nonlinear oscillators with <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">real non-volatile memristor devices</i> obeying Stanford model. This is in contrast with papers in the literature considering oscillators with ideal, abstract, or artificial memristor models, that are unable to describe physical memristors implemented in nanotechnology. One main new idea in the paper is to use the memristor as a <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">programmable nonlinear resistor</i> . Namely, two principal modes of operation are considered. 1) Analogue transient phase: the oscillator is designed so that in the transient oscillations the voltage on the memristor is below threshold, hence the main memristor state variable, i.e., the gap of the insulating material, is almost constant and the memristor behaves as a static nonlinear resistor. 2) Programming phase: the nonlinear characteristic of the memristor, which depends on the gap, can be changed via the application of voltages above threshold. The paper studies nonlinear oscillations in the transient phase for a fixed gap as well as the bifurcations phenomena displayed when the gap is varied. The paper also discusses the differences between the approach in the paper and those to design other memristor oscillators with non-volatile memristors.

Physics-Based Stochastic Three-Dimensional Modeling for Metal–Oxide Resistive Random Access Memory

In this work, a fully physics-based stochastic 3-D modeling of metal–oxide-based resistive random access memory (RRAM) device has been conducted. In contrast to general 1-D or 2-D modeling of RRAM devices, 3-D modeling is able to provide a picture of the evolution of the 3-D random distributions of oxygen vacancies and temperature inside the device during the forming and SET/RESET processes. The modeling confirms that a tunneling gap between the top electrode (TE) which serves as an oxygen ion reservoir and the tip of the conductive filament may form at a high resistive state, which is assumed in the frequently used compact models of RRAM devices. The modeling shows that the sites with high temperature are concentrated in a cylindrical region at the center of the RRAM device, running from the inert bottom electrode to the TE. The modeling can reproduce both typical current-voltage characteristics of metal–oxide RRAM devices in forming and RESET and SET operations under a dc voltage sweep and the modulation of RRAM conductance by SET/RESET pulses.

A simplified method to determine carrier transport mechanisms of metal-oxide resistive random access memory (RRAM) devices

The current carrier transport mechanism in non-linear resistance states of the current–voltage (I–V) curves of the resistance changing or resistive switching (RS) based random access memory (RRAM) devices would help to understand the physics behind the resistive switching phenomena. The non-linear portion of the I–V curves are most commonly categorized by three different types of conduction mechanisms, the space charge limit current (SCLC), the Schottky emission (SE) and the Poole-Frenkel (P-F) effect respectively. In this study, the current–voltage curves of the RS devices limited to the non-linear region were plotted on a log–log scale with the purpose of distinguishing the dominant current conduction mechanisms. Each of the I–V curves narrowed to the non-linear region were re-plotted for SCLC at the scale of I vs. V2, for SE at the scale of ln I vs. √V and for P-F at the scale of ln I/V vs. √V. The linear fitting lines were plotted and calculated for each one using linear fitting techniques. The slopes of the fitting lines were found respect to the scales using linear fitting equations. The conduction mechanisms of the devices were determined numerically using the degree of linearity of the slopes. Finally, the offered method was applied to TiO2 based resistive switching device.

Bidirectional Volatile Signatures of Metal-Oxide Memristors—Part II: Modeling

Volatility in metal-oxide resistive random access memory (RRAM) families has mostly been treated as an unwanted side-effect, although recently there are trends to interpret such behavior as an additional technological feature. To date, the field has seen early demonstrations of possible applications that harness volatility. Moreover, some work has been conducted to understand both the mechanisms responsible for this behavior. In the context of modeling RRAM volatility, we still lack a comprehensive model that could allow simulations in a larger scale. In an attempt to fill this gap, this work presents a modeling framework that can account for RRAM relaxation characteristics. Specifically, we show how volatility can be simulated to significant accuracy when the resistive state (RS) of a device as well as the stimulus protocol in use are well-defined. Importantly, our approach is solely data-driven and decoupled from previous physical modeling studies on volatility. Our results work for both stimulation polarities and are consistent for a number of $TiO_{x}$ devices in use. Moreover, the mathematical relations that unfold via modeling volatility provide further intuition on the effect that invasive protocols can have on this technology. This modeling solution enables more advanced studying of memristive technologies in one hand, as well as more intricate designs of larger systems that can account for transient RRAM changes over time.

STAR: Synthesis of Stateful Logic in RRAM Targeting High Area Utilization

Processing-in-memory (PIM) exploits massive parallelism with high energy efficiency and becomes a promising solution to the von Neumann bottleneck. Recently, the emerging metal-oxide resistive random access memory (RRAM) shows its potential to construct a PIM architecture, because several stateful logic operations, e.g., IMP and NOR, can be executed in an RRAM crossbar in parallel. Previous synthesis flows focus on improving latency with stateful logic operations, but they ignore that the memory should be used primarily for storage. i.e., most of the area in the crossbar is used for computation but not storage. In this situation, storage and computation still have to be separated into different crossbars, which leads to considerable data transfer overhead and limited parallelism. In this work, we define the ratio of storage in a crossbar as area utilization. We aim to improve the area utilization without throughput loss by proposing STAR, a novel synthesis flow for the stateful logic. We present two optimization strategies to reduce the computation area in STAR. First, we reduce the area for redundant inputs. For the shared constants among different rows (or columns), we encode them as immediate values into the control signals without writing them into the crossbar at runtime. For the other inputs, we only store one copy of them in the crossbar. Second, we reduce the area for intermediate variables by reusing invalid cells. And we design a scheduling algorithm to find a computation sequence with the minimal variable erasing cycles. Invalid primary inputs can also be erased in this algorithm. Furthermore, we present a case study of the image convolution to demonstrate the effectiveness of STAR. Experimental evaluation shows that STAR achieves 33.03% more area utilization and a 1.43x throughput compared to SIMPLER, the state-of-the-art stateful logic synthesis flow. Our image convolution implementation also provides 78.36% more area utilization and a 1.48x throughput compared with IMAGING, the state-of-the-art stateful logic-based image processing accelerator.

Design and Hardware Implementation of Neuromorphic Systems With RRAM Synapses and Threshold-Controlled Neurons for Pattern Recognition

In this paper, a hardware-realized neuromorphic system for pattern recognition is presented. The system directly captures images from the environment, and then conducts classification using a single layer neural network. Metal-oxide resistive random access memory (RRAM) is used as electronic synapses, and threshold-controlled neurons are proposed as postsynaptic neurons to save the system area and simplify the operation. In the proposed threshold-controlled neuron, no capacitor is utilized, which contributes to higher integration density. The total energy consumption of RRAM synapses for classifying an example is 0.31μJ on average. The proposed system has been implemented on hardware, and has been experimentally demonstrated to show the capability of pattern recognition.

Au doping effects in ZrO&amp;lt;sub&amp;gt;2&amp;lt;/sub&amp;gt;-based resistance random access memory based on first-principles calculations

Oxygen vacancy plays the critical role for resistive switching in transition metal oxide resistive random access memory (RRAM). First principles calculation was performed to investigate the band structure, density of states, the oxygen vacancy formation energy and the migration barriers energy of pure ZrO2 and Au doped ZrO2, and we analyzed the impact of Au doping in ZrO2-based RRAM. It was found that the localized impurity band at the Fermi level appeared in forbidden band and the band gap was significantly reduced in Au doped ZrO2, which improved the conductivity of ZrO2. By doping Au in ZrO2, the formation energy and the migration barriers energy of oxygen vacancy were significantly reduced, indicating that it was beneficial to the formation and migration of oxygen vacancy and decreased the forming voltage and the set voltage of ZrO2-based RRAM. The electron localization function was used to study the [001] direction oxygen vacancy cluster of ZrO2 supercell with an Au doped element. The results showed that the oxygen vacancy around the impurity formed an ordered conductive filament in the [001] direction.

An energy efficient and high speed architecture for convolution computing based on binary resistive random access memory

In this work we present a novel convolution computing architecture based on metal oxide resistive random access memory (RRAM) to process the image data stored in the RRAM arrays. The proposed image storage architecture shows performances of better speed-device consumption efficiency compared with the previous kernel storage architecture. Further we improve the architecture for a high accuracy and low power computing by utilizing the binary storage and the series resistor. For a 28 × 28 image and 10 kernels with a size of 3 × 3, compared with the previous kernel storage approach, the newly proposed architecture shows excellent performances including: 1) almost 100% accuracy within 20% LRS variation and 90% HRS variation; 2) more than 67 times speed boost; 3) 71.4% energy saving.

A Novel ReRAM-Based Processing-in-Memory Architecture for Graph Traversal

Graph algorithms such as graph traversal have been gaining ever-increasing importance in the era of big data. However, graph processing on traditional architectures issues many random and irregular memory accesses, leading to a huge number of data movements and the consumption of very large amounts of energy. To minimize the waste of memory bandwidth, we investigate utilizing processing-in-memory (PIM), combined with non-volatile metal-oxide resistive random access memory (ReRAM), to improve both computation and I/O performance. We propose a new ReRAM-based processing-in-memory architecture called RPBFS, in which graph data can be persistently stored and processed in place. We study the problem of graph traversal, and we design an efficient graph traversal algorithm in RPBFS. Benefiting from low data movement overhead and high bank-level parallel computation, RPBFS shows a significant performance improvement compared with both the CPU-based and the GPU-based BFS implementations. On a suite of real-world graphs, our architecture yields a speedup in graph traversal performance of up to 33.8×, and achieves a reduction in energy over conventional systems of up to 142.8×.

Device Instability of ReRAM and a Novel Reference Cell Design for Wide Temperature Range Operation

This letter addresses two difficult challenges for transition metal oxide resistive random access memories (ReRAMs)—sensitivity to operation temperature and random fluctuation of resistance value. A careful study of a WO x ReRAM array reveals that these devices are unstable and their read currents fluctuate with time due to random telegraph noise and structure relaxation. Consequently, even after careful programming, the current distribution can broaden with time and tail bit population grows. Furthermore, ReRAM state is sensitive to temperature and a reference cell made of the same device material must be used. Thus, although the broadening of read current distribution may be tolerated by creating a larger RESET/SET memory window, the current fluctuation still makes it impossible to predict the output of the reference cell, leading to array malfunction. This letter investigates the current (resistance) instability in detail and proposes a reference array with a novel trimming method that can stabilize the reference current level. The proposed reference array has very good dc stress reliability as well as wide-range temperature tracking performance from −40 °C to 85 °C.

Distinguishing Oxygen Vacancy Electromigration and Conductive Filament Formation in TiO2 Resistance Switching Using Liquid Electrolyte Contacts.

Resistance switching in TiO2 and many other transition metal oxide resistive random access memory materials is believed to involve the assembly and breaking of interacting oxygen vacancy filaments via the combined effects of field-driven ion migration and local electronic conduction leading to Joule heating. These complex processes are very difficult to study directly in part because the filaments form between metallic electrode layers that block their observation by most characterization techniques. By replacing the top electrode layer in a metal-insulator-metal memory structure with easily removable liquid electrolytes, either an ionic liquid (IL) with high resistance contact or a conductive aqueous electrolyte, we probe field-driven oxygen vacancy redistribution in TiO2 thin films under conditions that either suppress or promote Joule heating. Oxygen isotope exchange experiments indicate that exchange of oxygen ions between TiO2 and the IL is facile at room temperature. Oxygen loss significantly increases the conductivity of the TiO2 films; however, filament formation is not observed after IL gating alone. Replacing the IL with a more conductive aqueous electrolyte contact and biasing does produce electroformed conductive filaments, consistent with a requirement for Joule heating to enhance the vacancy concentration and mobility at specific locations in the film.

Impact of ultra-thin Al2O3–y layers on TiO2–x ReRAM switching characteristics

Transition metal-oxide resistive random access memory devices have demonstrated excellent performance in switching speed, versatility of switching and low-power operation. However, this technology still faces challenges like poor cycling endurance, degradation due to high electroforming (EF) switching voltages and low yields. Approaches such as engineering of the active layer by doping or addition of thin oxide buffer layers have been often adopted to tackle these problems. Here, we have followed a strategy that combines the two; we have used ultra-thin Al2O3–y buffer layers incorporated between TiO2–x thin films taking into account both 3+/4+ oxidation states of Al/Ti cations. Our devices were tested by DC and pulsed voltage sweeping and in both cases demonstrated improved switching voltages. We believe that the Al2O3–y layers act as reservoirs of oxygen vacancies which are injected during EF, facilitate a filamentary switching mechanism and provide enhanced filament stability, as shown by the cycling endurance measurements.

A Novel Varying-Bias Read Scheme for MLC and Wide Temperature Range TMO ReRAM

Resistance of transition metal oxide (TMO) resistive random access memory (ReRAM) depends sharply on temperature, resulting in drastic memory window loss at high temperature. Thus, it is difficult to design the ReRAM that can serve a wide range of operating conditions. It is especially challenging to achieve multi-level-cell (MLC) ReRAM because of the large temperature dependency. This letter investigates both the temperature and read bias dependencies of WO x ReRAM, and found both can be well understood by a modified space-charge limited conduction model. Using this model, we have designed a novel read scheme that varies the read bias according to the device temperature and compensates for the temperature effect on cell resistance. Since TMO ReRAM devices depend on defect states, cell-to-cell and cycle-to-cycle variations are naturally large. An algorithm is designed to address the variability. A 1-Mb WO x ReRAM array is fabricated to both characterize the bias and temperature dependencies and verify the new read scheme. A large and constant memory window is preserved for MLC across a wide temperature range (−40 °C–125 °C), suitable for high-reliability applications.

PRIME

Processing-in-memory (PIM) is a promising solution to address the "memory wall" challenges for future computer systems. Prior proposed PIM architectures put additional computation logic in or near memory. The emerging metal-oxide resistive random access memory (ReRAM) has showed its potential to be used for main memory. Moreover, with its crossbar array structure, ReRAM can perform matrix-vector multiplication efficiently, and has been widely studied to accelerate neural network (NN) applications. In this work, we propose a novel PIM architecture, called PRIME, to accelerate NN applications in ReRAM based main memory. In PRIME, a portion of ReRAM crossbar arrays can be configured as accelerators for NN applications or as normal memory for a larger memory space. We provide microarchitecture and circuit designs to enable the morphable functions with an insignificant area overhead. We also design a software/hardware interface for software developers to implement various NNs on PRIME. Benefiting from both the PIM architecture and the efficiency of using ReRAM for NN computation, PRIME distinguishes itself from prior work on NN acceleration, with significant performance improvement and energy saving. Our experimental results show that, compared with a state-of-the-art neural processing unit design, PRIME improves the performance by ~2360× and the energy consumption by ~895×, across the evaluated machine learning benchmarks.

A Compact Model for Metal–Oxide Resistive Random Access Memory With Experiment Verification

A dynamic Verilog-A resistive random access memory (RRAM) compact model, including cycle-to-cycle variation, is developed for circuit/system explorations. The model not only captures dc and ac behavior, but also includes intrinsic random fluctuations and variations. A methodology to systematically calibrate the model parameters with experiments is presented and illustrated with a broad set of experimental data, including multilayer RRAM. The physical meanings of the various model parameters are discussed. An example of applying the RRAM cell model to a ternary content-addressable-memory (TCAM) macro is provided. Tradeoffs on the design of RRAM devices for the TCAM macro are discussed in the context of the energy consumption and worst case latency of the memory array.

Technological Exploration of RRAM Crossbar Array for Matrix-Vector Multiplication

Matrix-vector multiplication is the key operation for many computationally intensive algorithms. The emerging metal oxide resistive switching random access memory (RRAM) device and RRAM crossbar array have demonstrated a promising hardware realization of the analog matrix-vector multiplication with ultra-high energy efficiency. In this paper, we analyze the impact of both device level and circuit level non-ideal factors, including the nonlinear current-voltage relationship of RRAM devices, the variation of device fabrication and write operation, and the interconnect resistance as well as other crossbar array parameters. On top of that, we propose a technological exploration flow for device parameter configuration to overcome the impact of non-ideal factors and achieve a better trade-off among performance, energy, and reliability for each specific application. Our simulation results of a support vector machine (SVM) and Mixed National Institute of Standards and Technology (MNIST) pattern recognition dataset show that RRAM crossbar array based SVM is robust to input signal fluctuation but sensitive to tunneling gap deviation. A further resistance resolution test presents that a 6-bit RRAM device is able to realize a recognition accuracy around 90 %, indicating the physical feasibility of RRAM crossbar array based SVM. In addition, the proposed technological exploration flow is able to achieve 10.98 % improvement of recognition accuracy on the MNIST dataset and 26.4 % energy savings compared with previous work. Experimental results also show that more than 84.4 % power saving can be achieved at the cost of little accuracy reduction.