Metal/interlayer/semiconductor Research Articles

Formation of Low-Resistivity Metal/Germanium Contact with Ultra-Thin Interlayer and Plasma Oxidation for n-Channel Germanium FET

In this work, the plasma oxidation process is introduced into the metal–interlayer–semiconductor (M–I–S) structure to reduce the contact resistance of the metal/n-type germanium (n-Ge) contact. The GeOx layer formed by the plasma oxidation process acts as a good passivation layer between TiO2 and Ge, and also an additional metal induced gap states (MIGS) blocking layer. From these effects of the GeOx layer, the M–I–S structure with multi-layered interlayer stack, TiO2/GeOx, shows approximately four orders of magnitude of the reverse current density improvement from the M–S contact. This technique can be a solution of the severe Fermi-level pinning (FLP) and the high contact resistance in source/drain (S/D) regions of the n-channel germanium field-effect transistor (FET).

Influence of nanostructure Fe-doped ZnO interlayer on the electrical properties of Au/n-type InP Schottky structure

The Au/Fe-doped ZnO/n-InP metal/interlayer/semiconductor (MIS) Schottky structure is fabricated with Fe-doped ZnO nanostructure (NS) as an interlayer. The field emission scanning electron microscopy and atomic force microscopy results demonstrated that the surface morphology of the FeZnO NS on n-InP is fairly smooth. The x-ray diffraction results reveal that the average grain size of the FeZnO film is 12.35 nm. The electrical properties of the Au/n-InP metal-semiconductor (MS) and Au/FeZnO NS/n-InP MIS Schottky structures are investigated by current-voltage and capacitance-voltage measurements at room temperature. The Au/FeZnO NS/n-InP MIS Schottky structure has good rectifying ratio with low-leakage current compared to the Au/n-InP MS structure. The barrier height obtained for the MIS structure is higher than those of MS Schottky structure because of the modification of the effective barrier height by the FeZnO NS interlayer. Further, the barrier height, ideality factor and series resistance are determined for the MS and MIS Schottky structures using Norde and Cheung's functions and compared to each other. The estimated interface state density of MIS Schottky structure is lower than that of MS Schottky structure. Experimental results revealed that the Poole-Frenkel emission is the dominant conduction mechanism in the lower bias region whereas Schottky emission is the dominant in the higher bias region for both the Au/n-InP MS and Au/FeZnO NS/n-InP MIS Schottky structures.

Source/Drain Contact Resistance Reduction through Al-Doped ZnO Interlayer to Metal-Interlayer-GaAs Contact Structure

As silicon-based complementary metal-oxide-semiconductor (CMOS) technology obviously approaches its physical limits, a need for its replacement with other materials such as GaAs and InGaAs for high mobility and scalable logic devices has emerged. However, large source/drain (S/D) spacing induced by annealing process to make ohmic contacts obstructed the scaling of III-V devices. Also, Fermi level pinning at metal/semiconductor interfaces caused by metal-induced gap states (MIGS) leads to high contact resistivity. Recently, to prevent the MIGS penetration into the semiconductor, the metal-interlayer-semiconductor (MIS) structure has been studied [1]. In addition, the heavily doped interlayer can reduce specific contact resistivity (ρ c ) more than undoped one, which has been experimentally demonstrated [2, 3]. Because it induce the effect of Schottky barrier lowering and the reduction of tunneling resistance. Although GaAs, a representative material of III-V semiconductors, is used in this study to confirm the effect of surface passivation and the MIS structure, other III-V semiconductors such as InGaAs and InAlAs can be applied to this proposed method. The surface of n-GaAs substrates, passivated by using the SF6 plasma, were prepared. Because the SF6 plasma treatment has the effect of S and F passivation simultaneously, the SF6 plasma treated samples exhibit better electrical performance than (NH4)2S solution passivated samples as shown in the Fig. 1. Figure 1 shows the I-V characteristics and the ρ c of the SF6-treated MIS contacts using a ZnO and an Aluminum-doped ZnO (AZO) as interlayers. The ZnO based interlayers have an advantage of low tunneling resistance due to its low conduction barrier offset (CBO) to GaAs, compared to other dielectric materials such as Al2O3, and SiN [4]. Also, the heavily doped ZnO, such as AZO, leads to more improve the electrical properties than those of undoped one because the thin ZnO depletion region, caused by aluminum doping, induces reduction of the tunneling resistance. In the Fig. 1(a), both current densities of the SF6-treated MIS contacts are higher than non-passivated, (NH4)2S-passivated, and SF6-treated metal-semiconductor (MS) contacts. And the AZO inserted MIS contact has more improvement of current densities than the ZnO inserted MIS contact. The ρ c ratio of the SF6-treated MIS contacts to the non-passivated MS contact are shown in the Fig. 1(b) and the Ti/AZO (2 nm)/SF6-treated n-GaAs (~2 × 1018 cm-3) contact exhibits the minimum ρ c which presents ~105 × reduction from the Ti/non-passivated n-GaAs contact. And also it exhibits 10 times lower than that of our previous work, the Ge-passivated MIS contact [5]. In this study, we have experimentally demonstrated the Fermi-level unpinning through the MIS structure by inserting an AZO interlayer. A ~105 × reduction in ρc is achieved in the Ti/AZO (2 nm)/SF6-treated n-GaAs contact compared to Ti/non-passivated n-GaAs. Therefore, this proposed MIS structure can be used as non-alloyed S/D ohmic contacts in beyond CMOS technology. [1] A. Agrawal et al., APL, 101, 042108 (2012). [2] G.-S. Kim et al., IEEE EDL, 35, 1076-1078 (2014). [3] S. Gupta et al., JAP, 113, 234505 (2013). [4] J. Hu et al., JAP, 107, 063712 (2010). [5] S.-H. Kim et al., IEEE EDL, 36, 884-886 (2015). Figure 1

Formation of Low-Resistivity Metal/Germanium Contact with Ultra-Thin Interlayer and Plasma Oxidation for n-Channel Germanium FET

Germanium (Ge) has emerged as a new channel material substituting traditional silicon (Si) in CMOS technology due to its high carrier mobility and process compatibility with Si. However, n-channel Ge MOSFET has not exhibited high performance because of some bottlenecks. High source/drain (S/D) contact resistance resulted from Fermi-level pinning (FLP) between the metal and Ge is the most serious obstacle for the development of Ge n-MOSFET. The metal/n-Ge contact has very large Schottky barrier height, approximately 0.55eV, regardless of metal work function because the Fermi-level on the metal side is strongly pinned to the edge of the valence band of Ge. Metal-induced gap states (MIGS) are the main cause of Fermi-level pinning, however, effect of interface states at the Ge surface on FLP is turned out to be not small by previous researches [1, 2]. Therefore, it is important to reduce both MIGS and interface states in order to alleviate FLP and form low-resistance Ge S/D contact. In this work, moderately-doped n-Ge wafer (N d = 1×1017 cm–3) was used as a substrate. In order to alleviate FLP of metal/n-Ge contact, 1.5 nm-thick ultra-thin TiO2 layer is inserted between the metal and n-Ge to block MIGS penetration into the energy gap of Ge, and plasma oxidation process is introduced before and after TiO2 deposition, respectively, to passivate Ge surface and reduce interface states [3]. Two approaches of plasma oxidation are applied; pre-oxidation and post-oxidation. The plasma oxidation process was carried out using ICP-RIE system. For pre-oxidation process, Ge substrate was oxidized prior to the TiO2 deposition with source power of 500 W, no bias power, gas flow of O2 40 sccm/Ar 5 sccm, pressure of 10 mTorr, and process time of 70 sec. For post-oxidation process, Ge substrate was oxidized after the TiO2 deposition with bias power of 50 W and process time of 30 sec with other plasma conditions not changed. The TiO2interlayer was deposited using atomic layer deposition (ALD) system at process temperature of 250 °C. As a result, a back-to-back reverse current density of Ti/TiO2/GeOx/n-Ge structure is improved compared to that of Ti/TiO2/n-Ge structure for both pre-oxidation and post-oxidation as shown in Fig. 1, which means Fermi-level on the metal side was more unpinned due to the GeOx passivation layer. It exhibits 4 orders of magnitude of reverse current improvement than the Ti/n-Ge structure does. Besides, the TiO2/GeOx stack shows better electrical properties than single TiO2 does when they have the same total thickness, approximately 2.1 nm (not shown here). It means an increase of single interlayer thickness in metal-interlayer-semiconductor (M-I-S) structure cannot be the best solution for FLP, and multi-layered structure should be introduced to reduce both MIGS and interface states. The Ti/TiO2/pre-GeOx/n-Ge shows slightly better performance than the Ti/TiO2/post-GeOx/n-Ge does. This is because the amount of GeOx formed by post-plasma oxidation process is smaller than that formed by pre-oxidation process due to the presence of TiO2 interlayer as shown in Fig. 2. Thicker GeOx can block MIGS more resulting in slight increase of reverse current density, however, GeOx layer formed by post-oxidation process has more GeO2-like characteristics which can passivate Ge surface better. For this reason, the Ti/TiO2/post-GeOx/n-Ge structure exhibits more ohmic-like (i.e., more linear) I–V characteristics, and post-oxidation process is considered to have more potential to plasma passivation process for the M-I-S structure. In conclusion, we successfully demonstrate the effect of pre- and post-oxidation process on Ge M-I-S structure. The GeOx layer formed by plasma oxidation between the metal and the TiO2 interlayer can reduce interface state density resulting in additional Fermi-level unpinning. Therefore, this plasma oxidation process with M-I-S structure can be a key technology to overcome the bottleneck of Ge n-channel MOSFET development by alleviating FLP effectively and reducing S/D contact resistance. [1] G.-S. Kim et al., IEEE Electron Device Lett., 36, 8 (2015) [2] J.-R. Wu et al., Appl. Phys. Lett., 99, 25 (2011) [3] J. Kang et al., Opt. Express, 23, 13 (2015) Figure 1

Non-Alloyed Ohmic Contacts on GaAs Using Metal-Interlayer-Semiconductor Structure With SF6Plasma Treatment

We demonstrate the effect of SF <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">6</sub> plasma passivation with a ZnO interlayer in a metal-interlayer-semiconductor (MIS) structure to reduce source/drain (S/D) contact resistance. The interface trap states and the metal-induced gap states causing the Fermi-level pinning problem are effectively alleviated by passivating the GaAs surface with SF <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">6</sub> plasma treatment and inserting a thin ZnO interlayer, respectively. Specific contact resistivity exhibits ~10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">4</sup> × reduction when the GaAs surface is treated with SF6 plasma, followed by ZnO interlayer deposition, compared with the Ti/n-GaAs (~2 × 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">18</sup> cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-3</sup> ) S/D contact. This result proposes the promising non-alloyed S/D ohmic contact for III-V semiconductor-based transistors.

Dark Current Suppression of Germanium Photodiode Using Metal-Interlayer-Semiconductor-Metal Structure with TiO2 interlayer

Germanium (Ge) photodetectors (PDs) are promising optoelectronics device for advanced Si photonics and optical interconnection due to excellent absorption property, near-infrared wavelengths, and process compatibility with Si-based complementary metal-oxide-semiconductor (CMOS). Ge metal-semiconductor-metal (MSM) PDs have many advantages over Ge PIN PDs in terms of low capacitance, high bandwidth, and process simplicity. However, Ge MSM PDs have large dark current because of a low hole barrier height induced by severe Fermi-level pinning between the metal and Ge, which results in poor sensitivity and large power consumption of PDs. In this work, the dark current of Ge MSM PD was tremendously reduced by introducing asymmetric metal-interlayer-semiconductor-metal (MISM) structure [Fig. 1]. As shown in Fig 2, a thin TiO2 layer was selected as the interlayer to reduce hole dark current by enhancing the hole Schottky barrier and the proposed structure can collect the photo current efficiently due to almost zero conduction band offset between TiO2 and Ge. Low p-type Ge wafer was used to minimize bulk defect current. To form MISM structure, TiO2 interlayer was deposited by atomic layer deposition (ALD) system at process temperature of 250 °C. To increase responsivity, finger-type PD was used with 10 um finger spacing and 10 um finger width. Metal-semiconductor (MS) contact region is defined by e-beam lithography and etched by 6:1 buffered HF, then metal-interlayer-semiconductor (MIS) contact region is defined by e-beam lithography. Cu contact was formed by e-beam evaporation and lift off process. As a result, MISM structure exhibits tremendous dark current reduction by approximately 4,000 times at a bias voltage of 1 V. The dark current reduces as the TiO2 thickness increases as shown in Fig. 3. In case of 1 nm-thick TiO2 interlayer the dark current is hardly reduced compared to symmetric MSM structure because most of holes can flow through 1 nm-thick TiO2 interlayer by tunneling. The hole dark current from the metal side diminishes as TiO2 thickness increases because hole tunneling probability decreases. The dark current with 3 nm-thick and 5 nm-thick TiO2 is reduced by 64 times and 3,970 times at 1 V, respectively, from symmetric MSM structure. As shown in Fig. 4, photo I-V measurement was carried out on asymmetric Ge MISM PD with 5 nm-thick TiO2 interlayer with collimated infrared laser (λ=1.55 um). Measured photo current value was 0.2 mA and it was saturated at 0.6 V, and the sensitivity of the PD was 24.52 at 1 V. In summary, we tremendously suppress dark current by approximately 4,000 times at 1 V using MISM structure. TiO2 interlayer of asymmetric MISM structure efficiently decrease hole dark current, and this structure can be promising structure for dark-current suppression in Ge MSM PD. Figure 1

The optical characterization of organometallic complex thin films by spectroscopic ellipsometry and photovoltaic diode application

In this work, organometallic complex (OMC) films have been deposited onto glass or silicon substrates by spin coating technique and their photovoltaic application potential has been investigated. Optical properties and thickness of the film have been investigated by spectroscopic ellipsometry (SE). Also, transmittance spectrum has been taken by UV/vis spectrophotometer. The optical method has been used to determine the band gap value of the films. Also, Au/OMC/n-Si metal/interlayer/semiconductor (MIS) diode has been fabricated. Current–voltage and photovoltaic properties of the structure were investigated. The ideality factor (n) and barrier height (Φb) values of the diode were found to be 2.89 and 0.79eV, respectively. The device shows photovoltaic behavior with a maximum open-circuit voltage of 396mV and a short circuit current of 33.8μA under 300W light.

Effect of Hydrogen Annealing on Contact Resistance Reduction of Metal–Interlayer–n-Germanium Source/Drain Structure

The effect of post-deposition H2 annealing (PDHA) on the reduction of a contact resistance by the metal–interlayer–semiconductor (M–I–S) source/drain (S/D) structure of the germanium (Ge) n-channel field-effect transistor (FET) is demonstrated in this letter. The M–I–S structure reduces the contact resistance of the metal/n-type Ge (n-Ge) contact by alleviating the Fermi-level pinning (FLP). In addition, the PDHA induces interlayer doping and interface controlling effects that result in a reduction of the tunneling resistance and the series resistance regarding the interlayer and an alleviation of the FLP, respectively. A specific contact resistivity ( $\rho _{c})$ of $3.4\times 10^{-4} \Omega \cdot \text {cm}^{2}$ was achieved on a moderately doped n-Ge substrate ( $1\times 10^{17}$ cm $^{-3})$ , whereby $5900\times $ reduction was exhibited from the Ti/n-Ge structure, and a $10\times $ reduction was achieved from the Ti/Ar plasma-treated TiO2– x /n-Ge structure. The PDHA technique is, therefore, presented as a promising S/D contact technique for the development of the Ge n-channel FET, as it can further lower the contact resistance of the M–I–S structure.

Fermi-Level Unpinning Using a Ge-Passivated Metal–Interlayer–Semiconductor Structure for Non-Alloyed Ohmic Contact of High-Electron-Mobility Transistors

We demonstrate the use of germanium passivation in conjunction with a ZnO interlayer in a metal-interlayer- semiconductor structure in a source/drain (S/D) contact. The Fermi-level pinning problem resulting in the large contact resistances in S/D contacts is effectively alleviated by inserting a thin Ge passivation layer and a ZnO interlayer, passivating the GaAs surface and reducing the metal-induced gap states on the GaAs surface, respectively. The specific contact resistivity for the Ti/ZnO/Ge/n-GaAs (~2 × 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">18</sup> cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-3</sup> ) structure exhibits a ~1660× reduction compared with that of a Ti/n-GaAs structure. These results suggest that the proposed structure shows promise as a nonalloyed ohmic contact in high-electron-mobility transistors.

Electrical characterization of metal/diamond-like carbon/inorganic semiconductor MIS Schottky barrier diodes

In this study, electrodeposited diamond-like carbon (DLC) film was used to fabricate 12 identical Au/DLC/p-Si metal–interlayer–semiconductor (MIS) Schottky diodes. Current–voltage (I–V) measurements were carried out to obtain diodes' parameters. The rectification ratios of the MIS diodes were found between 103 and 104. By using the forward bias I–V characteristics, the average ideality factor (n) and barrier height (Φb) values of Au/DLC/p-Si MIS structures were found as 2.06 and 0.84eV, respectively. The Φb value of 0.84eV obtained for Au/DLC/p-Si MIS diode was much higher than the value of 0.34 of conventional Au/p-Si Schottky diode. Cheung–Cheung functions were also used to extract barrier height and series resistance values and the obtained results were compared with I–V method. I–V measurements were also carried out under the hydrostatic pressure in the range of 0.0–2.0kbar. It was found that barrier height and series resistance values were highly pressure sensitive and increased with the ascending pressure. It was proposed that Au/DLC/p-Si Schottky MIS diode can be used as pressure sensor due to high sensitivity to changing pressure.

Electrical characterization of a pre-ceramic polymer modified Ag/poly(hydridocarbyne)/p-Si Schottky barrier diode

In this study, poly(hydridocarbyne) (PHC), a pre-ceramic polymer that can be converted to ceramic upon heating, was used to fabricate Ag/PHC/p-Si metal-interlayer-semiconductor (MIS) diode. The diode obtained by easy processing steps presented a good rectifying behavior and a sufficient reverse bias saturation. By using the forward bias I–V characteristics, the ideality factor (n) and barrier height (Φb) of Ag/PHC/p-Si MIS structure were found as 1.93 and 0.94 eV, respectively. The non-ideal I–V behavior with the value of ideality factor greater than unity was attributed to series resistance. The Φb value of 0.94 eV obtained for Ag/PHC/p-Si MIS diode was larger than value of 0.84 of conventional Ag/p-Si Schottky diode. This was ascribed to PHC interlayer influencing the space-charge region of Si. The interface state density of MIS diode was determined, and it was found that the interface state density of Ag/p-Si junction significantly changed by PHC organic layer inserted into metal and semiconductor. Furthermore, Cheung’s and Norde’s functions were used to extract barrier height and series resistance values, and the obtained results were compared.

Electrical analysis of organic dye-based MIS Schottky contacts

In this work, we prepared metal/interlayer/semiconductor (MIS) diodes by coating of an organic film on p-Si substrate. Metal(Al)/interlayer(Orange G OG)/semiconductor( p-Si) MIS structure had a good rectifying behavior. By using the forward-bias I– V characteristics, the values of ideality factor ( n) and barrier height (BH) for the Al/OG/ p-Si MIS diode were obtained as 1.73 and 0.77 eV, respectively. It was seen that the BH value of 0.77 eV calculated for the Al/OG/ p-Si MIS diode was significantly larger than the value of 0.50 eV of conventional Al/ p-Si Schottky diodes. Modification of the potential barrier of Al/ p-Si diode was achieved by using thin interlayer of the OG organic material. This was attributed to the fact that the OG organic interlayer increased the effective barrier height by influencing the space charge region of Si. The interface-state density of the MIS diode was found to vary from 2.79 × 10 13 to 5.80 × 10 12 eV −1 cm −2.

Silicon MIS diodes with Cr 2O 3 nanofilm: Optical, morphological/structural and electronic transport properties

In this work we report the optical, morphological and structural characterization and diode application of Cr 2O 3 nanofilms grown on p-Si substrates by spin coating and annealing process. X-ray diffraction (XRD), non-contact mode atomic force microscopy (NC-AFM), ultraviolet–visible (UV–vis) spectroscopy and photoluminescence (PL) spectroscopy were used for characterization of nanofilms. For Cr 2O 3 nanofilms, the average particle size determined from XRD and NC-AFM measurements was approximately 70 nm. Structure analyses of nanofilms demonstrate that the single phase Cr 2O 3 on silicon substrate is of high a crystalline structure with a dominant in hexagonal (1 1 0) orientation. The morphologic analysis of the films indicates that the films formed from hexagonal nanoparticles are with low roughness and uniform. UV–vis absorption measurements indicate that the band gap of the Cr 2O 3 film is 3.08 eV. The PL measurement shows that the Cr 2O 3 nanofilm has a strong and narrow ultraviolet emission, which facilitates potential applications in future photoelectric nanodevices. Au/Cr 2O 3/p-Si metal/interlayer/semiconductor (MIS) diodes were fabricated for investigation of the electronic properties such as current–voltage and capacitance–voltage. Ideality factor and barrier height for Au//Cr 2O 3/p-Si diode were calculated as 2.15 eV and 0.74 eV, respectively. Also, interfacial state properties of the MIS diode were determined. The interface-state density of the MIS diode was found to vary from 2.90 × 10 13 eV −1 cm −2 to 8.45 × 10 12 eV −1 cm −2.

Electrical analysis of organic interlayer based metal/interlayer/semiconductor diode structures

In this work, metal/interlayer/semiconductor (MIS) diodes formed by coating of an organic film to p-Si semiconductor substrate were prepared. Metal(Al)/interlayer (phenolsulfonphthalein=PSP)/semiconductor(p-Si) MIS device had a good rectifying behavior. By using the forward bias I-V characteristics, the values of ideality factor (n) and barrier height (Φb) for the Al/PSP/p-Si MIS diode were obtained as 1.45 and 0.81 eV, respectively. It was seen that the Φb value of 0.81 eV calculated for the Al/PSP/p-Si MIS diode was significantly larger than value of 0.50 eV of conventional Al/p-Si Schottky diodes. Modification of the interfacial potential barrier of Al/p-Si diode was achieved by using a thin interlayer of the PSP organic material. This has been attributed to the fact that the PSP organic interlayer increases the effective barrier height by influencing the space-charge region of Si. The interface-state density of the MIS diode was determined, and the interface-state density was found to vary from 3.00×1013 to 2.99×1012 eV−1 cm−2.