Metal Interconnect Layers Research Articles

Effect of Fe on the oxidation behavior, electrical properties and microstructure of Co[sbnd]Ni protective coatings for metal interconnect layers in solid oxide fuel cells

CoNi and 5% Fe doping CoNi alloy coatings are prepared on SUS 430 substrates as interconnect protect layers for solid oxide fuel cells by electroplating. The electrical characteristics and oxidation resistance of interconnects are enhanced by the alloy coatings after they are oxidized in air at 800 °C for 1000 h and the Co-Ni-Fe alloy coatings showing the better effect. Cr is unable to diffuse outward owing to the multi-layer oxidation structure. Addition of Fe to CoNi alloy coatings leads to the formation of a (Fe,Co,Ni)3O4 spinel layer with lower activation energy and stronger ability to restrict oxygen diffusion inward.

Development of Wafer Level Package Platform for High Reliability Crossover MCUs

Fan in and fan out wafer level packages are primarily used in the industry for applications in handheld consumer electronic products. The key benefits of wafer level package (WLP) are small form factor, reduced cost, improved electrical and thermal performance. WLP investigated in this study are directly surface mounted on PCB and have no intermediate substrate. Direct mount of package on PCB, leads to significant CTE mismatch between the package and board which stresses the package solder joint, leading to cyclic fatigue induced solder joint cracking. To overcome the solder joint cracking, stiffer solder alloys have been evaluated. However, higher stiffness of the solder alloy shifts the cyclic stress induced failure, from the solder joint to the package metal interconnect layers. Moreover, WLP on advanced silicon node have fragile low-k and extremely low-k back end of line dielectric layers that also crack or delaminate in cyclic fatigue. In this work extensive WLP platform development has been done with following DOE variables; multi-layer package routing, dielectric materials, solder alloys, solder ball pitch and diameter. Developed packages passed and outperformed the following product reliability qualification conditions: high temperature storage life (150°C, 2000 hours), highly accelerated stress test (110°C / 85%RH / Bias, 528 hours), application level temperature cycling ((-40 °C to 125 °C, 600 cycles), board level temperature cycling (-40 °C to 125 °C, 500 cycles) and board level drop test (1500g/0.5ms, 30 drops). Excellent reliability, functional performance, and successful chip package integration was achieved for WLP for crossover MCU products.

Visible and Near-IR Nano-Optical Components and Systems in CMOS

Integration of complex optical systems operating in the visible and near-IR range, realized in a CMOS fabrication process with an absolutely ‘no change’ approach, can have a transformative impact in enabling a new class of miniaturized, low-cost, smart optical sensors and imagers for emerging applications. While ‘silicon photonics’ has demonstrated the path towards such advancements in the IR regime, the field of VIS/NIR integrated optics has seen less progress. Therefore, while currently ultra high-density and higher performance image sensors are commonplace in CMOS, all passive optical components (such as lenses, filters, gratings, collimators) that typically constitute a high-performance sensing or imaging system, are typically non-integrated, bulky and expensive, severely limiting their application potential in the space of connected sensors. Here, we present an approach to utilize the embedded copper-based metal interconnect layers in modern CMOS processes with sub-wavelength feature sizes to realize multi-functional nano-optical structures and components. Based on our prior works, we illustrate this electronic-photonic co-design approach exploiting metal/light interactions and integrated electronics in the 400nm-900 nm wavelengths with three design examples. Realized in 65-nm CMOS, these demonstrate for the first time: fully integrated multiplied fluorescence based biosensors with integrated filters, optical spectrometer, and CMOS optical physically unclonable function (PUF). These examples cover a range of optical processing elements in silicon, from deep sub-wavelength nano-optics to diffractive structures. We will demonstrate that when co-designed with embedded photo-detection and signal processing circuitry, this approach can foster millimeter-scale, intelligent optical sensors for a wide range of emerging applications in healthcare, diagnostics, smart sensing, food, air quality, environment monitoring and others.

Notched Anchor Design for Low Voltage Operation of Nanoelectromechanical (NEM) Memory Switches.

Because nanoelectromechanical (NEM) memory switches generally have higher pull-in voltage (VPI) and lower reliability than CMOS devices, reducing VPI and maximum stress (σMAX) of NEM memory switches have been critical issues for the implementation of monolithic-3D (M3D) CMOS-NEM hybrid reconfigurable logic (RL) circuits. In this paper, a novel notched anchor design is proposed to reduce the VPI and σMAX of NEM memory switches. Moreover, the novel design has an advantage in terms of chip density over the conventional design under the same VPI condition. In the case of our proposed NEM memory switches, their anchors are placed in the vias of metal interconnection layers. Thus, even if notched patterns are formed on the anchors, it will be helpful to effectively increase beam length, which eventually lowers VPI and σMAX. In this manuscript, the proposed notched anchor design has been confirmed by finite-element-method (FEM) simulation. According to the simulation results, the proposed notched anchor design lowers VPI by ~23% and σMAX by ~24%.

Encapsulation of NEM Memory Switches for Monolithic-Three-Dimensional (M3D) CMOS⁻NEM Hybrid Circuits.

Considering the isotropic release process of nanoelectromechanical systems (NEMSs), defining the active region of NEM memory switches is one of the most challenging process technologies for the implementation of monolithic-three-dimensional (M3D) CMOS–NEM hybrid circuits. In this paper, we propose a novel encapsulation method of NEM memory switches. It uses alumina (Al2O3) passivation layers which are fully compatible with the CMOS baseline process. The Al2O3 bottom passivation layer can protect intermetal dielectric (IMD) and metal interconnection layers from the vapor hydrogen fluoride (HF) etching process. Thus, the controllable formation of the cavity for the mechanical movement of NEM devices can be achieved without causing any damage to CMOS baseline circuits as well as metal interconnection lines. As a result, NEM memory switches can be located in any place and metal layer of an M3D CMOS–NEM hybrid chip, which makes circuit design easier and more volume efficient. The feasibility of our proposed method is verified based on experimental results.

Fully Integrated Optical Spectrometer in Visible and Near-IR in CMOS.

Optical spectrometry in the visible and near-infrared range has a wide range of applications in healthcare, sensing, imaging, and diagnostics. This paper presents the first fully integrated optical spectrometer in standard bulk CMOS process without custom fabrication, postprocessing, or any external optical passive structure such as lenses, gratings, collimators, or mirrors. The architecture exploits metal interconnect layers available in CMOS processes with subwavelength feature sizes to guide, manipulate, control, diffract light, integrated photodetector, and read-out circuitry to detect dispersed light, and then back-end signal processing for robust spectral estimation. The chip, realized in bulk 65-nm low power-CMOS process, measures 0.64 mm 0.56 mm in active area, and achieves 1.4nm in peak detection accuracy for continuous wave excitations between 500 and 830nm. This paper demonstrates the ability to use these metal-optic nanostructures to miniaturize complex optical instrumentation into a new class of optics-free CMOS-based systems-on-chip in the visible and near-IR for various sensing and imaging applications.

CMOS micro-heater design for direct integration of carbon nanotubes

Carbon nanotubes (CNTs) are nanomaterials that exhibit many remarkable electrical, mechanical and thermal properties, which can be exploited in various smart sensing applications by integrating them in standard CMOS processes. However, such integration technique is challenging since CMOS does not tolerate high temperatures required for local CNT synthesis. This work involves designing power efficient CMOS micro-heaters that can generate CNT growth temperature (~900°C) in a post-CMOS CNT fabrication step, while maintaining CMOS compatible temperature (<300°C) in the microsystem. One suitable metal interconnect layer and a polysilicon layer available in AMS 0.18μm CMOS technology have been used to design and simulate the micro-heaters. This paper proposes and compares six different optimal micro-heater designs alongside their thermal and thermomechanical analysis using multiphysics simulation software, ANSYS. Feasibility of implementing the designed micro-heaters in a real chip is discussed based on the analysis. Required CMOS post processing steps for the designed micro-heaters are also discussed. The promising results are expected to lead the way for successful implementation of carbon nanotube based sensors in a commercial CMOS process.

A 28 nm Embedded Split-Gate MONOS (SG-MONOS) Flash Macro for Automotive Achieving 6.4 GB/s Read Throughput by 200 MHz No-Wait Read Operation and 2.0 MB/s Write Throughput at Tj of 170C

First-ever 28 nm embedded split-gate MONOS (SG-MONOS) flash macros have been developed to increase memory capacity embedded in micro controller units and to improve performance over wide junction temperature range from $-40^{\circ}{\hbox {C}}$ to 170 $^{\circ}{\hbox {C}}$ as demanded strongly in automotive uses. Much attention has been paid to the degradation of the reliability characteristics along with the process shrinkage. Temperature-adjusted word-line overdrive scheme improves random read access frequency by 15% and realizes both of 6.4 GB/s read throughput by 200 MHz no-wait random access of code flash macros and more than ten times longer TDDB lifetime of WL drivers. Temperature-adaptive step pulse erase control (TASPEC) improves the TDDB lifetime of dielectric films between metal interconnect layers by three times. TASPEC is particularly useful for a data flash macro with one million rewrite cycles. Source-side injection (SSI) program with negative back-bias voltage achieves 63% reduction of program pulse time and, consequently, realizes 2.0 MB/s write throughput of code flash macros. A spread spectrum clock generation and a clock phase shift technique are introduced for charge pump clock generation in order to suppress EMI noise due to high write throughput of code flash macros, and peak power of EMI noise is reduced by 19 dB.

An Uncooled Infrared Microbolometer Array for Low-Cost Applications

This letter describes the implementation of a low-cost $32\times 32$ uncooled infrared microbolometer array using a standard 0.5- $\mu \text{m}$ CMOS process and a surface sacrificial layer technique, in which the CMOS metal interconnection layers are used as the infrared sensitive material. The sacrificial layer embedded during the CMOS fabrication can be etched using a simple wet etching process following the CMOS processes, without the need for any lithography or material deposition steps. The CMOS metal interconnect layers are aluminum, with a temperature coefficient of resistance of 0.398%/K. The 32 $\times $ 32 focal plane array (FPA) has a pixel size of 65 $\mu {\rm m}\times 65~\mu \text{m}$ and a fill factor of 29%. The thermal conductance of the FPA was measured to be $3.47\times 10^{-6}$ W/K, with a thermal time of 3.85 ms, and a dc responsivity of 1050 V/W at a 10-Hz chopper frequency. The total measured rms noise of the microbolometer is 0.706 $\mu \text{V}$ for a 10-kHz bandwidth, resulting in a detectivity of $5.2\times 10^{8}$ cmHz $^{1/2}$ /W.

Ion traps fabricated in a CMOS foundry

We demonstrate trapping in a surface-electrode ion trap fabricated in a 90-nm CMOS (complementary metal-oxide-semiconductor) foundry process utilizing the top metal layer of the process for the trap electrodes. The process includes doped active regions and metal interconnect layers, allowing for co-fabrication of standard CMOS circuitry as well as devices for optical control and measurement. With one of the interconnect layers defining a ground plane between the trap electrode layer and the p-type doped silicon substrate, ion loading is robust and trapping is stable. We measure a motional heating rate comparable to those seen in surface-electrode traps of similar size. This demonstration of scalable quantum computing hardware utilizing a commercial CMOS process opens the door to integration and co-fabrication of electronics and photonics for large-scale quantum processing in trapped-ion arrays.

Fully printed electronics on flexible substrates: High gain amplifiers and DAC

We propose a novel simple Fully-Additive printing process, involving only depositions, for realizing printed electronics circuits/systems on flexible plastic films. This process is Green (non-corrosive chemicals), On-Demand (quick-to-print), Scalable (large-format printing) and Low-Cost vis-à-vis Subtractive printing, a complex deposition-cum-etching process that otherwise requires expensive/sophisticated specialized IC-like facilities and is Un-Green, Not-On-Demand, Un-scalable and High-Cost. The proposed Fully-Additive process features printed transistors with high (∼1.5cm2/Vs) semiconductor carrier-mobility, ∼3× higher than competing state-of-the-art Fully-Additive processes and comparable to Subtractive processes. Furthermore, passive elements including capacitors, resistors, and inductors, and two metal-interconnect layers are likewise Fully-Additive printed–to our knowledge, to-date the only Fully-Additive process capable of realizing complex circuits/systems on flexible plastic films.Several analog and mixed-signal circuits are demonstrated, including proposed and conventional differential amplifiers, and a charge-redistribution 4-bit digital-to-analog converter (DAC). The proposed amplifier embodies a novel positive-cum-negative feedback to simultaneously significantly improve the gain and reduce susceptibility to process variations. To improve the speed and reduce the area of the DAC, the parasitic capacitors therein are exploited. The Fully-Additive proposed amplifier and DAC are benchmarked against reported realizations (all Subtractive-based processes), and are shown to be highly competitive despite its realization based on the simple low-cost proposed Fully-Additive process.

A Test Circuit for Statistical Evaluation of $p-n$ Junction Leakage Current and its Noise

We develop a test circuit to evaluate statistical distributions of p-n junction leakage currents for numerous samples in a very short time (0.1-10 fA, 28672 n+-p diodes in 0.77s). This test circuit is based on a complementary metal-oxide-semiconductor active pixel image sensor, which contains a current-to-voltage conversion function by a capacitor and amplifiers of voltage signals in each pixel. The test structure can be easily designed because of a small number of mask layer requirements (at least one poly-Si, one metal interconnect layer). Its simplicity has considerable benefits, such as an easy fabrication for the evaluation of various processes technologies without exceptional cares. We demonstrate that two normal distributions exist in the steady-state (time averaging) Ileak distributions, which have differing temperature dependencies. A distribution of the activation energy extracted from temperature dependence of Ileak is also revealed experimentally. Dynamic fluctuation of Ileak is confirmed to be measured, due to the execute pseudoparallel sampling among whole samples over a long recording time.

A Light-Field Image Sensor in 180 nm CMOS

This paper presents a CMOS image sensor which captures local incident angle and intensity information from the light it records. The 400×384 pixel array employs 7.5 μm angle-sensitive pixels, which use pairs of local diffraction gratings above a photodiode to detect incident angle. The gratings are implemented with the metal interconnect layers of CMOS manufacturing technology and therefore require no post-processing or external optics. Fabricated in a 180 nm mixed-mode CMOS process, the sensor requires only a single lens to create a light-field image. Using the information contained in a single image, we demonstrate range finding with 2.5 mm precision at 1 m and post-capture refocus on complex visual scenes.

Localized Growth of Carbon Nanotubes on CMOS Substrate at Room Temperature Using Maskless Post-CMOS Processing

Carbon nanotubes (CNTs) have been successfully synthesized on foundry CMOS substrate using maskless post-CMOS surface micromachining and localized heating techniques. The integrated heater is directly made of gate polysilicon and suspended over a micromachined cavity for thermal isolation. The synthesized CNTs are connected to CMOS interconnect metal layers without the need of any metal deposition. It is experimentally verified that the electrical properties of the neighboring CMOS transistors are unchanged after CNT growth.

Development of spin-on-glass process for triple metal interconnects

Spin-on-glass (SOG), an interlayer dielectric material applied in liquid form to fill narrow gaps in the sub-dielectric surface and thus conducive to planarization, is an alternative to silicon dioxide (SiO2) deposited using PECVD processes. However, its inability to adhere to metal and problems such as cracking prevent the easy application of SOG technology to provide an interlayer dielectric in multilevel metal interconnect circuits, particularly in university processing labs. This paper will show that a thin layer of CVD SiO2 and a curing temperature below the sintering temperature of the metal interconnect layer will promote adhesion, reduce gaps, and prevent cracking. Electron scanning microscope analysis has been used to demonstrate the success of the improved technique. This optimized process has been used in batches of double-poly, triple-metal CMOS wafer fabrication to date.

Performance improvement of the EEPROM cells with the standard logic process featuring a metal finger coupling capacitor

In this paper, a novel single-poly electrically erasable programmable read-only memory (EEPROM) using a metal finger coupling capacitor is proposed and fabricated with a pure logic CMOS process. The metal interconnect layer is applied to form the finger-type capacitor which can be used as the coupling capacitor in the EEPROM cell. Using the metal finger capacitor, the proposed cell exhibits the advantages of a metallic control gate and features a higher coupling ratio to achieve smaller cell area and lower program/erase voltage. The program/erase characteristics, endurance and retention performances are presented. In addition, the EEPROM cell with a stacked metal finger structure can further improve the coupling ratio. Thus, lower operation voltage can be obtained without increasing the cell area.

Logic circuits based on individual semiconducting and metallic carbon-nanotubedevices

Nanoscale transistors employing an individual semiconducting carbon nanotube as thechannel hold great potential for logic circuits with large integration densities that can bemanufactured on glass or plastic substrates. Carbon nanotubes are usually produced as amixture of semiconducting and metallic nanotubes. Since only semiconductingnanotubes yield transistors, the metallic nanotubes are typically not utilized.However, integrated circuits often require not only transistors, but also resistiveload devices. Here we show that many of the metallic carbon nanotubes thatare deposited on the substrate along with the semiconducting nanotubes can beconveniently utilized as load resistors with favorable characteristics for the design ofintegrated circuits. We also demonstrate the fabrication of arrays of transistorsand resistors, each based on an individual semiconducting or metallic carbonnanotube, and their integration on glass substrates into logic circuits with switchingfrequencies of up to 500 kHz using a custom-designed metal interconnect layer.

RF-MEMS switching devices using vertical comb-drive actuation in the CMOS process

Radio frequency micro-electro-mechanical system (RF-MEMS) switching devices using vertical comb-drive actuation toward low-voltage actuation, fast response are presented in this paper. The switching devices, which comprise comb-drive electrodes, are actuated entirely by the electrostatic forces applied not only for the down-state but also for the up-state. The cost-effective MEMS process compatible with the complementary metal oxide semiconductor (CMOS) process is presented in this paper as well. The fabrication process is composed by adapting the CMOS 0.18 µm back end of line (BEOL) process on 200 mm wafers. The MEMS process in the CMOS process enables the realization of passive devices integrated with active devices, which is effective for size and cost reduction. Two metal interconnection layers in the BEOL process are used for the MEMS process. Interconnection aluminum and inter-layer dielectric tetraethoxysilane (TEOS) are used as MEMS structural material and sacrificial material, respectively. The chemical mechanical polishing (CMP) process is implemented to planarize the sacrificial material surface. The structures were fabricated using a simple low-cost two-mask process. The characteristics of switching capacitors, C-V, RF performance, switching speed and continuous drive cycles are measured on the fabricated devices. The capacitance ratio for the down-state/up-state is Cdown/Cup = 5.4. The characteristics of switching speed response/actuation voltage in the down-state and up-state are 4.5 µs/5 V and 8.0 µs/5 V, respectively. The switching speed is stable up to 107 cycles in spite of the fact that the unipolar voltage speed is stable up to 107 cycles.

Capacitive RF MEMS Switches Fabricated in Standard 0.35-$\mu{\hbox{m}}$ CMOS Technology

The objective of this paper is to investigate the integration of capacitive type RF microelectromechanical systems (MEMS) switches in a standard CMOS technology. A maskless monolithic integration process dedicated to electrostatically actuated capacitive type RF MEMS switches is developed and optimized. The fabricated switches consist of composite metal-dielectric warped membranes. The warped-plate structure is used to increase the capacitance ratio of the switch. The switches are fabricated using the interconnect metal and dielectric layers available in a standard 0.35-μm CMOS process. Measurement results for the first switch show an insertion loss less than 0.98 dB, a return loss below 13 dB up to 20 GHz in the up-state, and a down-state isolation of 12.4-17.9 dB from 10 to 20 GHz. The capacitance ratio is enhanced up to 91:1 using the warped-plate structure. A second cascaded switch consisting of two shunt capacitive switches and a slow-wave high-impedance transmission line section is designed and fabricated for high-isolation applications. The measured insertion loss for this switch is less than 1.41 dB up to 20 GHz, the return loss is below 19 dB, and the isolation is 19-40 dB across the frequency band from 10 to 20 GHz. The proposed RF MEMS switches can be used in millimeter-wave CMOS RF front-ends where multiband functionality and reconfigurability is required.

Fully differential CMOS-MEMS &lt;inline-formula&gt;&lt;math display="inline" overflow="scroll"&gt;&lt;mi&gt;z&lt;/mi&gt;&lt;/math&gt;&lt;/inline-formula&gt;-axis accelerometer with torsional structures and planar comb fingers

Fully differential z-axis acceleration sensing often requires complicated multiwafer bonding processes. We present an integrated fully differential complementary metal-oxide semiconductor-microelectromechanical systems (CMOS-MEMS) z-axis accelerometer utilizing planar comb fingers and a pair of single-crystal silicon (SCS) torsional springs. The sidewall capacitors formed by multiple CMOS interconnect metal layers are exploited for fully differential displacement sensing with a common-centroid wiring configuration. Single crystal silicon is used throughout the device to form robust microstructures. A deep reactive ion etching (DRIE)-based microfabrication process with large processing tolerance has been developed to allow monolithic integration of CMOS circuitry with sensor structures and high fabrication yield. With an on-chip low-power, low-noise, dual-chopper amplifier that has a measured 44.5-dB gain and 1-mW power consumption, the fabricated integrated z-axis accelerometer demonstrates a sensitivity of 250 mV/g and an overall noise floor of 110 µg/Hz.