MOSFET Research Articles

Design of CMOS low noise amplifier with inductive degeneration for navigation application

Abstract This paper presents an advanced Low Noise Amplifier (LNA) tailored for high-precision navigation applications, designed using the 180nm technology node and implemented in Cadence Virtuoso. The LNA features a single-ended amplifier configuration with cascaded NMOS transistors to achieve superior isolation and input matching through source degeneration, optimizing gain and noise performance. At 1.2 GHz, the amplifier achieves a gain of 33 dB and a noise figure of 1.3 dB. It demonstrates a 1 dB compression point of –16 dBm and a third-order intercept point (IIP3) of –10 dBm, with a power consumption of 44 mW from a 1.8 V supply. Post-layout simulations reflect a noise figure of 2.9 dB and a gain of 19.5 dB, highlighting practical design considerations. The layout area is 0.51 mm², underscoring the compact yet highly efficient design.

A breathable, waterproof and battery-free wearable e-nose with high flexibility based on MEMS gas sensors for accurate identification of volatile aromatic hydrocarbons

Benzene, toluene, ethylbenzene, xylene, and styrene (BTEXS) are harmful gases indoors and in the cabin. Electronic nose (e-nose) technology has shown great potential in detecting BTEXS. However, to maintain the normal operation of the e-nose and improve the recognition accuracy, it often employs a large array of metal oxide semiconductor (MOS) gas sensors, along with extensive signal processing circuits and high-power solid-state batteries. The bulky structure makes it difficult for the e-nose to realize the portable real-time detection of BTEXS. Herein, a breathable, waterproof, battery-free, and highly flexible wearable e-nose (BWBFW e-nose) is fabricated for BTEXS detections. In detail, we first prepare a combination scheme of n-type and p-type MOS for forming four MEMS gas sensors, exhibiting differentiated response characteristics. Subsequently, a wireless supply module and a wireless signal processing module are designed on a flexible porous circuit board. Then, a waterproof and breathable membrane by electrospinning was adopted to encapsulate the flexible circuit board, endowing the e-nose with high safety. Finally, accurate identification and low-error concentration prediction of BTEXS are achieved with the help of a 1D Convolutional Neural Network (1DCNN) algorithm. We believe the e-nose reported here will shed new light on the design of new devices for detecting BTEXS.

A 0.7‐V 7.4‐nW 6.4‐ppm/°C CMOS Subthreshold Voltage Reference With Temperature Compensation Circuit

ABSTRACTThis paper proposes a nanowatt voltage reference (VR) with temperature coefficient compensation. All transistors work in the subthreshold region. The complementary‐to‐absolute‐temperature (CTAT) voltage and proportional‐to‐absolute‐temperature (PTAT) voltage are mainly generated by two NMOS transistors with different threshold voltages. At the same time, a simple temperature compensation circuit is designed to optimize the temperature coefficient at high temperatures, so that the proposed VR circuit can generate a reference voltage with a wider temperature range and a lower temperature coefficient. The proposed VR circuit is implemented using a standard 0.18‐μm CMOS process with an active area of only 0.022 mm2. The postlayout simulation results show that the proposed VR circuit generates a reference voltage of 308.21 mV at room temperature. Its temperature coefficient is 6.4 ppm/°C over a temperature range of −40°C°C–140°C, with a power consumption of 7.4 nW. The voltage line sensitivity (LS) is 0.098%/V, and the power supply ripple rejection (PSRR) is −72 dB @DC and −42 dB @10 MHz.

Engineered Gate-Based Nanoscaled JK Flip-Flop: Design, Simulation and Applications

In this paper, we design and simulate a novel, highly compact and power-efficient silicon-based JK flip-flop (JKFF) employing an engineered gate technique, for the first time. Herein, the pull-down and the pull-up paths used to realize the JKFF have been realized by 4 and 2 engineered gate transistors, respectively (total six), whereas 8 pull-ups and 8 pull-down (total 16) transistors are used to realize the JK flip-flip in the conventional MOS technology. Two-dimensional (2D) calibrated mixed-mode simulations have revealed substantial improvement in various performance measuring parameters of the proposed JK flip-flop. The proposed technique has resulted in a significant reduction of 62.5% in transistor count, [Formula: see text]9.12% in power consumption, 2.5% decrease in delay and 11.38% in power delay product in comparison to the conventional JKFF realization. Further, the proposed gate-engineered JKFF has been used to realize highly compact D and T flip-flops. It has been observed that a 55.5% and 62.5% decrease in transistor count have been achieved in comparison to the conventional MOS-based JKFF realization of D and T flip-flops, respectively. A significant improvement in power consumption, delay, and power delay products has been achieved in the proposed D and T flip-flops in comparison to the conventional JKFF-based D and T flips. It has been observed that notably, the versatility of this approach allows for straightforward adaptation to realize various other sequential and combinational circuits. Besides, the process flow for the fabrication of the proposed engineered gate transistors for realizing the JKFF, D and T flip-flops has also been given.

Machine Learning‐Driven Extraction of Hybrid Compact Models Integrating Neural Networks and Berkeley Short‐Channel Insulated‐Gate Field‐Effect Transistor Model‐Common Multigate for Multidevice Applications

Conventional techniques for extracting physics‐based model parameters are inherently slow processes and often yield less accurate model parameters because of the inflexibility of physical equations. This study presents a novel machine learning–based method to accelerate and enhance the accuracy of compact model generation for multiple devices simultaneously. By integrating a Berkeley short‐channel Insulated‐Gate Field‐Effect Transistor (IGFET) model‐common multigate (BSIM) model with an error‐correction neural network, the proposed approach refines predictions for critical electrical behaviors such as drain current and gate capacitance. Extraction networks dynamically optimize parameter sets for both models, eliminating manual tuning and reducing the need for separate training for each device. The method was validated using TCAD‐simulated 3 nm nanosheet field‐effect transistors devices, achieving a mean absolute percentage error of 1.8% for drain current, 2.8% for transconductance, 8.5% for output conductance, and 0.4% for capacitances. Compared with the BSIM model alone, error reductions of 75, 70, 39, 85, and 81%, respectively, were achieved. This approach showed significant error reductions compared to the BSIM model alone and demonstrated robust performance across devices with variations, proving its effectiveness for large‐scale applications.

Design of Cascode Current Mirror Using CMOS Technology for Low Power Application

Background: Many applications, including biological applications, require a very high output impedance current mirror because they run at very low voltages. The circuit known as the current mirror applies the idea that two identical MOS transistors with the same gate-source voltage will have equal channel currents flowing through them. Objective: The objective of this study is to optimize the design to minimize power consumption while maintaining accurate current mirroring, which is crucial for low-power and energy-efficient electronic systems. Methods: This study is performed in Cadence Virtuoso using the gdpk45 technology node to construct a cascode current mirror, comparing simulation findings to other contemporary mirrors. Results: A significant improvement in power usage is shown compared to other current mirrors, and a small signal model analysis of the circuit, the design, and its mathematical model is investigated. Conclusion: Compared to the circuits that were previously designed, the output resistance values are substantially greater. The cascode current mirror that is suggested in this paper uses 48 μW of electricity, while the other cascode current mirror uses 74.186 μW.

16-nW 0.5-V low-pass filter for bio-signal applications

A low-voltage, ultra-low power fully differential low-pass filter for bio-signal applications using multiple-input fully differential operational transconductance amplifiers (OTA) is presented in this article. The multiple inputs of OTA can be achieved using multiple-input dynamic threshold MOS transistor (MIDT-MOST) technique. The novelty of this work is to exhibit the proposed filter using multiple-input OTAs, which leads to a reduction in the number of active OTAs and power consumption. The fourth-order low-pass filter that is cascaded by two second-order filters has been presented. The fourth-order low-pass filter is designed and simulated in the Cadence environment using the 0.18 μm CMOS technology from TSMC at a supply voltage of 0.5 V. The simulation results show that the filter consumes 16 nW of power at a bandwidth of 110 Hz, has a total harmonic distortion (THD) of 1 % at 204.96 mV input amplitude, and provides dynamic range of 69.24 dB. These results indicate that the proposed low-pass filter can be applied to bio-signal processing applications.

Investigation of PNN Inverter-Based Low PDP 12T GNRFET Full Adder for VLSI Signal Processing Applications

When an adder circuit, which uses less power and operates at a higher speed, is introduced as a fundamental building block, the multiplier, arithmetic and logic unit (ALU), and digital system’s power delay product (PDP) performance can be easily improved. The graphene nanoribbon field effect transistor (GNRFET) used in very large-scale integrated (VLSI) circuits was developed in the submicron regime and offers superior electrical properties to the MOS transistor. This research paper introduces a full-adder circuit containing twelve GNRFETs (12T GF-FA). Calculations have been made about the introduced 12T GF-FA’s power usage, speed, PDP and leakage power. A few of the existing full adders with 8–32 transistors are compared to the performance of the newly proposed 12T GF-FA in terms of power and delay. For this comparison, some conventional full adders with 8–32 transistors have been implemented using 16[Formula: see text]nm technology GNRFETs. The pull-down network of the suggested adder has two stacked GNRFETs. The proposed adder’s current conduction and power consumption are reduced by the use of stacked transistors. According to the simulation results, the PDP of the suggested 12T GF-FA is 73.2–99% lower when compared to other full adders considered state-of-the-art. Additionally, it has been researched and documented how variations in the PVT and GNRFET parameters affect the performance of full-adder circuits. The proposed adder, with its low PDP, is especially suitable for VLSI signal processing applications. The simulation was carried out using the HSPICE simulation tool and the 16[Formula: see text]nm MOS-GNRFET model.

0.5 V, Low-Power Bulk-Driven Current Differencing Transconductance Amplifier.

This paper presents a novel low-power low-voltage current differencing transconductance amplifier (CDTA). To achieve a low-voltage low-power CDTA, the BD-MOST (bulk-driven MOS transistor) technique operating in a subthreshold region is used. The proposed CDTA is designed in 0.18 µm CMOS technology, can operate with a supply voltage of 0.5 V, and consumes 1.05 μW of power. The proposed CDTA is used to realize a current-mode universal filter. The filter can realize five standard transfer functions of low-pass, band-pass, high-pass and band-stop, and all-pass from the same circuit. Neither component-matching conditions nor input signals of the inverse type are required to realize these filter functions. The current-mode filter offers low-input and high-output impedance and uses grounded capacitors. The natural frequency and quality factor of the filters can be orthogonally controlled. The proposed CDTA and its applications are simulated using SPICE to confirm the feasibility and functionality of the new circuits.

The Influence of Rapid Heat Treatment During the Formation of Aluminum-Polysilicon Contacts on the Electrical Parameters of CMOS Microcircuits

The influence of rapid heat treatment (450 °C, 7 s) on the electrical parameters of CMOS integrated circuits during the formation of ohmic contact between aluminum metallization and polysilicon is considered. The following volt-ampere characteristics of the dependence of drain current on voltage were chosen as the analyzed parameters of n- and p-channel transistors: at the gate when diode-connected; on the drain at different gate voltages; on the drain in the channel breakdown mode without applying potential to the gate. A comparison of these parameters was carried out with respect to microcircuits manufactured using standard technology (450 °C, 20 min) to form these contacts. Analysis of the results showed that the use of rapid heat treatment to form an ohmic aluminum-polysilicon contact can significantly improve the above characteristics of n-MOS and p-MOS transistors. From the current-voltage characteristics of n- and p-channel transistors it follows that in the region of gate voltages greater than 0.65 V, the drain current after long-term heat treatment is higher than after quick heat treatment. Analysis of the current-voltage characteristics of the drain current versus the drain voltage showed that the drain current when using long-term heat treatment is significantly higher than after rapid heat treatment. In this case, for long-term heat treatment, there is a decrease in the channel breakdown voltage only for n-channel transistors and an increase in the drain current in the region of more than 5 V for both n- and p-channel transistors. Such improvements occur by eliminating the formation of polysilicon conglomerates in the aluminum contact, significantly reducing the epitaxial recrystallization of silicon doped with aluminum on the silicon surface, as well as reducing the microrelief of the interface of this contact and reducing the growth in the size of contact windows due to the lateral interaction of aluminum with polysilicon.

Piezo-VFETs: Vacuum Field Emission Transistors Controlled by Piezoelectric MEMS Sensors as an Artificial Mechanoreceptor with High Sensitivity and Low Power Consumption.

As one of the most promising electronic devices in the post-Moore era, nanoscale vacuum field emission transistors (VFETs) have garnered significant attention due to their unique electron transport mechanism featuring ballistic transport within vacuum channels. Existing research on these nanoscale vacuum channel devices has primarily focused on structural design for logic circuits. Studies exploring their application potential in other vital fields, such as sensors based on VFET, are more limited. In this study, for the first time, the design of a vacuum field emission transistor (VFET) coupled with a piezoelectric microelectromechanical (MEMS) sensing unit is proposed as the artificial mechanoreceptor for sensing purposes. With a negative threshold voltage similar to an N-channel depletion-mode metal oxide silicon field effect transistor, the proposed VFET has its continuous current tuned by the piezoelectric potential generated by the sensing unit, amplifying the magnitude of signals resulting from electromechanical coupling. Simulations have been conducted to validate the feasibility of such a configuration. As indictable from the simulation results, the proposed piezoelectric VFET exhibits high sensitivity and an electrically adjustable measurement range. Compared to the traditional combination of piezoelectric MEMS sensors and solid-state field effect transistors (FETs), the piezoelectric VFET design has a significantly reduced power consumption thanks to its continuous current that is orders of magnitude smaller. These findings reveal the immense potential of piezoelectric VFET in sensing applications, building up the basis for using VFETs for simple, effective, and low-power pre-amplification of piezoelectric MEMS sensors and broadening the application scope of VFET in general.

A highly efficient adaptive body bias CMOS rectifier with double-side feedback at a tone of 2.4 GHz

ABSTRACT In this paper, a highly efficient adaptive body bias CMOS rectifier employed with double side feedback, operating with 2.4 GHz frequency, is proposed for radio frequency energy harvesting. The proposed circuit is built with 45 nm TSMC CMOS technology. In the suggested architecture, the double side feedback along with body bias is used to regulate threshold voltage. The use of PMOS transistors as a diode in reverse bias configuration has restricted the reverse current without compromising the forward current. This design has gained a maximum PCE of 82.25% and 77.29% at an input power of −23.90dBm and −23.74dBm and 500K and 100K load, respectively. The circuit has maintained a wide dynamic range of 30dbm at PCE >30% and registered an input sensitivity of −10.07dBm for attaining a DC output voltage of 1 V as compared to the previous works.

An 11 nW, ＋0.34 °C/−0.38 °C inaccuracy self-biased CMOS temperature sensor at sub-thermal drain voltage

This paper presents a low-power, high-accuracy self-biased full CMOS temperature sensor based on sub-threshold currents at sub-thermal drain voltage. The sensor achieves high accuracy and minimal corner dependence by generating sub-threshold current ratios using NMOS transistors of different sizes operating at sub-thermal drain voltage. The proposed self-biased all-CMOS temperature sensing architecture enhances sensitivity by up to seven times and improves linearity. The overall stability under temperature fluctuations is significantly enhanced by utilizing a substrate diode structure that maintains constant current variation. Additionally, a high-threshold comparator with a fast response compresses the oscillator reset voltage difference, enabling ultra-low power operation. Timing logic control is employed to discard unstable cycle outputs, thereby reducing errors and achieving high-accuracy outputs. Operating at 1 V, the circuit consumes only 11 nW at 27 °C in a 180 nm CMOS process. It achieves a peak-to-peak inaccuracy of ＋0.34 °C/−0.38 °C from −10 to 100 °C after two-point calibration, with a resolution of 40 mK and a resolution FoM as low as 3.7 pJK2.

A Flexible Artificial Spiking Photoreceptor Enabled by a Single VO2 Mott Memristor for the Spike-Based Electronic Retina.

The neuromorphic vision system that utilizes spikes as information carriers is crucial for the formation of spiking neural networks. Here, we present a bioinspired flexible artificial spiking photoreceptor (ASP), which is realized by using a single VO2 Mott memristor that can simultaneously sense and encode the stimulus light into spikes. The ASP has high spike-encoded photosensitivity and ultrawide photosensing range (405-808 nm) with good endurance (>7 × 107) and high flexibility (bending radius ∼5 mm). Then, we put forward an all-spike electronic retina architecture that comprises one layer of ASPs and one layer of artificial optical nerves (AONs) to process the spike information. Each AON consists of a single Mott memristor connected in series with a neuro-transistor that is a multiple-input floating-gate MOS transistor. Simulation results demonstrate that the all-spike electronic retina can successfully segment images with high Shannon entropy, thus laying the foundation for the development of a spike-based neuromorphic vision system.

Enhanced Threshold Voltage and Improved Subthreshold Swing Using NiOX/ITO Reverse Bias Gated Diamond pMOS

An increase in the device performance of diamond‐based p‐type metal–oxide–semiconductor (pMOS) transistors using a combination of p‐type nickel oxide and n‐type indium tin oxide (NiOX/ITO) reverse bias diode as the gate dielectric is reported. Negative threshold voltage pMOS transistors are desirable for digital circuits and power applications for fail‐safe operation. A Schottky gate‐based conventional diamond pMOS transistor suffers from many limitations, including a positive threshold voltage (VT). Herein, it is experimentally demonstrated that NiOX/ITO gate dielectric with Al gate contact circumvents many critical limitations, providing a negative threshold voltage of −1.2 V, improved subthreshold slope of 145 mV dec−1, current ON/OFF ratio >107, and peak gate leakage current reduction >103. An Al/NiOX‐based control gate structure shifts the VTH negative with improvements in crucial device performances. Adding a reverse bias junction through the Al/ITO/NiOX heterointerface with the Al metal gate further improves performance. The measured device characteristics are explained in a common framework of energy band diagram for all the devices.

Addressing Power Efficiency and Stability in SRAM: A 4x4 Cell Array Design with Enhanced Power Gating

In order to lower power consumption and leakage currents during active operation, the suggested SRAM architecture with power gating design trims the source voltage across the SRAM cell, ranging from 50 to 150 mV. Power gating based on sectors is utilized, using a self-biasing approach where the gate terminal and source of a PMOS transistor act as a diode, controlling the virtual ground. However, three challenges arise with this method in nanometer technology: the additional self- biasing transistor (SBT) occupies 5% more space, the source voltage adjustment mechanisms are not effectively implemented, and the increase in virtual ground voltage leads to bias temperature instability. To implement this design, a 4x4 SRAM cell array is constructed, consisting of 4 rows and 4 columns of 10T SRAM cells. A decoder addresses these cells, and each row represents half a byte, with control circuitry managing input and output data. Additionally, the outputs of individual cells in each column are combined using a 4-bit OR, producing a single data output point. This architecture effectively reduces power consumption while maintaining operational efficiency, making it suitable for nanometer-scale SRAM designs.

Boron Delta-Doping in Si : B Stacks By RP-CVD Epitaxy

Low resistivity materials are required for advanced MOS or equivalent technologies. High boron in-situ doped Si epitaxy is known to create defects that increase the resistivity. Boron delta-doping (Si:B epitaxy alternating with boron saturation layers) is a potential solution to overcome this limitation. Using the delta-doping process at 750 °C in a Reduced Pressure Chemical Vapor Deposition reactor, a resistivity two times lower than that without delta-doping (8.9x10-4 Ω.cm and 1.86x10-3 Ω.cm respectively) was achieved. SIMS characterization measured a total boron concentration of 3.3x1021 at.cm-3. However, the delta-doping processes , as a function of the soaking volume (product of B2H6 flow and saturation time), resulted in low crystal quality and highly stressed layers. Moreover, thin layers were observed by TEM likely due to the formation of the SiBx phase at each saturation layer. For an equivalent soaking volume, a better crystal quality was obtained with a high B2H6 flow and short saturation time.

Thermal annealing induced recovery of the VT of irradiated commercial MOS transistors

Thermal annealing induced recovery of the <i>V_T</i> of irradiated commercial MOS transistors

Back-side stress to ease p-MOSFET degradation on e-MRAM chips

Abstract The magnetoresistive random access memory process makes a great contribution to threshold voltage deterioration of metal–oxide–silicon field-effect transistors, especially on p-type devices. Herein, a method was proposed to reduce the threshold voltage degradation by utilizing back-side stress. Through the deposition of tensile material on the back side, positive charges generated by silicon–hydrogen bond breakage were inhibited, resulting in a potential reduction in threshold voltage shift by up to 20%. In addition, it was found that the method could only relieve silicon–hydrogen bond breakage physically, thus failing to provide a complete cure. However, it holds significant potential for applications where additional thermal budget is undesired. Furthermore, it was also concluded that the method used in this work is irreversible, with its effect sustained to the chip package phase, and it ensures competitive reliability of the resulting magnetic tunnel junction devices.

Electrical contact property and control effects for stable T(H)-TaS2/C3B metal-semiconductor heterojunctions.

Metal-semiconductor heterojunctions are the basis for developing new electronic devices. Here, T(H)-TaS2/C3B metal-semiconductor heterostructures are constructed by different phase T- and H-TaS2 monolayers combined with the C3B monolayer. The calculated corrected binding energies, phonon band structures, elastic constants, and molecular dynamics simulations indicated that both heterojunctions are highly stable, meaning that T(H)-TaS2/C3B heterojunctions possibly exist in experiments. The electronic property calculations showed that the intrinsic T(H)-TaS2/C3B heterojunction is an n(p)-type Schottky contact with a low Schottky barrier height (SBH), which is very important for the design of high-performance field-effect transistors. The electronic properties of the T(H)-TaS2/C3B heterojunctions can be controlled by varying the vertical strain and external electric field; however, the strain only resulted in a small change in the heterojunction SBH. Nevertheless, under external electrical field control, the T-TaS2/C3B heterojunction could manage a transition from an n-type Schottky contact to an n-type Ohmic contact and the H-TaS2/C3B heterojunction could be altered from a p-type Schottky contact to a p-type Ohmic contact. These findings provide theoretical insights into the electronic and electrical contact properties of the T(H)-TaS2/C3B heterojunction, which could be beneficial for developing n-type MOS and p-type MOS transistors.