Metal Etch Process Research Articles

Effects of Gas Species on Charging Induced Tungsten Plug Corrosion during Post Metal Etch Process

Effects of gas species on charging induced tungsten plug corrosion during post metal etch process have been investigated. It was found that the O2 plasma in the dry strip process induces considerable charge build-up, which subsequently results in the tungsten plug corrosion in the solvent with pH value larger than 4.0. Experiments were performed in various strip chambers in order to find effective methods to avoid the charging by the O2 plasma. Adding H2 or H2O to the O2 plasma during the strip process or additional H2O plasma treatment right after the O2 plasma strip process were proven to be an effective way to prevents the charge build-up by the O2 plasma. Mechanisms for the charge build-up by the O2 plasma and the drastic reduction of the charging by H-related compounds are discussed.

Analysis of injection current through thin gate oxide during metal etch

A charging damage mode due to “latent antenna” formation for high aspect ratio structures in a metal etch process was investigated by a new surface charging simulation technique. The latent antenna is formed at the end of the metal etch process because of the microloading effect, and is connected to a transistor gate with 35 A thickness. By using a new simulation algorithm, the plasma stress current current–voltage (I–V) characteristic caused by topography dependent charging was calculated for different ranges of the injection current to the antenna structure. Subsequent gate injection current through the thin gate oxide was estimated by the plasma I–V with a measured holding current I–V characteristic especially optimized for high current injection. The plasma I–V was calculated for the latent antenna and a mask-defined structure (overetch structure), which are formed during an overetch period. The steady state gate injection current is largest during the latent antenna formation. Because of a device deg...

Dependence of metal sheet resistance on metal etch/post-etch treatment and subsequent process conditions

Metal sheet resistance ( R s) becomes more important in manufacturing sub-half-micron devices, especially for logic devices. This study focuses on investigating the relationship of the metal R s with metal etch/post-etch treatment conditions and subsequent deposition and annealing conditions. Various experimental results related to the metal R s variation with respect to corrosion characteristics were described in detail. The metal R s was increased with chlorine flow rate due to more isotropic etching property of chlorine plasma during the metal etch process. It was also found that the conditions of inter-metal dielectric (IMD) deposition and hydrogen annealing process performed subsequently after the metal etch are dominant factors affecting the metal R s. The metal R s of the sample with H 2 annealing (400°C, 30 min) increased up to 25.5% compared with the one obtained from the sample without H 2 treatment. The metal R s was observed to be almost independent of the pitting corrosion induced by post-wet cleaning process. In addition, the change of the metal R s for 48 h after metal etch and the mechanism of the pitting corrosion deduced from AES analysis results are mentioned in this paper.

Reactive ion etch of 150 nm Al lines for interconnections in dynamic random access memory

Three different aluminum reactive ion etch (RIE) processes have been developed for manufacturing 175 and 150 nm line/space wiring patterns in multilevel interconnection. The three approaches vary in complexity: (1) Conventional organic antireflective coating (ARC) with a photoresist etch mask, (2) inorganic silicon oxynitride dielectric ARC with a photoresist etch mask, and (3) a physical vapor deposition tungsten cap layer used as a hardmask. The reliability performance for the 150 nm Al RIE lines scales with previous technologies at larger groundrules. The process windows for each key parameters are evaluated. It is also shown that the metal etch processes can be extended to even smaller ground rules with a line or space width to height aspect ratio as high as 5 without requiring a new tool set.

Integration of metal masking and etching for deep submicron patterning

Although copper damascene interconnects offer many advantages over conventional subtractive etched Al alloys, the challenges and costs associated with converting to copper have combined to extend the useful life of Al alloy etching into the deep submicron regime. As a result, metal masking and etching are facing new challenges. Deep ultraviolet (DUV) photolithography has replaced the conventional i-line technique for patterning fine metal pitches, but some DUV photoresists are less able to withstand the aggressive plasma environment than their i-line counterparts. Reflectivity increases at DUV wavelength, so dielectric antireflective films are added on top of the metal stack. The mask-open process, where the dielectric film is plasma etched prior to etching the metal stack, alters the photoresist further and influences the subsequent metal etch. Aspect ratio dependent etch effects increase when etching narrow spaces resulting from tightened metal pitches, and gas additives may be required to protect the metal sidewalls. These effects are characterized and the challenges of deep submicron metal etch process development are discussed. The option of true hardmasked etching of the metal stack is also investigated.

A Comparative Study of Deep-UV Thin Resist by Electron Beam Stabilization.

The method of electron beam stabilization has been applied for improving the etch selectivity of resist patterns having an aspect ratio of less than 3:1. With the application of electron beam stabilization, the Deep-UV photoresists based on the chemical structures of Acetal and ESCAP have been evaluated with respect to etch selectivity as a function of electron beam dose and etch condition. A resist etch rate reduction of 20 percent and 26 percent in a metal etch process, have been observed for the two types of resists, Acetal and ESCAP respectively, at 2000μC/cm2. The thermal and chemical properties were characterized before and after electron beam stabilization using DSC, TGA, and FT-IR. The cross-sectional views of resist patterns after electron beam processing were also investigated to understand the chemical stability of resist during the electron beam process. Based on the experimental results, the application of electron beam stabilization for real device fabrication below 0.14μm has been presented.

Degradation of Ferroelectric Capacitors during Metal Etching and Ashing Processes

AbstractPolarization degradation due to metal etch and/or photoresist(PR) strip processes has been investigated for Pt/SrBi2Ta2O9(SBT)/Pt ferroelectric capacitors. Interconnect metal line consisting of TiN/Al/Ti/TiN/Ti layers has been patterned by normal photolithography and plasma etch processes. We used two different sources for metal etcher, helicon or electron cyclotron resonance(ECR) source, and stripped the PR with either microwave or helicon source stripper. Polarization degradation was evaluated by measuring switching and non-switching polarization of the ferroelectric capacitors.Neither etch machine nor etch parameters played an important role for determining polarization of the ferroelectric capacitors. Photoresist strip process, however, significantly affected the polarization of the ferroelectric capacitors. Factors affecting polarization of the ferroelectric capacitors were presence of hydrogen and plasma density during the strip process. Hydrogen atoms and protons produced by H2O or NH3 plasma penetrated through the dielectric layer and caused hydrogen induced damage. Thus the hydrogen damage was dependent on strip temperature and time. Photoresist strip with high density plasma results in charging damage to ferroelectric capacitors. It is believed that charges from the plasma are trapped at domain boundaries and interfaces, leading to polarization degradation. Damage free metal etching process for the ferroelectric capacitor was applied for the fabrication of the fully working ferroelectric random access memory.

Operating high-density plasma sources in a low-density range: Applications to metal etch processes

A new way of operating high-density plasma sources is presented which allows the resist/metal selectivity to be significantly increased during a metal etching process while maintaining the anisotropy of the etching profile. The principle of the technique is to operate a high-density plasma source in a low-density range in which the radio-frequency (rf) source power is lower than the chuck power. When the source is operated under these conditions, the ion density is strongly decreased while the source is still operated at low pressures. Optical emission spectroscopy has been used to compare the dissociation efficiency of the source operated in the low- and high-density modes. The photoresist etch rate was measured using light reflectometry. In some cases, after etching, the resist sample was transferred in vacuo into an x-ray photoelectron spectrometer analysis chamber to measure the chlorine coverage on the resist surface. The ion current density (Ji) was determined using a new type of electrostatic probe. The ion flux was determined from the discharging of a RF-biased capacitance in series with the probe. Finally, a simple model is suggested to explain the impact of the plasma operating conditions (source power and chuck power) on the resist etch rate.

Enhancement of Reactivity in Au Etching by Pulse-Time-Modulated Cl2 Plasma

In Al, Au and Pt metal etching processes, low etching rate and low etching selectivity are serious problems. To achieve a breakthrough in these problems, metal etching by pulse-time-modulated plasma was investigated. In particular, the Au etching rate was increased significantly in the pulsed plasma even when the ion energy decreases. However, an increase in the etching rate cannot be observed in Al etching. As a result, it is speculated that the increase in the Au etching rate is caused by the increase in the evaporation rate of Au etching products, which results from the injection of negative ions.

Plasma charging damage on ultrathin gate oxides

Capacitor C-V and threshold voltage and subthreshold swing of MOSFET's with gate oxide thickness varying from 2.2 to 7.7 nm are analyzed to study the plasma charging damage by the metal etching process. Surprisingly, the ultrathin gate oxide has better immunity to plasma charging damage than the thicker oxide, thanks to the excellent tolerance of the thin gate oxide to tunneling current. This finding has very positive implications for the prospect of manufacturable scaling of gate oxide to very thin thickness.

Production evaluation of real-time statistical process control on a sub-0.5 μm inductively coupled metal etch process

The semiconductor manufacturing industry is demanding improved algorithms for the detection and isolation of equipment faults. The real-time statistical process control (RTSPC) algorithm analyzes real-time sensor and actuator data for the detection of such faults. The software was evaluated using SECS-II (Serial Equipment Communication Standard) data from several commercial plasma etchers. These data were used to build statistical models which were then applied to data recorded during subsequent wafer processing. RTSPC was able to detect several faults related to failure of rf matching networks. For one of the rf match failures, the RTSPC alarm preceded the component failure by several weeks. This alarm was correlated to a shift in the critical dimension of wafers processed in this etcher. The statistical data filters included within RTSPC are discussed, as well as the characterization of the real-time data. Emphasis is placed on whether uni-variate, multivariate, or time-varying statistics are required to detect the faults seen on the etchers, and additional algorithms which would enhance the fault detection capability.

Post Metal Etch Treatment for Submicron Applications

ABSTRACTCorrosion control and passivation of post metal etch structures are critical for submicron applications and overall yield performance. This study focused on 0.6 micron metal line spaces and the development of a process utilizing an integrated metal etch, photoresist strip and passivation tool. Data collected to characterize the corrosion/passivation mechanism included: veil and photoresist strip chemistries, passivation steps, time delays, subsurface material versus veil formation and electrical and defectivity yield. A post metal etch process was tested and integrated into a manufacturing environment that has provided minimal line loss, complete removal of etch veils, robust corrosion control and substantial reduction of intermetal shorts.

Round-Up

CTI-Cryogenics has launched the company's first On-Board waterpumps, which have been specifically designed to decrease the formation of particulates during semiconductor metal etch processing. Reducing particulates can decrease the amount of cleaning needed, thereby significantly improving tool productivity. The elimination of water slows particulate formulation from the etch residue and reduces flaking from the exposed aluminium surfaces.

Development of a gate metal etch process for gallium arsenide wafers

The reactive ion etching of TiWN, which is used as a gate metal on gallium-arsenide device wafers, was studied in a parallel-plate, single-wafer plasma reactor operating at a frequency of 13.56 MHz. We discuss our experimental program designed to develop a highly uniform TiWN etch process with low linewidth loss for 100 mm GaAs wafers, using a sulfur hexafluoride, trifluoromethane, helium chemistry. The effects of different gas compositions, plasma power, inter-electrode gap, chamber pressure, and electrode temperature on the TiWN etch rate, linewidth loss, and etch uniformity were determined. The effects of adding oxygen and/or nitrogen to the above mixture were also studied. In preliminary experiments on Si wafers, standard design of experiments methods were used to narrow the ranges of parameters for further experiments to develop an optimum process for Si wafers. The results of these experiments guided us to the optimum process for GaAs wafers. The optimum conditions, for both Si and GaAs wafers, are presented.

Characterization and optimization of metal etch processes to minimize charging damage to submicron transistor gate oxide

Two metal etch systems are compared in terms of their impacts on submicron transistor gate oxide integrity. The magnetically enhanced RIE (MERIE) system is shown to cause significant gate oxide damage with a pronounced radial dependence. This damage does not occur on wafers etched in the hexode-type RIE system. Experimental work on the MERIE system shows that the presence of the magnetic field during the aluminum overetch and barrier metal etch portion of the process is the primary cause for the observed gate oxide damage. This damage can be minimized by reducing or eliminating the magnetic field during the overetch step.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Plasma Etching of Aluminum Metallizations for Ultralarge Scale Integrated Circuits

The metallizations which interconnect devices formed on silicon wafers have evolved from a single level of “broad” lines of aluminum to very narrow lines (<1 μm in width), often more than two levels per chip. Whereas broad lines may be satisfactorily defined by solution or “wet” etching, narrow lines must be defined by plasma etching to maintain dimensional and profile control. Moreover, simple aluminum metallization has become complex, generally consisting of a composite of barrier and antireflecting layers which sandwich the aluminum film. In addition, the aluminum film itself is probably “doped” with silicon and copper for solid solubility and electromigration considerations. Consequently, plasma etching of “aluminum” has become more complicated in the last few years. In this article, the issues confronting the process engineer in attempting to implement reliable metal etching processes are reviewed, emphasizing metallization layers employed for very advanced complementary metal oxide semiconductor integrated circuits.

Magnetron-Enhanced Reactive-Ion-Etching of Al-1%Si-2%Cu Alloy

ABSTRACTPlasma etching of Al-1%Si-2%Cu presents serious challenges in corrosion, residue, and critical dimension (CD) control in single wafer etchers. One approach is to pattern the metal with oxide mask so chlorine can no longer be trapped in resist and sidewall polymers to cause corrosion. The magnetron-enhanced reactive-ion-etching (MERIE) offers a high degree of ionization at very low pressure, so anisotropic etching with reasonably high etch rate can be achieved even without sidewall protection. This paper summarizes our MERIE process characterization in terms of the effects of SiCl4 flow rate and plasma power on selectivity and CD control using an oxide mask. Typical etching was performed at 1000 watts and 40 sccm SiCl4 with the unthrottled pressure at 4.0 mTorr and a self-induced dc bias of 75 V. A 2-minute NF3 plasma at 250 watts and 100 sccm of NF3 flow served as the passivation step. This metal etch process has been successfully implemented in a doublelayer-metal interconnect technology.