Bond Pad Metallization Research Articles

Impact of Thermo-Mechanical Stress Due to Probing and Wire Bonding on CUP Devices

Recently, the circuit under pad (CUP) designs are getting very popular because they could save lots of silicon especially for high-density and high-complexity applications. Polysilicon is a material widely used in many electronic device components. When such devices are placed underneath the bond pads, it is highly expected not to show any change in the electrical behavior due to any kind of thermo-mechanical stresses such as probing or wire bonding mainly during the process of packaging. This article presents a detailed investigation of such impacts on a polysilicon resistor placed underneath the bond pads. The standard meander-shaped polysilicon resistor was used as a test vehicle. In this article, different stress-causing factors such as probing insertions, probing temperature, and wire bond materials were investigated in detail. The impact of such thermo-mechanical stresses is simulated using Comsol to understand the stress phenomenon and for qualitative analysis. Then, the wafer-level silicon testing was carried out to quantify the impact of such thermo-mechanical stresses using a standard design of experiments (DOEs). The impact in terms of change in resistance of the polysilicon resistor of two different widths (5 and 0.42 μm) for two different bond pad metal options viz. Middle thickness metal (METMID) (thickness of 880 nm) and thick metal (METTHK) (thickness of 3000 nm) was investigated. The percent change in resistance was observed to be very negligible after multiple probing attempts and probe temperatures. However, after wire bonding, up to ~14% change in resistance was observed when copper was used as the wire bonding material. Nevertheless, this percent change was still well within the reliability specification limit set by Joint Electron Device Engineering Council (JEDEC), which is widely used in the industry. This detailed investigation will help CUP designers choose the correct back end of line (BEOL) metal options and also wire bonding material upfront and accordingly plan their design margins.

Relative Contributions of Packaging Elements to the Thermal Hysteresis of a MEMS Pressure Sensor

Piezoresistive silicon pressure sensor samples were thermally cycled after being consecutively packaged to three different levels. These started with the absolute minimum to allow measurement of the output and with each subsequent level incorporating additional packaging elements within the build. Fitting the data to a mathematical function was necessary both to correct for any testing uncertainties within the pressure and temperature controllers, and to enable the identification and quantification of any hysteresis. Without being subjected to any previous thermal preconditioning, the sensors were characterized over three different temperature ranges and for multiple cycles, in order to determine the relative contributions of each packaging level toward thermal hysteresis. After reaching a stabilised hysteretic behaviour, 88.5% of the thermal hysteresis was determined to be related to the bond pads and wire bonds, which is likely to be due to the large thermal mismatch between the silicon and bond pad metallisation. The fluid-fill and isolation membrane contributed just 7.2% of the total hysteresis and the remaining 4.3% was related to the adhesive used for attachment of the sensing element to the housing. This novel sequential packaging evaluation methodology is independent of sensor design and is useful in identifying those packaging elements contributing the most to hysteresis.

A computational study of the effect of bond pad thickness on the polysilicon piezoresistivity due to wafer level probing

Polysilicon is an integral part of many devices in all CMOS processes. Circuit Under Pad (CUP) devices are required to have consistent and accurate electrical performance just like any other device. This paper presents an investigation on stress impact of probe insertions on two bond pad metal options (METMID and METTHK) on a polysilicon resistor placed under the bond pad. Wafer level probing results in residual stress on both Back End Of Line (BEOL) as well as Front End Of Line (FEOL) structures. This residual stress would impact the electrical properties of the polysilicon material used in such devices. In this study, such electrical impact is measured in terms of change in resistance (piezoresistivity) of a polysilicon resistor which was placed underneath the bond pads. A commercial finite element analysis software (Comsol Multiphysics) was used to predict the stress distribution in the polysilicon device, followed by experimental validation of the electrical resistance. It was observed that the bond pad thickness can influence the residual stress which in turn causes a change in resistance after wafer level probing. However, for each bond pad thickness, multiple probe insertions did not significantly change the resistance of the device placed under the bond pad.

Photosensitive Glass-Ceramics for Heterogeneous Integration

The push for heterogeneous integration requires very unique material properties with respect to processing, material constants, and integration capabilities with other materials (such as copper, II...

Intermetallic growth kinetics of 2N gold wire ball bonds on aluminium bond pads annealed at 175 °C

Gold ball bonding wires of 2N purity were bonded to Si devices with aluminium alloy bond pad metallisation. Specimens were subjected to isothermal annealing at 175 °C in a fan-circulated oven in an air environment for various times t. Samples of ball bonds from each specimen were cross-sectioned, and the total intermetallic thickness x at the centre of the ball bonds was measured. The kinetics of x versus t were modelled using a power law expression $$ x(t)={x}_0+{\theta}_1{t}^{\theta_2} $$ with growth parameter θ 1 and constrained parameter 0 < θ 2 ≤ 1. The parameter θ 2 is supposedly capable of differentiating between diffusion controlled intermetallic growth (grain boundary and/or volume diffusion) and interfacial reaction controlled growth with the presence/absence of grain growth solely based on its numerical value. The parameters θ 1 and θ 2 and the regression function were obtained by log-transformation of both the response variable x and the explanatory variable t and data fitting using simple linear regression (SLR), taking care to perform diagnostic checks to confirm that transformed data satisfied the requirements of SLR. Simulated intermetallic thickness data obtained by sampling from lognormal distributions was observed to closely approximate the experimental observations. Values of the exponent θ 2 were observed in the range 0.2–0.4, which was interpreted as indicative of grain boundary dominated interdiffusion with grain growth.

Effect of Cu and PdCu wire bonding on bond pad splash

Cu wire bonding research has exploded exponentially in the past few years. Many studies have been carried out to understand the different behaviours of Cu wire and Au wire. One of the observations on Cu wire bonding is the excessive formation of aluminium (Al) splash on the bond pad due to a higher bond force. This leads to pad peeling and bond failure resulting in poor reliability performance of Cu and PdCu wire semiconductor devices. It is known that the Al splash is influenced by the front-end pad metal process and back-end wire bond process. Reported is the design of an experiment carried out to study a few factors that could influence the Al splash. The characterisation work is implemented to understand the bond pad structure using the focused ion beam (FIB) followed by a hardness test of bond pad metallisation. Then the mechanical cross-section is taken to measure the Al splash in three different directions. The results show that Al splash can be controlled by optimising the bond pad thickness, hardness and additive for reliable Cu and PdCu wire bonding.

Effect of Metal Bond-Pad Configurations on the Solder Microstructure Development of Flip-Chip Solder Joints

Various microstructural zones were observed in the solidified solder of flip-chip solder joints with three metal bond-pad configurations (Cu/Sn/Cu, Ni/Sn/Cu, and Cu/Sn/Ni). The developed microstructures of the solidified flip-chip solder joints were strongly related to the associated metal bond pad. A hypoeutectic microstructure always developed near the Ni bond pad, and a eutectic or hypereutectic microstructure formed near the Cu pad. The effect of the metal bond pads on the solder microstructure alters the Cu solubility in the molten solder. The Cu content (solubility) in the molten Sn(Cu) solder eventually leads to the development of particular microstructures. In addition to the effect of the associated metal bond pads, the developed microstructure of the flip-chip solder joint depends on the configuration of the metal bond pads. A hypereutectic microstructure formed near the bottom Cu pad, and a eutectic microstructure formed near the top Cu pad. Directional cooling in the flip-chip solder joint during the solidification process causes the effects of the metal bond-pad configuration. Directional cooling causes the Cu content to vary in the liquid Sn(Cu) phase, resulting in the formation of distinct microstructural zones in the developed microstructure of the flip-chip solder joint.

Effectiveness of Barrier Layer Metallizations in Long Term High Temperature Endurance Tests on Wire Bond Interconnections

Silicon on insulator (SOI) device technology has been shown to be capable of functioning satisfactorily at operating temperatures of &amp;gt;200°C, with device lifetimes of 5 y at 225°C being declared. One of the key areas governing the lifetime of the packaged electronic devices is the reliability of the wire bond interconnection between the device and the package or substrate connection. Extended temperature storage testing at 250°C of packaged SOI devices has highlighted end of life failure modes associated with wire bond connections. SOI devices are normally supplied with an aluminum based bond pad metallization, which are not suitable for direct connection of Au wire at operating temperatures of &amp;gt;125°C, due to the formation of Au-Al intermetallics. It is possible to postprocess silicon wafers to deposit barrier and connection materials to create a monometallic Au-Au joint at the surface. For long term endurance at temperatures &amp;gt;200°C, the effectiveness of the barrier layer in preventing diffusion of the aluminum bond pad metallization to interact with the Au is a critical factor. This paper presents results of studies carried out on two postprocess metallization systems Au/TiW and Au/Pd/Ni deposited onto aluminum bond pads, which have been Au wire bonded and exposed to 250°C temperature storage for up to 13,000 h. The results have shown that the barrier layers are not effective in preventing diffusion of the aluminum bond pad metallization to create Au-Al based intermetallics. The results are compared with Al-1%Si wire bonding to the aluminum bond pad, where the second wedge bond is attached to a Au/Ni plated metallization, where the degradation appears to be less severe. Recommendations for designing stable wire bond interconnection systems for extended high temperature operation will be presented.

Dicing Development for low-k Copper Wafers using Nickel-Palladium-Gold Bond Pads for Automotive Application

New automotive requirements expect plastic packages to survive higher operating temperatures with extended thermal duration. Mission profiles for under-the-hood and transmission application historically specified minimal duration at maximum junction temperature, such as 50 total hours at 150C, while keeping most of the total operating duration at lower temperatures. Further module integration and more stringent environmental requirements push modules and thus plastic packages closer to the heat source. As such, new mission profiles include more than 3500 total hours at 150°C. To satisfy new automotive requirements, plastic packages must meet AEC Grade 0 or higher. One key limitation of the conventional plastic package is the use of gold bond wire on aluminum bond pad. Au-Al intermetallic degradation due to intermetallic transformation in high temperature storage condition remains the main reliability concern. More reliable intermetallic systems have been proposed that change the wire material and/or the bond pad metallization. An alternative wire material to gold, copper, has many benefits including low cost, high electrical and thermal conductivities and excellent reliability with aluminum pad metallization. Pad re-metallization using nickel/palladium, nickel/gold or nickel/palladium/gold over aluminum bond pad or copper bond pad offers a noble and reliable metal interconnect. This study focused on the development of dicing process for low-K-copper wafers having aluminum pad re-metallized with electroless nickel / electroless palladium / immersion gold Over Pad Metallization (OPM). Development wafers were pizza mask wafers on which multiple die designs and scribe grid production control (SGPC) modules were designed. SGPC modules are designed with aluminum probe pads that are used to monitor wafer-level process control. All aluminum features on the wafer were plated with nickel/palladium/gold OPM. With the hardness of nickel and palladium being more than 10 to 15 times the hardness of aluminum, OPM-plated SGPC's were much more difficult to dice than conventional SGPC's with aluminum pads. Cracking on silicon sidewall with crack propagating towards the die was found to cause back-end-of-line (BEOL) delamination and device failure. Extensive mechanical dicing studies were conducted to modulate the failures and resolve the dicing challenge. Specifically, dicing was observed to be not centered on SPGC pads on the pizza mask. Off-centered dicing produced drastic change in Ni loading at the center of the blade and on the edges of the blade. Packages underwent extensive reliability stress conditions. The associated process improvements described in this paper supported a successful integration of a 55nm die technology in Low Profile Quad Flat Package with Exposed Pad (LQFP-EP) meeting and exceeding AEC grade 0 requirements.

Effectiveness of Barrier Layer Metallisations in Long Term High Temperature Endurance Tests on Wire Bond Interconnections

Silicon on Insulator (SOI) device technology has been shown to be capable of functioning satisfactorily at operating temperatures of &amp;gt;200°C, with device lifetimes of 5 years at 225°C being declared. One of the key areas governing the lifetime of the packaged electronic devices is the reliability of the wire bond interconnection between the device and the package or substrate connection. Extended temperature storage testing at 250°C of packaged SOI devices has highlighted end of life failure modes associated with wire bond connections. SOI devices are normally supplied with an aluminium based bond pad metallisation, which are not suitable for direct connection of Au wire at operating temperatures of &amp;gt;125°C, due to the formation of Au-Al intermetallics. It is possible to post-process silicon wafers to deposit barrier and connection materials to create a mono-metallic Au-Au joint at the surface. For long term endurance at temperatures &amp;gt;200°C, the effectiveness of the barrier layer in preventing diffusion of the aluminium bond pad metallisation to interact with the Au is a critical factor. This paper presents results of studies carried out on two post-process metallisation systems Au/TiW and Au/Pd/Ni deposited onto aluminium bond pads, which have been Au wire bonded and exposed to 250°C temperature storage for up to 13,000 hours. The results have shown that the barrier layers are not effective in preventing diffusion of the aluminium bond pad metallisation to create Au-Al based intermetallics. The results are compared with Al-1%Si wire bonding to the aluminium bond pad, where the 2nd wedge bond is attached to a Au/Ni plated metallisation, where the degradation appears to be less severe. Recommendations for designing stable wire bond interconnection systems for extended high temperature operation will be presented.

Oxidation study on as-bonded intermetallic of copper wire–aluminum bond pad metallization for electronic microchip

In this work, influence of Copper free air ball (FAB) oxidation towards Intermetallic Compound (IMC) at Copper wire–Aluminum bond pad metallization (Cu/Al) is studied. Samples are synthesized with different Copper FAB oxidation condition by turning Forming Gas supply ON and OFF. Studies are performed using Optical Microscope (OM), Scanning Electron Microscope (SEM), Transmission Electron Microscope (TEM) and line-scan Energy Dispersive X-ray (EDX). SEM result shows there is a cross-sectional position offset from center in sample synthesized with Forming Gas OFF. This is due to difficulty of determining the position of cross-section in manual grinding/polishing process and high occurrence rate of golf-clubbed shape of oxidized Copper ball bond. TEM inspection reveals that the Copper ball bond on sample synthesized with Forming Gas OFF is having intermediate oxidation. Besides, the presence of IMC at the bonding interface of Cu/Al for both samples is seen. TEM study shows voids form at the bonding interface of Forming Gas ON sample belongs to unbonded area; while that in Forming Gas OFF sample is due to volume shrinkage of IMC growth. Line-scan EDX shows the phases present in the interfaces of as-bonded samples are Al4Cu9 (∼3 nm) for sample with Forming Gas ON and mixed CuAl and CuAl2 (∼15 nm) for sample with Forming Gas OFF. Thicker IMC in sample with Forming Gas OFF is due to cross-section is positioned at high stress area that is close to edge of ball bond. Mechanical ball shear test shows that shear strength of sample with Forming Gas OFF is about 19% lower than that of sample with Forming Gas ON. Interface temperature is estimated at 437 °C for as-bonded sample with Forming Gas ON by using empirical parabolic law of volume diffusion.

Dicing Development for low-k Copper Wafers using Nickel-Palladium-Gold Bond Pads for Automotive Application

New automotive requirements expect plastic packages to survive higher operating temperatures with extended thermal duration. Mission profiles for under-the-hood and transmission application historically specified minimal duration at maximum junction temperature, such as 50 total hours at 150C, while keeping most of the total operating duration at lower temperatures. Further module integration and more stringent environmental requirements push modules and thus plastic packages closer to the heat source. As such, new mission profiles include more than 3500 total hours at 150°C. To satisfy new automotive requirements, plastic packages must meet AEC Grade 0 or higher. One key limitation of the conventional plastic package is the use of gold bond wire on aluminum bond pad. Au-Al intermetallic degradation due to intermetallic transformation in high temperature storage condition remains the main reliability concern. More reliable intermetallic systems have been proposed that change the wire material and/or the bond pad metallization. An alternative wire material to gold, copper, has many benefits including low cost, high electrical and thermal conductivities and excellent reliability with aluminum pad metallization. Pad re-metallization using nickel/palladium, nickel/gold or nickel/palladium/gold over aluminum bond pad or copper bond pad offers a noble and reliable metal interconnect. This study focused on the development of dicing process for low-K-copper wafers having aluminum pad re-metallized with electroless nickel / electroless palladium / immersion gold Over Pad Metallization (OPM). Development wafers were pizza mask wafers on which multiple die designs and scribe grid production control (SGPC) modules were designed. SGPC modules are designed with aluminum probe pads that are used to monitor wafer-level process control. All aluminum features on the wafer were plated with nickel/palladium/gold OPM. With nickel about four times as hard as aluminum, OPM plated SGPC's were much more difficult to dice than conventional SGPC's with aluminum pads. Cracking on silicon sidewall with crack propagating towards the die was found to cause back-end-of-line (BEOL) delamination and device failure. Surface roughness and hardness measurements were taken on OPM variations. Extensive mechanical dicing studies were conducted to modulate the failures and resolve the dicing challenge. Laser grooving followed by mechanical dicing of OPM wafers was also performed. Packages underwent extensive reliability stress conditions. The associated process improvements described in this paper supported a successful integration of a 55nm die technology in Low Profile Quad Flat Package with Exposed Pad (LQFP-EP) meeting and exceeding AEC grade 0 requirements.

Comparison of Gold and Copper Wire Bonding on Aluminum and Nickel-Palladium-Gold Bond Pads for Automotive Application

New automotive requirements expect plastic packages to survive higher operating temperatures with extended thermal duration. Mission profiles for under-the-hood and transmission application historically specified minimal duration at maximum junction temperature, such as 50 total hours at 150C, while keeping most of the total operating duration at lower temperatures. Further module integration and more stringent environmental requirements push modules and thus plastic packages closer to the heat source. As such, new mission profiles include more than 3500 total hours at 150°C. To satisfy new automotive requirements, plastic packages must meet AEC Grade 0 or higher. One key limitation of the conventional plastic package is the use of gold bond wire on aluminum bond pad. Au-Al intermetallic degradation due to intermetallic transformation in high temperature storage condition remains the main reliability concern. More reliable intermetallic systems have been proposed that change the wire material and/or the bond pad metallization. An alternative wire material to gold, copper, has many benefits including low cost, high electrical and thermal conductivities and excellent reliability with aluminum pad metallization. Pad re-metallization using nickel/palladium, nickel/gold or nickel/palladium/gold over aluminum bond pad or copper bond pad offers a noble and reliable metal interconnect. This study focused on evaluating Au and Cu wire bonding on low-K-copper wafers having two types of bonding surfaces, the conventional aluminum pad and aluminum pad re-metallized with electroless nickel / electroless palladium / immersion gold. Ni thickness ranging from 1μm to 3μm was evaluated. Defects on as-plated Ni/Pd/Au bond pads such as color difference and surface roughness were determined to be due to nodule growth and plating non-uniformity. Wire bonded strip-level thermal aging was conducted to compare the high-temperature performance of the four interconnect types. Packages underwent extensive reliability stress conditions. Cross-sectioning through the ball bonds was also conducted to examine the welding region between the ball bond and bond pad. Defects in plating and wire bonding processes causing package reliability failures were identified. Recommendations for plating and wire bonding processes were derived to ensure high quality and reliable interconnect exceeding AEC grade 0 requirements.

300mm Scaling of Critical Silicon Etches for Image Sensor Wafer-Level Packaging Based on Tessera's MVP (TSV) Technology

Miniature, high performance camera modules are found in a range of consumer devices including phones, PDAs, cameras and gaming consoles. According to Gartner the $1B image sensor market will grow to $2.3B by 2013. Image sensor packaging technologies are increasingly required to deliver greater reliability within smaller form factors. Tessera's OptiML™ Micro Via Pad (MVP) wafer-level packaging technology is in production on 200mm wafers. This paper will report on the first joint activity that scales this technology to 300mm. We focus on three critical silicon etches that form the back-bone of the structure. These etches are carried out from the wafer back-side while bonded to a glass carrier. First there is a blanket dry etch. This removes stress introduced by the back-grind. Uniformity control to &amp;lt; ±5% is essential for this process. Second, after a lithography step, tapered silicon trenches are etched forming streets to a certain depth. The trench etch uniformity is critical because it defines the depth range for the subsequent Vias. Profile control is needed to ease the subsequent spray-coat lithography. Lastly, vias are then etched down to metal bond pads on the device side of the wafer. CD and taper control is required here both within wafer and between wafers. End-pointing represents a way of ensuring process reproducibility. In 2010 Tessera carried out 300mm demos with key suppliers. As part of this activity SPTS scaled the above critical silicon etches. The wafers were further processed into functional die. We will describe the etch equipment used, report on the critical processes developed emphasizing the relationships between 200mm and 300mm results and the essential control parameters. We will also demonstrate successful scaling by including data on the electrical performance of packaged devices.

Cu wire bond parameter optimization on various bond pad metallization and barrier layer material schemes

The use of copper wire for semiconductor package assembly has been gradually gaining acceptance throughout the industry over the last decade. Although copper has several advantages over gold for wire bonding applications, the manufacturing difficulties using copper wire have made high volume, fine pitch copper bonding slow to materialize. In recent years with the spike in gold prices, copper wire has become even more attractive, and this has driven many studies on the topic. Due to the propensity for copper to work harden upon deformation, which occurs during the ball bonding process as the capillary tip smashes the ball into the bond pad, a high amount of stress is transferred into the bond pad structure. This can result in catastrophic defects such as dielectric cracking or pad cratering. The current study aims to quantify the level of underlying bond pad damage with respect to various bond pad metallization and barrier layer schemes. A first bond parameter optimization was completed on each experimental group. The results indicate that barrier layer structure and composition have a significant impact on the presence of pad cratering. The experimental group containing only TiN as the barrier material showed a high occurrence of cratering, while groups with Ti and TiW barrier metals showed no cratering, even if a TiN layer was on top of the Ti. The bond pad metal thickness, on the other hand, does not appear to play a significant role in the prevention of bond pad cratering. Metal thickness values ranging from 0.825 to 2.025 μm were evaluated, and none had bond pad cratering other than the group with TiN as the barrier metal. In addition to the first bond parameter evaluations with various bond pad and barrier metal combinations, the initial free air ball (FAB) optimization is discussed.

2 mils Au wire interchip wedge bond cratering study

Au wire thermosonic wedge bonding is applied for die to die interconnect on accelerometer device. With the fragile bond pad structure of MEMS device, bond pad cratering or bond pad metal peel is a fatal wedge bond defect during assembly packaging and reliability failure during field application. Typical interchip wedge bond failure mode and the cause of failures are studied through analyzing wedge bonding mechanism, packaging &amp; tooling design and bond pad metallization. Comprehensive wedge bond process characterization was carried out to improve wedge bond quality and reliability. Critical wedge bond responses (wedge pull, wedge shear, Cratering) were studied during wedge bond process characterization. Post wedge bond cratering has good correlation with the wedge tool in both position and shape. Si nodule underneath the bond pad metal generates higher local stress to the bond pad during wedge bonding. Thinner bond pad metal could not act as a cushion to mitigate the wedge bond stress to the poly silicon layer beneath the bond pad. The initial post wedge bond cratering / bond pad damage will get deteriorated during following assembly reflow process as well as SMT process, eventually the weakest interface layer beneath the bond pad will be separated, reflected as the bond pad metal peel. Approaches to enhance interchip wedge bond integrity were explored and significant improvements were seen.

Dependence of the Fracture of PowerTrench MOSFET Device on Its Topography in Cu Bonding Process

Dependence of the fracture-resistance of a PowerTrench MOSFET device on its topography in Cu bonding process was investigated. Two different topographies, namely dimple and round, have been tested. A significantly higher cratering rate has been clearly observed on dimple topography. The dimple topography exhibited a cratering rate of 371 k ppm levels compared to 0 ppm in round topographies. Three-dimensional nonlinear finite-element analysis has shown that the largest compressive and shear stresses and their locations were identified, respectively, in borophosphosilicate glass (BPSG)/barrier metal layers of the dimple topography. The round topography had the smallest stress in BPSG/barrier metal layers. The higher compressive stress transferred to silicon in the dimple topography during the bonding process can induce a local crack, consequently causing silicon fracturing during the shearing processes. A significant improvement in the cratering performance was observed when the Al bond pad metal layer was reinforced by adding a barrier layer sandwiched in the Al metal layers. The cratering rate decreased to 1300 ppm levels. Additionally, the change in composition of a BPSG layer caused cratering was briefly discussed and an oxygen rich BPSG film in round topography was confirmed by the energy dispersive spectroscopy (EDS) of a cross-sectional TEM sample. It has been found that the cratering rate on dimple topography significantly increased from 1 k ppm to 100 k ppm levels, when the resulting residual Al pad thickness is less than 0.65 mum for Cu bonding performed with different ultrasonic (US) power and bond forces.

Wire bonding of low‐k devices

PurposeThe purpose of this paper is to review recent advances in wire bonding of low‐k devices.Design/methodology/approachDozens of journal and conference articles published in 2005‐2008 are reviewed.FindingsThe paper finds that many articles have discussed and analysed problems/challenges such as bond pad metal peeling/lift, non‐sticking on pad, decreased bonding strength and lower wire‐bond assembly yield. The paper discusses the articles' solutions to the problems and recent findings/developments in wire bonding of low‐k devices.Research limitations/implicationsBecause of the page limitation, only brief discussions are given in this paper. Further reading is needed for more details.Originality/valueThe paper attempts to provide an introduction to recent developments and the trends in wire bonding of low‐k devices. With the references provided, readers may explore more deeply by reading the original articles.

Reliability of BGA Solder Joints on the Au/Ni/Cu Bond Pad-Effect of Thicknesses of Au and Ni Layer

A systematic experimental work has been carried out to investigate the effect of thicknesses of the Au and Ni layers in the bond pad metallization on the reliability of ball grid array (BGA) solder joints as well as to understand the mechanism of Au diffusion to the solder interface. BGA solder balls of Sn-37 wt.% Pb have been bonded on BGA solder bond pads of Au/electrolytic Ni/Cu by reflowing at 225 degC for 0.5 min. The thickness of the Ni layer was varied from 0.35 to 2.8 mum, while the thickness of Au layer was varied from 0.1 to 1.3 mum. Solid state aging at 150 degC up to 1000 h has been carried out to simulate the ultimate interfacial reactions during the operational life of electronic devices. Cross-sectional studies of the solder-to-bond pad interfaces have been conducted by scanning electron microscopy equipped with an energy-dispersive X-ray analyzer to investigate the interfacial reaction phenomena. Ball shear tests have been carried out to obtain the mechanical strength of the solder joints and to correlate shear behavior with the interfacial reaction products. After the shear tests, fracture surfaces have also been investigated to understand the fracture modes. It has been found that Au embrittlement in the BGA Sn-Pb solder joints on Au/Ni/Cu BGA bond pads can be reduced by using either a thin Au layer or a thin Ni layer in the trilayer metallization of Au/Ni/Cu. It is easy to understand why Au embrittlement is reduced when a thin Au layer in the BGA bond pad is used; however, contrary to the usual expectation, it has been realized in this paper that a very thin Ni metallization is an effective means to maintain the mechanical integrity of the BGA SnPb solder joint. It is revealed that the out-diffusion of the Cu atoms during the aging period changes the chemistry and morphology of the intermetallic compounds (IMCs) at the solder interface, contributing to a significant reduction in brittleness. During aging at 150 degC, the thin Ni layer facilitates Cu diffusion from the bond pad toward IMCs. As a result, the brittle continuous layers of (Au,Ni)Sn <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">4</sub> and Ni <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> Sn <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">4</sub> are transformed into a nodular-shaped discontinuous layer of AuSn <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">4</sub> and a layer of (Au,Cu,Ni) <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">6 </sub> Sn <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">5</sub> , respectively. New interfacial reaction products with the modified morphology change the typical scenario of Au embrittlement at the BGA solder interface and thus improve the interfacial joint strength significantly

Oxidation of Au 4Al in gold ballbonds

Two different 4N (99.99% purity) gold wires were ballbonded on 1 μm thick Al–1 wt.% Si–0.5 wt.% Cu bondpad metallisation and subjected to high temperature storage (HTS) at 175 °C in air. Each wire type showed ball lift failures, Type A after 500 h and Type B after 1500 h, which in both cases was a result of Au 4Al oxidation. With wire Type A the dominant compound underneath the ball was Au 8Al 3. A thin layer of Au 4Al (≈ 1 μm thick) was observed between the Au 8Al 3 and the gold ball. Ball lift failures occurred in the Au 4Al layer, which appeared to disintegrate due to oxidation and the resulting by products of oxidation were deposited on the underlying and unoxidised Au 8Al 3. With wire Type B, a double layer Au 4Al was dominant after long term ageing and Au 8Al 3 was confined to the ball periphery. Consequently, because of the much greater volume of Au 4Al, compound oxidation resulted in the formation of a large amount of a completely new microstructure consisting of gold precipitates embedded in a dark oxide matrix. The Au 8Al 3 compound remained unoxidised. It is speculated that internal stress and contamination may accelerate the oxidation reaction.