Mesh Interconnection Network Research Articles

Performance Evaluation of Contiguous and Noncontiguous Processor Allocation Based on Common Communication Patterns for 2D Mesh Interconnection Network

Several processor allocation studies show that the performance of noncontiguous allocation is dramatically better than that of contiguous allocation, but this is not always true. The communication pattern may have a great effect on the performance of processor allocation algorithms. In this paper, the performance of well-known allocation algorithms is re-considered based on several communication patterns, including Near Neighbor, Ring, All-to-All, Divide and Conquer Binomial Tree (DQBT), Fast Fourier Transform (FFT), One-to-All, All-to-One, and Random. The allocation algorithms investigated include the contiguous First Fit (FF) and Best Fit (BF) and the noncontiguous Paging(0), Greedy Available Busy List (GABL) and Multiple Buddy Strategy (MBS). In near neighbor, FFT and DQBT, the simulation results show that the performance of contiguous allocation is dramatically better than that of the noncontiguous allocation in terms of response time; except for MBS in DQBT. In All-to-All, the results show that the performance of contiguous FF and BF is better than that of the noncontiguous MBS.

Improving system performance in non-contiguous processor allocation for mesh interconnection networks

Contiguous allocation of parallel jobs in multicomputers usually suffers from the degrading effects of fragmentation, because it requires that the allocated processors be contiguous and have the same topology as that of the multicomputer's interconnection network. Fragmentation can be avoided by adopting non-contiguous allocation. However, non-contiguous allocation can increase the distances among processors allocated to a job, which can increase the interference among messages of different jobs and increases message contention and delays. This paper suggests a new non-contiguous processor allocation strategy, referred to as Minimum Interference Paging (MIP), for the 2D mesh network. MIP attempts to reduce the distances among processors allocated using a paging variant that chooses a set of processors with the lowest distance between the first and last allocated processors, where the distance is the number of processors between the first allocated node and last allocated node. Using software simulation, we compared the performance of MIP against that of several well-known non-contiguous allocation strategies: paging (0), Multiple Buddy System (MBS) and Adaptive Non-contiguous Allocation (ANCA). The comparative evaluation was conducted using First-Come-First-Served (FCFS) job scheduling, wormhole routing and six communication patterns. These are the one-to-all, all-to-all, Near Neighbour, Ring, Divide and Conquer Binomial Tree (DQBT), and Random communication patterns. The results show that MIP exhibits superior performance in terms of average turnaround time of jobs.

Broadcast communication operations for hyper hexa-cell interconnection network

The hyper hexa-cell (HHC) interconnection network is relatively a new interconnection network, which is constructed from hexa-cell and hypercube topologies. HHC is developed to support parallel algorithms for solving computation and communication intensive problems. Thus, in order to support solving these problems efficiently, this paper presents two broadcast communication operations for HHC using store-and-forward technique; namely, one-to-all and all-to-all broadcast operations; which allow a message to be transmitted through the shortest path from the source node to all other nodes. The broadcast communication operations are evaluated analytically in terms of communication steps, communication latency, communication cost, and speed over HHC and wraparound square mesh interconnection networks. The analytical results over HHC show that in both one-to-all and all-to-all broadcast operations, the maximum communication steps are \( d + 2\), where d is the dimension of HHC, which is a small integer number. Also, the communication latency increases linearly when the network size increases, and the communication cost for the broadcast operations is equal to O(\(2^{d-1})\). Moreover, the speed of both broadcast operations on d-dimensional HHC is \(d+2\times \)speed of electronic links. In comparison between HHC and wraparound square mesh, one-to-all and all-to-all broadcast communication operations over HHC perform much better than mesh in terms of maximum communication steps, communication latency, and speed.

Optimal extra links placement in mesh interconnection network using improved environmental adaptation method

Many variants of the mesh interconnection networks have been suggested in past by the placement of the extra links to the existing mesh topology. In this paper, we have searched for the optimal links that should place in the topology so as to reduce the average inter node distance of the resultant topology. This is a heuristic search problem which has the single objective that is to minimize the average inter node distance of the topology. The Improved Environmental Adaptation Method (IEAM) is one of the latest techniques based on phenotypic properties of genes, which prove to be fast in searching the optimal solution to the problem. The paper describes in detail the various operator of IEAM and compares its performance with the existing heuristic technique that is Genetic algorithm. The IEAM obviously proves to be better in finding the results. After finding the optimized topology the resultant is tested for the performance with existing variant of the topology like mesh, center concentrated mesh, T Mesh for performance and proves to give the improvement more than 2 times.

Efficient Communication Algorithms in Hexagonal Mesh Interconnection Networks

In this paper, we show that the hexagonal mesh networks developed in the early 1990s are a special case of the EJ networks that have been considered more recently. Using a node addressing scheme based on the EJ number system, we give a shortest path routing algorithm for hexagonal mesh networks. We also extend the known efficient one-to-all broadcasting algorithm on hexagonal mesh networks to algorithms for one-to-one personalized broadcasting, all-to-all broadcasting, and all-to-all personalized broadcasting algorithms. Their time complexity and optimality are analyzed.

An efficient placement and routing technique for fault-tolerant distributed embedded computing

This article presents an efficient technique for placement and routing of sensors/actuators and processing units in a grid network. The driver application that we present is a medical jacket, which requires an extremely high level of robustness and fault tolerance. The power consumption of such jacket is another key technological constraint. Our proposed interconnection network is a mesh of wires. A jacket made of fabric and wires would be susceptible to accidental damage via tears. By modeling the tears, we evaluate the probability of having failures on every segment of wires in our mesh interconnection network. Then, we study two problems of placement and routing in the sensor networks such that the fault tolerance is maximized while the power consumption is minimized. We develop efficient integer linear programming (ILP) formulations to address these problems and perform both placement and routing, simultaneously. This ensures that the solution is a lower bound for both problems. We evaluate the effectiveness of our proposed techniques on a variety of benchmarks.

A 5-GHz Mesh Interconnect for a Teraflops Processor

A multicore processor in 65-Nm technology with 80 single-precision, floatingpoint cores delivers performance in excess of a Teraflops while consuming less than 100 W. A 2D on-die mesh interconnection network operating at 5 GHz provides the high-performance communication fabric to connect the cores. The network delivers a bisection bandwidth of 2.56 Terabits per second and a per hop fall-through latency of 1 nanosecond.

An accurate performance model of fully adaptive routing in wormhole-switched two-dimensional mesh multicomputers

Numerous analytical performance models have been proposed for deterministic wormhole-routed mesh networks while only a single model, to our best knowledge, has been suggested for fully adaptive wormhole routing in mesh interconnection networks. This paper proposes a new and accurate analytical performance model for fully adaptive wormhole-routed mesh networks. Simulation results show that unlike the previously proposed model which is only accurate in light traffic loads, this model can be used for the performance analysis of almost all traffic loads.

Processor Allocationand Job Scheduling on 3D Mesh Interconnection Networks

Contiguous allocation of parallel jobs usually suffers from the degrading effects of fragmentation, because it requires that the allocated processors be contiguous and have the same topology as the network topology connecting these processors. This paper suggests two non-contiguous processor allocation strategies, referred to as Paging and Greedy-Available respectively, for the 3D mesh network and compares their performance using software simulation against the well-known contiguous First Fit strategy. The comparative evaluation is conducted for two job scheduling strategies, notably first-come-first-served (FCFS) and out-of-order (OO). The results reveal that our proposed non-contiguous strategies exhibit superior performance properties despite the added contention that results from non-contiguity. The results also reveal that the scheduling and allocation strategies both have substantial effect on the performance of contiguous and non-contiguous allocation in that the OO scheduling strategy leads to much better performance than its FCFS counterpart in the 3D mesh.

Characterization of spatial fault patterns in interconnection networks

Parallel computers, such as multiprocessors system-on-chip (Mp-SoCs), multicomputers and cluster computers, are consisting of hundreds or thousands multiple processing units and components (such as routers, channels and connectors) connected via some interconnection network that collectively may undergo high failure rates. Therefore, these systems are required to be equipped with fault-tolerant mechanisms to ensure that the system will keep running in a degraded mode. Normally, the faulty components are coalesced into fault regions, which are classified into two major categories: convex and concave regions. In this paper, we propose the first solution to calculate the probability of occurrences of common fault patterns in torus and mesh interconnection networks which includes both convex (∣-shaped, □-shaped) and concave (L-shaped, T-shaped, +-shaped, H-shaped) regions. These results play a key role when studying, particularly, the performance analysis of routing algorithms proposed for interconnection networks under faulty conditions.

Explanation of Performance Degradation in Turn Model

The Turn model routing algorithms for mesh interconnection network achieve partial adaptivity without any virtual channels. However, the routing performance measured by simulations is worse than with the simple deterministic routing algorithm. Authors have explained these results simply by uneven dynamic load through the network. However, this phenomenon has not been studied further. This paper investigates performance degradation with Turn model and drawbacks of partially adaptive routing in comparison with the deterministic routing, and it introduces some new concepts. Our simulations deal with individual channels and results are presented by 3D graphs, rather than by commonly used averages. An additional parameter--channel occupation, which is consistent with queuing theory commonly used in many proposed analytical models, is introduced. We also propose a new structure, the Channel Directions Dependency Graph (CDDG). It provides a new approach in analysis, helps in understanding of dynamic routing behaviour, and it can be generalized in other routing algorithms.

THE COMMUNICATION MACHINE

The Communication Machine brings to the multicomputer what vectorization brought to the uniprocessor. It provides the same tools to speed communication that have traditionally been used to speed computation; namely, the capability to program optimal communication algorithms on an architecture that can, to the extent possible, replicate their performance in terms of wall-clock time. In addition to the usual complement of logic and arithmetic units, each module contains a programmable communication unit that orchestrates traffic between the network and registers that communicate directly with comparable registers in neighboring modules. Communication tasks are performed out of these registers like computational tasks on a vector uniprocessor. The architecture is balanced in the sense that, on average, the speed of local and global memory is comparable. Theoretical performance is tabulated for both hypercube and mesh interconnection networks. The Communication Machine returns to the somewhat beleaguered, yet intuitive concept that the performance we ultimately seek must come from a truly massive number of processors.

TRIDIAGONAL SOLVERS WITH MULTIPLE RIGHT HAND SIDES ON k-DIMENSIONAL MESH AND TORUS INTERCONNECTION NETWORKS

We consider the problem of designing optimal and efficient algorithms for solving tridiagonal linear systems with multiple right-hand side vectors on k-dimensional mesh and torus interconnection networks. We derive asymptotic upper and lower bounds for these solvers using odd-even cyclic reduction. We present various important bounds on execution time including general lower bounds which are independent of initial data assignment, and lower bounds based on classifying assignments via the proportion of initial data assigned amongst processors. Finally, different algorithms are designed in order to achieve running times that are within a small constant factor of the lower bounds provided.

On the fault-tolerant embeddings of complete binary trees in the mesh interconnection networks

In this article, several schemes are proposed for embedding complete binary trees (CBT) into meshes. All of the proposed methods outperform those in the previous studies. First, a link congestion 1 embedding is achieved. Its expansion ratio is at the lowest level as we know now. Except for this superiority, it also provides another capability for fault tolerance to resist abnormal system faults, thus the embedding structure can be more guaranteed and the node utilization is raised further. Second, a link congestion 1 embedding with no-bending constraint is obtained. This scheme provides efficient CBT embedding for both the optical mesh and general mesh at the same time while keeping those good properties as the previous scheme. The last one is an optimal embedding which is applied to a 3D cubic mesh, where the node is almost fully utilized and its link congestion is 2.

Complexity Issues on Designing Tridiagonal Solvers on 2-Dimensional Mesh Interconnection Networks

We consider the problem of designing optimal and efficient algorithms for solving tridiagonal linear systems with multiple right-hand side vectors on two-dimensional mesh interconnection networks. We derive asymptotic upper and lower bounds for these solvers using odd-even cyclic reduction. We present various important lower bounds on execution time for solving these systems including general lower bounds which are independent of initial data assignment, and lower bounds based on classifications of initial data assignments which classify assignments via the proportion of initial data assigned amongst processors. Finally, different algorithms are designed in order to achieve running times that are within a small constant factor of the lower bounds provided.

Exploiting the capabilities of the interconnection network on Dawning-1000

On Dawning-1000, the two-dimension mesh interconnection network enables low-latency, high-bandwidth communication, however, these capabilities have not been realized because of the high processing overhead imposed by existing communication software. Active Messages provide an efficient communication mechanism with small overhead, which may expose the raw capabilities of the underlying hardware. In addition, one of the most promising techniques, user-level communication, is often used to improve the performance of the traditional protocols such as TCP and UDP, and is also adopted in implementing the novel abstractions like Active Messages. Thus a user-level Active Messages model is designed and implemented on Dawning-1000. Preliminary experiments show that the combination of Active Messages mechanism and user-level communication technique is quite efficient in reducing software overhead associated with sending and receiving messages, and in exploiting the capabilities of the interconnection network.

Comparisons between mesh and hierarchical ring networks for shared-memory multiprocessors

Communication performance comparisons, in terms of message latency, between mesh and hierarchical ring interconnection networks for shared-memory multiprocessors are developed. Traffic in the networks is assumed to consist of the short, fixed-length messages needed for remote-memory read/write operations and cache coherency control. Square-mesh networks with bidirectional links and no end-around connections are compared to two- and three-level hierarchical rings. Wormhole routing is used in the meshes, with messages consisting of / flits, with each flit containing b bits. In the ring networks, each ring segment can contain a complete message of f × b bits. Meshes and three-level rings provide comparable delays for system sizes of up to 200 or 300 processor clusters. The delay comparisons are valid only for the lightly loaded traffic case in which contention and blocking are low. This is the situation in practical shared-memory multiprocessor systems with a low cache miss rate and a high physical locality of reference in the global address space.

Mapping finite element grids onto parallel multicomputers using a self-organising map

LSOM (load-balancing self-organising map), a neural network based on Kohonen's self-organising map, is proposed for the problem of mapping finite element method (FEM) grids to distributed memory parallel computers with mesh interconnection networks. The rough global ordering produced by LSOM is combined with the local refinement Kernighan-Lin algorithm (LSOM-KL) to obtain the solution. LSOM-KL achieved a load imbalance of less than 0.1%, and a low number of hops, comparable to results obtained with commonly used recursive bisection methods.

A survey and comparison of wormhole routing techniques in a mesh networks

The growing demand for high processing power in various scientific and engineering applications has made multiprocessing architectures increasingly popular. These multiprocessing systems consist of processing elements or nodes which are connected together by interconnection networks in various topologies. One of the design methodologies used for parallel machines has fed to the development of distributed memory message-passing concurrent computers, commonly known as multicomputers. They consist of many processing nodes that interact by sending messages (containing both data and synchronization information) over a communication link, between nodes. Thus, efficient communication in multicomputers is one of the important research areas in parallel computing today, and it depends on the underlying scheme for routing. For this reason it is essential to know which routing techniques are suitable and practical. Although an extremely wide number of routing algorithms have been proposed and implemented in hardware and software, it is difficult for the designer of a multicomputer to choose the best routing algorithm given a particular architectural configuration. In an attempt to overcome this difficulty, we present a survey and comparison of wormhole routing techniques in mesh interconnection networks. The mesh topology is important because of its scalability. Moreover, it has already been implemented in many commercial multicomputers.

On the Scalability of 2-D Discrete Wavelet Transform Algorithms

The ability of a parallel algorithm to make efficient use of increasing computational resources is known as its scalability. In this paper, we develop four parallel algorithms for the 2-dimensional Discrete Wavelet Transform algorithm (2-D DWT), and derive their scalability properties on Mesh and Hypercube interconnection networks. We consider two versions of the 2-D DWT algorithm, known as the Standard (S) and Non-standard (NS) forms, mapped onto P processors under two data partitioning schemes, namely checkerboard (CP) and stripped (SP) partitioning. The two checkerboard partitioned algorithms on the cut-through-routed (CT-routed) Mesh are scalable as M^{2}=\Omega(P\log P) (Non-standard form, NS-CP), and as M^{2}=\Omega(P\log^{2}P) (Standard form, S-CP); while on the store-and-forward-routed (SF-routed) Mesh and Hypercube they are scalable as M^2=\Omega(P^{\frac{3}{3-\gamma}}) (NS-CP), and as M^2=\Omega(P^{\frac{2}{2-\gamma}}) (S-CP), respectively, where M^{2} is the number of elements in the input matrix, and \gamma\in (0,1) is a parameter relating M to the number of desired octaves J as J=\lceil \gamma \log M \rceil. On the CT-routed Hypercube, scalability of the NS-form algorithms shows similar behavior as on the CT-routed Mesh. The Standard form algorithm with stripped partitioning (S-SP) is scalable on the CT-routed Hypercube as M^{2}=\Omega(P^{2}), and it is unscalable on the CT-routed Mesh. Although asymptotically the stripped partitioned algorithm S-SP on the CT-routed Hypercube would appear to be inferior to its checkerboard counterpart S-CP, detailed analysis based on the proportionality constants of the isoefficiency function shows that S-SP is actually more efficient than S-CP over a realistic range of machine and problem sizes. A milder form of this result holds on the CT- and SF-routed Mesh, where S-SP would, asymptotically, appear to be altogether unscalable.