Memristor Crossbar Research Articles

Fast and Accurate Sparse Coding of Visual Stimuli With a Simple, Ultralow-Energy Spiking Architecture.

Memristive crossbars have become a popular means for realizing unsupervised and supervised learning techniques. In previous neuromorphic architectures with leaky integrate-and-fire neurons, the crossbar itself has been separated from the neuron capacitors to preserve mathematical rigor. In this paper, we sought to design a simplified sparse coding circuit without this restriction, resulting in a fast circuit that approximated a sparse coding operation at a minimal loss in accuracy. We showed that connecting the neurons directly to the crossbar resulted in a more energy-efficient sparse coding architecture and alleviated the need to prenormalize receptive fields. This paper provides derivations for the design of such a network, named the simple spiking locally competitive algorithm, as well as CMOS designs and results on the CIFAR and MNIST data sets. Compared to a nonspiking, nonapproximate model which scored 33% on CIFAR-10 with a single-layer classifier, this hardware scored 32% accuracy. When used with a state-of-the-art deep learning classifier, the nonspiking model achieved 82% and our simplified, spiking model achieved 80% while compressing the input data by 92%. Compared to a previously proposed spiking model, our proposed hardware consumed 99% less energy to do the same work at 21 × the throughput. Accuracy held out with online learning to a write variance of 3%, suitable for the often reported 4-bit resolution required for neuromorphic algorithms, with offline learning to a write variance of 27%, and with read variance to 40%. The proposed architecture's excellent accuracy, throughput, and significantly lower energy usage demonstrate the utility of our innovations.

Filament formation in lithium niobate memristors supports neuromorphic programming capability

Memristor crossbars are capable of implementing learning algorithms in a much more energy and area efficient manner compared to traditional systems. However, the programmable nature of memristor crossbars must first be explored on a smaller scale to see which memristor device structures are most suitable for applications in reconfigurable computing. In this paper, we demonstrate the programmability of memristor devices with filamentary switching based on LiNbO3, a new resistive switching oxide. We show that a range of resistance values can be set within these memristor devices using a pulse train for programming. We also show that a neuromorphic crossbar containing eight memristors was capable of correctly implementing an OR function. This work demonstrates that lithium niobate memristors are strong candidates for use in neuromorphic computing.

Self‐biasing memristor crossbar used for string matching and ternary content‐addressable memory implementation

A memristor crossbar-based technique for highly parallel string matching is presented. An input string can be simultaneously compared against a bank of stored words, each having a different length, due to the self-biasing nature of the crossbar circuit. This string matching system essentially acts as a ternary content-addressable memory (TCAM). Owing to the high-density nature of nanoscale memristor crossbars, this system can provide a significant area reduction when compared alternative TCAM designs while remaining competitive in terms of timing and energy.

A multiply-add engine with monolithically integrated 3D memristor crossbar/CMOS hybrid circuit

Silicon (Si) based complementary metal-oxide semiconductor (CMOS) technology has been the driving force of the information-technology revolution. However, scaling of CMOS technology as per Moore’s law has reached a serious bottleneck. Among the emerging technologies memristive devices can be promising for both memory as well as computing applications. Hybrid CMOS/memristor circuits with CMOL (CMOS + “Molecular”) architecture have been proposed to combine the extremely high density of the memristive devices with the robustness of CMOS technology, leading to terabit-scale memory and extremely efficient computing paradigm. In this work, we demonstrate a hybrid 3D CMOL circuit with 2 layers of memristive crossbars monolithically integrated on a pre-fabricated CMOS substrate. The integrated crossbars can be fully operated through the underlying CMOS circuitry. The memristive devices in both layers exhibit analog switching behavior with controlled tunability and stable multi-level operation. We perform dot-product operations with the 2D and 3D memristive crossbars to demonstrate the applicability of such 3D CMOL hybrid circuits as a multiply-add engine. To the best of our knowledge this is the first demonstration of a functional 3D CMOL hybrid circuit.

Coexistence of two types of metal filaments in oxide memristors

One generally considers the conducting filament in ZnO-based valence change memristors (VCMs) as an aggregation of oxygen vacancies. Recently, the transmission electron microscopy observation showed the filament is composed of a Zn-dominated ZnOx. In this study, careful analysis of the temperature dependence of the ON state resistance demonstrates that the formation/rupture of a Zn filament is responsible for the resistive switching in ZnO VCMs. Cu/ZnO/Pt memristive devices can be operated in both VCM and ECM (electrochemical metallization memristor) modes by forming different metal filaments including Cu, Zn and a coexistence of these two filaments. The device operation can be reversibly switched between ECM and VCM modes. The dual mode operation capability of Cu/ZnO/Pt provides a wide choice of select devices for constructing memristive crossbar architectures.

3-D Memristor Crossbars for Analog and Neuromorphic Computing Applications

We report a monolithically integrated 3-D metal-oxide memristor crossbar circuit suitable for analog, and in particular, neuromorphic computing applications. The demonstrated crossbar is based on Pt/Al2O3/TiO2– x /TiN/Pt memristors and consists of a stack of two passive $10\times10$ crossbars with shared middle electrodes. The fabrication process has a low, less than 175 °C, temperature budget and includes a planarization step performed before the deposition of the second crossbar layer. These features greatly improve yield and uniformity of the crosspoint devices and allows for utilizing such a fabrication process for integration with CMOS circuits as well as for stacking of multiple crossbar layers. Furthermore, the integrated crosspoint memristors are optimized for analog computing applications allowing successful forming and switching of all 200 devices in the demonstrated crossbar circuit, and, most importantly, precise tuning of the devices’ conductance values within the dynamic range of operation. We believe that the demonstrated work is an important milestone toward the implementation of analog artificial neural networks, specifically, those based on 3-D CMOL circuits.

Experimental demonstration of sequence recognition of serial memristors

The sequence recognition is very essential in mimicking brain’s neocortical function because most of input patterns to brain’s neocortex are dynamically changing over time, not static regardless of time. In this paper, we experimentally demonstrate the sequence recognition for various input sequences using serial memristors, for the first time. In this experiment, the serial memristors are used, which were fabricated with carbon fiber and aluminum film on glass substrate. To verify the sequence recognition, we store the following 3 sequences in the fabricated serial memristors, which are ‘A’→‘B’→‘C’, ‘B’→‘A’→‘C’, and ‘C’→‘B’→‘A’, respectively. By performing this experiment, it is verified the serial memristors are changed to Low Resistance State only when the input sequence matches the stored one. When the input sequence is different from the stored one, the serial memristors remain unchanged. The simple voltage comparator can be used to sense the output voltage to indicate whether the sequence matching happens or not. This experimental demonstration can be very useful to realize memristor crossbars which can process the temporal and sequential patterns in future.

Neuromorphic coprocessor prototype based on mixed metal oxide memristors

This paper presents developments in the field of nanoscale neuromorphic electronics. The developed device represents the integration of the memristive crossbar with commercially available electronics. The crossbar was deposited by PVD assisted by electron-beam lithography. The 20 nm mixed titanium-aluminium oxide film was used as a memristive layer in the crossbar. The device was developed as a complex consisting of two microcontrollers bound by I2C interface and connected to a PC via USB. The software consists of the neural network part implemented on microcontrollers and the control part installed on PC.

Realization of Functional Complete Stateful Boolean Logic in Memristive Crossbar.

Nonvolatile stateful logic computing in memristors is a promising paradigm with which to realize the unity of information storage and processing in the same physical location that has shown great feasibility for breaking the von Neumann bottleneck in traditional computing architecture. How to reduce the computational complexity of memristor-based logic functions is a matter of concern. Here, based on a general logic expression, we proposed a method to implement the arbitrary logic of complete 16 Boolean logic in two steps with one memristor in the crossbar architecture. A representative functional complete NAND logic is successfully experimentally demonstrated in the filamentary Ag-AgGeTe-Ta memristors to prove the validity of our method. We believe our work may promote the development of the revolutionary logic in memory architectures.

Sequential Memristor Crossbar for Neuromorphic Pattern Recognition

Most of human's intelligent behaviors such as inference, prediction, anticipation, etc. are based on the processing of sequential data from human's sensory systems. Thus, a sequential memory that can process sequential information is very essential to mimic brain's intelligent behaviors. In this paper, we propose a new sequential memristor crossbar which is regarded as the first memristor circuit that copes with the sequential data. The new crossbar is composed of two layers which are the base layer and the sequential one, respectively. The base layer can recognize only static items one by one. The sequential layer can detect the serial order of items and find the best match with the detected sequence among many reference sequences stored in the memristor array. The new crossbar can recognize the tested sequences of items as well as 88.6% on average for the memristance variation of 0%. The variation tolerance is also tested from 0-% variation to 20-% variation in the proposed sequential crossbar.

Experimental study of LiNbO3 memristors for use in neuromorphic computing

This paper describes the fabrication and characterization of Lithium Niobate (LiNbO3) memristor devices that have the ability to be tuned to a specific resistance state within a continuous resistance range. This is essential for programming neuromorphic systems based on memristor crossbars in order to achieve best deep learning capability. The memristor devices were formed using a 42nm layer of LiNbO3 sandwiched between two metal electrodes. I-V curves demonstrate a typical and repeatable memristor characteristic from −3V to 3V. Such devices have a continuous resistance range that has a maximum to minimum resistance ratio of about 100, and the ability to program intermediate resistance states. The results also show the ability to read the device symmetrically with a positive or negative voltage, and strong data retention after the programming phase.

Memristive Crossbar Memory Lifetime Evaluation and Reconfiguration Strategies

Among the emerging technologies and devices for highly scalable and low power memory architectures, memristors are considered as one of the most favorable alternatives for next generation memory technologies. They are attracting great attention recently, due to their many appealing characteristics such as non-volatility and compatibility with CMOS fabrication process. But beside all memristor advantages, their drawbacks including manufacturing process variability and limited read/write endurance, could risk their future utilization. This paper will evaluate the impact of reliability concerns in lifetime of memristive crossbars and will present the design basis of two proposed reconfiguration approaches in memristive crossbar-based memories, in order to extend the system lifetime by utilizing available resources in an intense way and without need of failure recovery. It is observed that the adaptive reconfiguring approach can improve the crossbar reliability and extend its lifetime up to 65 percent in comparison with non-adaptive reconfiguration strategy.

Reconfigurable neuromorphic crossbars based on titanium oxide memristors

Memristor crossbars are capable of implementing learning algorithms in a much more energy- and area-efficient manner compared with traditional systems. However, the programmable nature of memristor crossbars must first be explored on a smaller scale to see if physical devices are suitable for applications of reconfigurable computing. The reconfigurability of these devices through small scale memristor crossbar implementations is demonstrated. It is shown that a crossbar containing eight memristors is capable of learning several different two-input Boolean logic functions. A strong foundation is provided to build on demonstrating that physical memristor crossbars can be programmed as linear classifiers.

Efficient March test algorithm for 1T1R cross‐bar with complete fault coverage

As an attractive option of future non-volatile memories, resistive RAM (RRAM) has attracted more attentions. Among RRAM architectures, one transistor one memristor (1T1R) cross-bar is the most fledged one. A March C*-1T1R algorithm is proposed for 1T1R cross-bar. The pass–fail fault dictionary of the proposed March test algorithm is analysed. Analytical results show that the proposed test algorithm can detect all the modelled faults caused by the parametric variation of memristors, transistors and their interconnecting wires with a little test time overhead compared with previous methods.

Memristor-Based Volistor Gates Compute Logic with Low Power Consumption

We introduce a novel volistor logic gate which uses voltage as input and resistance as output. Volistors rely on the diode-like behavior of rectifying memristors. We show how to realize the first logic level, counted from the input, of any Boolean function with volistor gates in a memristive crossbar network. Unlike stateful logic, there is no need to store the inputs as resistances, and computation is performed directly. The fan-in and fan-out of volistor gates are large and different from traditional memristor circuits. Compared to solely memristive stateful logic, a combination of volistors and stateful inhibition gates can significantly reduce the number of operations required to calculate arbitrary multi-output Boolean functions. The power consumption of volistor logic is computed and compared with the power consumption of stateful logic using the simulation results obtained by LTspice—when implemented in a 1 × 8 or an 8 × 1 crosspoint array, volistors consume significantly less power.

Transient response characteristic of memristor circuits and biological-like current spikes

Although memristors are mostly considered as a strong candidate for physical realization of synapses in neuromorphic systems, implementation of biologically plausible neurons with memristors creates a great potential to integrate both synapses and neurons on memristor fabrics, such as memristor crossbars. Here we present a discussion regarding transient current response of memristors, and the way we can reproduce biological-like current spikes with very basic memristor circuits. In general, memristor shows a spike-like current response to step changes of the input voltage, which can be used in voltage-excited neuromorphic systems. Accordingly, the properties of current response of single and multiple memristor circuits are investigated in this work. The factors which can affect the shape of the spike-like current response are discussed. Furthermore, it is shown that current spike generated by serially connected memristor and capacitor can exhibit spikes with variety of signaling characteristics. We also discuss about the spike train generated using memristor excited by voltage square wave input. Finally, using memristor and capacitor, a spike-forming circuit is presented in which voltage square wave input is converted to biological-like current spike train.

Single-Readout High-Density Memristor Crossbar.

High-density memristor-crossbar architecture is a very promising technology for future computing systems. The simplicity of the gateless-crossbar structure is both its principal advantage and the source of undesired sneak-paths of current. This parasitic current could consume an enormous amount of energy and ruin the readout process. We introduce new adaptive-threshold readout techniques that utilize the locality and hierarchy properties of the computer-memory system to address the sneak-paths problem. The proposed methods require a single memory access per pixel for an array readout. Besides, the memristive crossbar consumes an order of magnitude less power than state-of-the-art readout techniques.

Model for maximum crossbar size based on input driver impedance

Memristor crossbars are capable of implementing learning algorithms in a much more energy and area efficient manner compared with traditional systems. However, no results have been published that describe how large a neuromorphic memristor crossbar could theoretically become before it is inoperable. Furthermore, the input drivers to the crossbar are not typically studied in these neuromorphic system simulations. Presented is a model for determining the maximum memristor crossbar size relative to the input driver impedance. This is a powerful tool that can be used by a memristor system designers to quickly determine the trade-offs between maximum crossbar size, resistance, energy, and write speed. This information can then be used to determine how many independent crossbar circuits are required for a given neuromorphic application.

Hybrid crossbar architecture for a memristor based cache

This paper describes a new memristor crossbar architecture that is proposed for use in a high density cache design. This design has less than 10% of the write energy consumption than a simple memristor crossbar. Also, it has up to 3 times the bit density of an STT-MRAM system and up to 11 times the bit density of an SRAM architecture. The proposed architecture is analyzed using a detailed SPICE analysis that accounts for the resistance of the wires in the memristor structure. Additionally, the memristor model used in this work has been matched to specific device characterization data to provide accurate results in terms of energy, area, and timing. The proposed memory system was analyzed by modeling two different devices that vary in resistance range and switching time. This system does not require that the memristor devices have inherent diode effects which limit alternate current paths. Therefore this system is capable of utilizing a much broader class of devices.An architectural analysis has also been completed that shows how the memory system may perform as a cache memory. A hybrid cache structure was used to alleviate the long write latencies of memristor devices. This approach consisted of the tag array being made of SRAM cells while the data array was made of the memristor circuit proposed. This hybrid scheme allows multiple reads and writes to concurrently access different sub-arrays within a cache. The performance of these novel memristor based caches was compared to SRAM and STT-MRAM based caches through detailed simulations. The results show that the memristor caches are denser and allow better performance along with lower system power when compared to the STT-MRAM and SRAM caches.

A Low-Power Variation-Aware Adaptive Write Scheme for Access-Transistor-Free Memristive Memory

Recent advances in access-transistor-free memristive crossbars have demonstrated the potential of memristor arrays as high-density and ultra-low-power memory. However, with considerable variations in the write-time characteristics of individual memristors, conventional fixed-pulse write schemes cannot guarantee reliable completion of the write operations and waste significant amount of energy. We propose an adaptive write scheme that adaptively adjusts the write pulses to address such variations in memristive arrays, resulting in 7×--11× average energy saving in our case studies. Our scheme embeds an online monitor to detect the completion of a write operation and takes into account the parasitic effect of line-shared devices in access-transistor-free crossbars. This feature also helps shorten the test time of memory march algorithms by eliminating the need of a verifying read right after a write, which is commonly employed in the test sequences of march algorithms.