Memristor Crossbar Array Research Articles

Memristive devices based on Cu-doped NbOx films with large self-rectifying ratio

To address the problem of sneak currents in large-scale crossbar arrays without extra access devices like transistors or selectors, memristive devices with self-rectifying characteristics are highly desired. Herein, memristive devices of Pt/Cu-NbOx/TiN with a large rectification ratio (~1.43 × 105 at ±2 V) are realized in Cu-doped NbOx thin films. The large rectification ratio is due to the large Schottky barrier height at the Pt/Cu-doped NbOx interface, which is closely related to the changes of the band structure through Cu doping. More importantly, the devices can facilitate the fabrication of memristive crossbar arrays whose scale can reach maximal 486 × 486 (~230 kbits) with 10% read margin. This work clearly proves the feasibility of the self-rectifying memristive devices for bio-inspired computing.

Scalable massively parallel computing using continuous-time data representation in nanoscale crossbar array.

The growth of connected intelligent devices in the Internet of Things has created a pressing need for real-time processing and understanding of large volumes of analogue data. The difficulty in boosting the computing speed renders digital computing unable to meet the demand for processing analogue information that is intrinsically continuous in magnitude and time. By utilizing a continuous data representation in a nanoscale crossbar array, parallel computing can be implemented for the direct processing of analogue information in real time. Here, we propose a scalable massively parallel computing scheme by exploiting a continuous-time data representation and frequency multiplexing in a nanoscale crossbar array. This computing scheme enables the parallel reading of stored data and the one-shot operation of matrix-matrix multiplications in the crossbar array. Furthermore, we achieve the one-shot recognition of 16 letter images based on two physically interconnected crossbar arrays and demonstrate that the processing and modulation of analogue information can be simultaneously performed in a memristive crossbar array.

Signal Integrity Modeling and Analysis of Large-Scale Memristor Crossbar Array in a High-Speed Neuromorphic System for Deep Neural Network

In this article, we modeled, analyzed, and evaluated a large-scale memristor crossbar array in a neuromorphic system for a deep neural network (DNN) considering signal integrity (SI). Since hardware-based DNN using a memristor crossbar array operates in an analog way, it has serious reliability problems caused by interconnects, driver, and nonlinear memory cells. The interconnects including an on-chip signal and power/ground (P/G) mesh were modeled as circuit parameters from a full 3-D-electromagnetic (EM) simulation. The memristor was electrically modeled including its nonlinear characteristics. These models were configured into a 512 ×512 memristor crossbar array with drivers and peripheral circuits for the implementation of DNN. Then, we analyzed the component-level SI and nonlinearity for the interconnects and memristors, and the system level for the total array configuration. Finally, the regression of DNN in the memristor crossbar array was evaluated for verification of the analysis. All the analyzed SI and nonlinearity effects from the interconnects, memristor, and array configuration affected the regression. As the input voltage level decreased, the effect of the SI effect on accuracy became more dominant than that of the nonlinearity of the memristor effect. In terms of SI, it was verified that there is a tradeoff relationship between IR drop and crosstalk according to the interconnects' size. Finally, the accuracy and power consumption were verified according to the array configuration in the system level as an important issue of the memristor crossbar array. Through the overall process, it was possible to analyze how the SI and nonlinearity effects affect the computational results in the neuromorphic system.

Logics execution in a multi-layers memristor array

Memristor stateful logic based on a two-dimensional (2D) memristor crossbar array (MCBA) has been proved to be an effective approach to break the von Neumann bottleneck. But the three-dimensional (3D) array which has an inherent high storage density is less investigated in logic computation field. In this work, we implemented the whole linearly separable binary Boolean logic functions completely by using the stateful logic circuits configured in a multi-layer memristor crossbar array. This circuit primitive can execute multi-gates parallelly inside layer or the interlayer of 3D MCBA. This work provided a significant reference for the achievement of real processing in memory (PiM) in a high-density array.

Memristive Crossbar Arrays for Storage and Computing Applications

The emergence of memristors with potential applications in data storage and artificial intelligence has attracted wide attentions. Memristors are assembled in crossbar arrays with data bits encoded by the resistance of individual cells. Despite the proposed high density and excellent scalability, the sneak‐path current causing cross interference impedes their practical applications. Therefore, developing novel architectures to mitigate sneak‐path current and improve efficiency, reliability, and stability may benefit next‐generation storage‐class memory (SCM). Moreover, conventional digital computers face the von‐Neumann bottleneck and the slowdown of transistors’ scaling, imposing a big challenge to hardware artificial intelligence. Memristive crossbar features colocation of memory and processing units, as well as superior scalability, making it a promising candidate for hardware accelerating machine learning and neuromorphic computing. Herein, first, crossbar architecture is introduced. Then, for storage, the origin of sneak‐path current is reviewed and techniques to mitigate this issue from the angle of materials and circuits are discussed. Computing wise, the applications of memristive crossbars in both machine learning and neuromorphic computing are surveyed, focusing on the structure of unit cells, the network topology, and the learning types. Finally, a perspective on future engineering and applications of memristive crossbars is discussed.

Bio‐Inspired Artificial Vision and Neuromorphic Image Processing Devices

AbstractRemarkable technological developments for efficient image recognition (i.e., image acquisition and image data processing) have been reported in the past decade. Such advances in imaging and image processing technologies have driven significant progress in mobile electronics and machine vision applications. In particular, for image acquisition devices, two types of natural eyes (i.e., chambered and compound eyes) have inspired the development of novel multifunctional imaging devices with unique optical geometries. For image data processing devices, novel computing devices based on memristor crossbar arrays, such as electronic synapses, have been developed. More recently, the integration of imaging and image processing devices in a single unit further enhances the system‐level efficiency. Herein, such recent advances in the bio‐inspired artificial vision and neuromorphic image processing devices, aimed at providing efficient image recognition, are reviewed. First, various imaging devices inspired by the structural and functional features of natural eyes are introduced. Second, artificial synapses and their operation principles are thoroughly discussed. Third, the neuromorphic vision sensor that integrates the imaging and image processing devices is reviewed. Finally, a brief summary and future outlook are presented.

Neural Networks: Low‐Power Self‐Rectifying Memristive Artificial Neural Network for Near Internet‐of‐Things Sensor Computing (Adv. Electron. Mater. 6/2021)

In article 2100050, Byung Joon Choi and co-workers report the viability of self-rectifying memristive artificial neural networks as near IoT-sensor data processors to reduce the latency and energy consumption from transferring data between the sensor and the cloud server. The low-power operational memristor crossbar arrays and their image processing ability present an advantage in near IoT sensor computing.

3-bit multilevel operation with accurate programming scheme in TiO x /Al2O3 memristor crossbar array for quantized neuromorphic system

As interest in artificial intelligence (AI) and relevant hardware technologies has been developed rapidly, algorithms and network structures have become significantly complicated, causing serious power consumption issues because an enormous amount of computation is required. Neuromorphic computing, a hardware AI technology with memory devices, has emerged to solve this problem. For this application, multilevel operations of synaptic devices are important to imitate floating point weight values in software AI technologies. Furthermore, weight transfer methods to desired weight targets must be arranged for off-chip training. From this point of view, we fabricate 32 × 32 memristor crossbar array and verify the 3-bit multilevel operations. The programming accuracy is verified for 3-bit quantized levels by applying a reset-voltage-control programming scheme to the fabricated TiO x /Al2O3-based memristor array. After that, a synapse composed of two differential memristors and a fully-connected neural network for modified national institute of standards and technology (MNIST) pattern recognition are constructed. The trained weights are post-training quantized in consideration of the 3-bit characteristics of the memristor. Finally, the effect of programming error on classification accuracy is verified based on the measured data, and we obtained 98.12% classification accuracy for MNIST data with the programming accuracy of 1.79% root-mean-square-error. These results imply that the proposed reset-voltage-control programming scheme can be utilized for a precise tuning, and expected to contribute for the development of a neuromorphic system capable of highly precise weight transfer.

Hybrid Memristor–CMOS Implementation of Combinational Logic Based on X-MRL

A great deal of effort has recently been devoted to extending the usage of memristor technology from memory to computing. Memristor-based logic design is an emerging concept that targets efficient computing systems. Several logic families have evolved, each with different attributes. Memristor Ratioed Logic (MRL) has been recently introduced as a hybrid memristor–CMOS logic family. MRL requires an efficient design strategy that takes into consideration the implementation phase. This paper presents a novel MRL-based crossbar design: X-MRL. The proposed structure combines the density and scalability attributes of memristive crossbar arrays and the opportunity of their implementation at the top of CMOS layer. The evaluation of the proposed approach is performed through the design of an X-MRL-based full adder. The design is presented with its layout and corresponding simulation results using the Cadence Virtuoso toolset and CMOS 65nm process. The comparison with a pure CMOS implementation is promising in terms of the area, as our approach exhibits a 44.79% area reduction. Moreover, the combined Energy.Delay metric demonstrates a significant improvement (between ×5.7 and ×31) with respect to the available literature.

Magnetoresistive Circuits and Systems: Embedded Non-Volatile Memory to Crossbar Arrays

This overview article describes Magnetoresistive Random Access Memory (MRAM) from a circuits and systems perspective. We discuss various tradeoffs and design challenges of MRAM in three broad application areas: 1) embedded non-volatile memory (eNVMs), 2) crossbar-based analog in-memory computing, and 3) stochastic computing. Certain MRAM characteristics, such as high retention, high endurance and fast read and write operations, make them ideal for replacing the standard CMOS memories for last-level cache applications with future scaling. However, various tradeoffs in power, performance and area pose conflicting requirements on MRAM design. We explore these challenges and various circuit techniques that have been developed to mitigate them. Further, we present various requirements of memristive crossbar arrays for accelerating matrix-vector-multiplication (MVM) operations in light of MRAM devices, and highlight various challenges, design considerations, and applicability of MRAM as crossbar arrays. Finally, we will elaborate on how inherent stochasticity of MRAM devices can be leveraged for implementing energy-efficient true random number generators (TRNGs) and stochastic units for performing certain tasks, such as developing fast solvers for combinatorial optimization, and stochastic neural networks.

Low‐Power Self‐Rectifying Memristive Artificial Neural Network for Near Internet‐of‐Things Sensor Computing

AbstractFrequent data transfers between Internet‐of‐Things (IoT) sensors and cloud servers consume energy and lead to latency—a bottleneck for ubiquitous computing. To reduce the need for such enormous data transfers, the combined function of IoT sensors and near‐sensor artificial neural networks can process data properly before they are transferred to cloud servers. Herein, energy‐efficient memristor crossbar arrays are demonstrated for image recognition tasks that are potentially adopted for IoT sensors. The adoption of the selector‐free memristor device with a self‐rectifying function allows for simple stacking of metal–dielectric–metal layer, thus significantly simplifying the fabrication process while achieving low‐current operation (<10 µA in microdevice). Area‐dependent resistive switching characteristics and the incorporation of interface effects reveal the role of the switching and rectifying phenomena in such devices. Finally, the Modified National Institute of Standards and Technology pattern recognition task is demonstrated with 32 × 32 memristor crossbar arrays combining a SPICE simulation. Therefore, it is expected that self‐rectifying memristor arrays can pave the way for the development of more intelligent IoT sensors.

Self-assembling crystalline peptide microrod for neuromorphic function implementation

Self-assembling crystalline peptide microrod for neuromorphic function implementation

Memristive Quantized Neural Networks: A Novel Approach to Accelerate Deep Learning On-Chip.

Existing deep neural networks (DNNs) are computationally expensive and memory intensive, which hinder their further deployment in novel nanoscale devices and applications with lower memory resources or strict latency requirements. In this paper, a novel approach to accelerate on-chip learning systems using memristive quantized neural networks (M-QNNs) is presented. A real problem of multilevel memristive synaptic weights due to device-to-device (D2D) and cycle-to-cycle (C2C) variations is considered. Different levels of Gaussian noise are added to the memristive model during each adjustment. Another method of using memristors with binary states to build M-QNNs is presented, which suffers from fewer D2D and C2C variations compared with using multilevel memristors. Furthermore, methods of solving the sneak path issues in the memristive crossbar arrays are proposed. The M-QNN approach is evaluated on two image classification datasets, that is, ten-digit number and handwritten images of mixed National Institute of Standards and Technology (MNIST). In addition, input images with different levels of zero-mean Gaussian noise are tested to verify the robustness of the proposed method. Another highlight of the proposed method is that it can significantly reduce computational time and memory during the process of image recognition.

Quantized Convolutional Neural Network Implementation on a Parallel-Connected Memristor Crossbar Array for Edge AI Platforms.

There are many challenges in the hardware implementation of a neural network using nanoscale memristor crossbar arrays where the use of analog cells is concerned. Multi-state or analog cells introduce more stringent noise margins, which are difficult to adhere to in light of variability. We propose a potential solution using a 1-bit memristor that stores binary values "0" or "1" with their memristive states, denoted as a high-resistance state (HRS) and a low-resistance state (LRS). In addition, we propose a new architecture consisting of 4-parallel 1-bit memristors at each crosspoint on the array. The four 1-bit memristors connected in parallel represent 5 decimal values according to the number of activated memristors. This is then mapped to a synaptic weight, which corresponds to the state of an artificial neuron in a neural network. We implement a convolutional neural network (CNN) model on a framework (tensorflow) using an equivalent quantized weight mapping model that demonstrates learning results almost identical to a high-precision CNN model. This radix-5 CNN is mapped to hardware on the proposed parallel-connected memristor crossbar array. Also, we propose a method for negative weight representation on a memristor crossbar array. Then, we verify the CNN hardware on an edge-AI (e-AI) platform, developed on a field-programmable gate array (FPGA). In this e-AI platform, we represent five weights per crosspoint using CLB logics. We test the learning results of the CNN hardware using an e-AI platform with a dataset consisting of 4×4 images in three classes. We verify the functionality of our radix-5 CNN implementation showing comparable classification accuracy to high-precision use cases, with reduction of the area of the memristor crossbar array by half, all verified on a FPGA. Implementing the CNN model on the FPGA board can contribute to the practical use of edge-AI.

Nano-Crossbar Weighted Memristor-Based Convolution Neural Network Architecture for High-Performance Artificial Intelligence Applications.

Nano memristor crossbar arrays, which can represent analog signals with smaller silicon areas, are popularly used to describe the node weights of the neural networks. The crossbar arrays provide high computational efficiency, as they can perform additions and multiplications at the same time at a cross-point. In this study, we propose a new approach for the memristor crossbar array architecture consisting of multi-weight nano memristors on each cross-point. As the proposed architecture can represent multiple integer-valued weights, it can enhance the precision of the weight coefficients in comparison with the existing memristor-based neural networks. This study presents a Radix-11 nano memristor crossbar array with weighted memristors; it validates the operations of the circuits, which use the arrays through circuit-level simulation. With the proposed Radix-11 approach, it is possible to represent eleven integer-valued weights. In addition, this study presents a neural network designed using the proposed Radix-11 weights, as an example of high-performance AI applications. The neural network implements a speech-keyword detection algorithm, and it was designed on a TensorFlow platform. The implemented keyword detection algorithm can recognize 35 Korean words with an inferencing accuracy of 95.45%, reducing the inferencing accuracy only by 2% when compared to the 97.53% accuracy of the real-valued weight case.

In Situ Learning in Hardware Compatible Multilayer Memristive Spiking Neural Network

As one of the most promising methods in the next generation of neuromorphic systems, memristor-based spiking neural networks (SNNs) show great advantages in terms of power efficiency, integration density, and biological plausibility. However, because of the nondifferentiability of discrete spikes, it is difficult to train SNNs with gradient descent and error backpropagation online. In this article, we propose an improved training algorithm for multilayer memristive SNN (MSNN) with three methods spontaneously, supporting <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">in situ</i> learning in hardware: 1) temporal order encoding is applied to generate different pulse trains in neurons; 2) a simplified homeostasis is realized by the activation state and refractory period to regulate hidden neurons spontaneously; and 3) spiking-timing-dependent plasticity (STDP) in memristive synapses is adopted to update weights <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">in situ</i> . Correspondingly, we provide a circuitry example and verify it in LTSPICE. Then the MSNN is benchmarked with the MNIST data set and analyzed with visualization methods, showing better recognition accuracy (95.15%) than existing SNNs with comparable scales and bio-inspired learning rules. We also consider some nonideal effects in memristor crossbar array and peripheral circuits. Evaluation results show that the proposed MSNN is robust to finite resolution, circuit noise and writing noise; and larger network scale will help the MSNN alleviate the negative impacts of other nonideal factors, including yield and device-to-device variation. Moreover, the energy efficiency of a MSNN system is estimated to achieve 7.6TOPS/W, showing great potential in low-power applications.

Multiply accumulate operations in memristor crossbar arrays for analog computing

Memristors are now becoming a prominent candidate to serve as the building blocks of non-von Neumann in-memory computing architectures. By mapping analog numerical matrices into memristor crossbar arrays, efficient multiply accumulate operations can be performed in a massively parallel fashion using the physics mechanisms of Ohm’s law and Kirchhoff’s law. In this brief review, we present the recent progress in two niche applications: neural network accelerators and numerical computing units, mainly focusing on the advances in hardware demonstrations. The former one is regarded as soft computing since it can tolerant some degree of the device and array imperfections. The acceleration of multiple layer perceptrons, convolutional neural networks, generative adversarial networks, and long short-term memory neural networks are described. The latter one is hard computing because the solving of numerical problems requires high-precision devices. Several breakthroughs in memristive equation solvers with improved computation accuracies are highlighted. Besides, other nonvolatile devices with the capability of analog computing are also briefly introduced. Finally, we conclude the review with discussions on the challenges and opportunities for future research toward realizing memristive analog computing machines.

Maximizing Parallel Activation of Word-Lines in MRAM-Based Binary Neural Network Accelerators

Magnetic RAM (MRAM)-based crossbar array has a great potential as a platform for in-memory binary neural network (BNN) computing. However, the number of word-lines that can be activated simultaneously is limited because of the low $I_{H}/I_{L}$ ratio of MRAM, which makes BNNs more vulnerable to the device variation. To address this issue, we propose an algorithm/hardware co-design methodology. First, we choose a promising memristor crossbar array (MCA) structure based on the sensitivity analysis to process variations. Since the selected MCA structure becomes more tolerant to the device variation when the number of 1 in input activation values decreases, we apply an input distribution regularization scheme to reduce the number of 1 in input of BNNs during training. We further improve the robustness against device variation by adopting the retraining scheme based on knowledge distillation. Experimental results show that the proposed method makes BNNs more tolerant to MRAM variation and increases the number of parallel word-line activation significantly; thereby achieving improved throughput and energy efficiency.

Optimization of Memristive Crossbar Array for Physical Unclonable Function Applications

Memristive crossbar Physical Unclonable Function (PUF) structures are emerging as strong security primitives for resource-constrained devices demanding good retention time, negligible standby power, small size, and ultra-low power operating requirements. Memristive PUF exploits the inherent high process variations of a memristor as a source of entropy to generate device-specific signatures. These PUFs need to be strong enough to deal with active and passive attacks as well as machine learning attacks, hence requires more device-to-device variability. Memristive PUF requires dense crossbar architecture to generate unique, uniform, and reliable device signatures. Dense memristive crossbars (Xbar) face the challenges of low noise margin, proper load resistance selection, scalability, and a precise sense circuitry at the load resistance side to read the resistive state of a memristor accurately. In this work, we have simulated and optimized the load resistance of memristive scaled up crossbar arrays. We have used two of our fabricated devices for memristive crossbar PUF simulation. The proposed crossbar PUF architecture satisfies the basic PUF evaluation metrics and improves noise margin (NM). The load resistance is optimized through MATLAB simulation. The impact of optimized load resistance on Xbar architecture is observed to be noticeable and around 18% improvement in the noise margin was observed when the crossbar is scaled up from 16×2 to 128×2.

A Monochloro Copper Phthalocyanine Memristor with High-Temperature Resilience for Electronic Synapse Applications.

Memristors are considered to be one of the most promising device concepts for neuromorphic computing, in particular thanks to their highly tunable resistive states. To realize neuromorphic computing architectures, the assembly of large memristive crossbar arrays is necessary, but is often accompanied by severe heat dispassion. Organic materials can be tailored with on-demand electronic properties in the context of neuromorphic applications. However, such materials are more susceptible to heat, and detrimental effects such as thermally induced degradation directly lead to failure of device operation. Here, an organic memristive synapse formed of monochloro copper phthalocyanine, which remains operational and capable of memristive switching at temperatures as high as 300 °C in ambient air without any encapsulation, is demonstrated. The change in the electrical conductance is found to be a result of ion movement, closely resembling what takes place in biological neurons. Furthermore, the high viability of this approach is showcased by demonstrating flexible memristors with stable switching behaviors after repeated mechanical bending as well as organic synapses capable of emulating a trainable and reconfigurable memristor array for image information processing. The results set a precedent for thermally resilient organic synapses to impact organic neuromorphic devices in progressing their practicality.