Memristor Crossbar Array Research Articles

Optical control of multiple resistance levels in graphene for memristic applications

Neuromorphic computing has emphasized the need for memristors with non-volatile, multiple conductance levels. This paper demonstrates the potential of hexagonal boron nitride (hBN)/graphene heterostructures to act as memristors with multiple resistance states that can be optically tuned using visible light. The number of resistance levels in graphene can be controlled by modulating doping levels, achieved by varying the electric field strength or adjusting the duration of optical illumination. Our measurements show that this photodoping of graphene results from the optical excitation of charge carriers from the nitrogen-vacancy levels of hBN to its conduction band, with these carriers then being transferred to graphene by the gate-induced electric field. We develop a qualitative model to describe our observations. Additionally, utilizing our device architecture, we propose a memristive crossbar array for vector-matrix multiplications.

In-Materia Annealing and Combinatorial Optimization Based on Vertical Memristive Array.

Due to its area and energy efficiency, a memristive crossbar array (CBA) has been extensively studied for various combinatorial optimization applications, from network problems to circuit design. However, conventional approaches include heavily burdening software fine-tuning for the annealing process. Instead, this study introduces the "in-materia annealing" method, where the inter-layer interference of vertically stacked memristive CBA is utilized as an annealing method. When mapping combinatorial optimization problems into the configuration layer of the CBA, exponentially decaying annealing profiles are generated in nearby noise layers. Moreover, in-materia annealing profiles can be controlled by changing compliance current, read voltage, and read pulse width. Therefore, the annealing profiles can be arbitrarily controlled and generated individually for each cell, providing rich noise sources to solve the problem efficiently. Consequently, the experimental and simulation of Max-Cut and weighted Max-Cut problems achieve notable results with the minimum software burden.

Custom RISC-V architecture incorporating memristive in-memory computing

Due to the rise in data-intensive applications, the von Neumann bottleneck is increasingly restricting modern computer architectures, resulting to latency and energy consumption. Addressing this challenge necessitates a CMOS-compatible solution with high energy efficiency and significant parallelism. Utilizing resistive switching components within a 1T1R crossbar array and the application of Stanford RRAM model, this paper suggests an original method for in-memory computing. Moreover, this work shows a new way to advance the popular RISC-V architecture by including memristive crossbar array. It does this by adding a custom instruction set, special hardware blocks, and the Scouting Logic Scheme. These modifications serve both as a comprehensive testbed for the memory system and a proof of concept for the future integration of memristors in computing architectures. The proposed design undergoes extensive testing and power analysis to validate its functionality and performance under various conditions. The results demonstrate significant improvements in computational efficiency and energy savings, highlighting the potential of memristor-based in-memory computing systems to overcome current architectural limitations.

Memristive Crossbar Array-Based Probabilistic Graph Modeling.

Modern graph datasets with structural complexity and uncertainties due to incomplete information or data variability require advanced modeling techniques beyond conventional graph models. This study introduces a memristive crossbar array (CBA)-based probabilistic graph model (C-PGM) utilizing Cu0.3Te0.7/HfO2/Pt memristors, which exhibit probabilistic switching, self-rectifying, and memory characteristics. C-PGM addresses the complexities and uncertainties inherent in structural graph data across various domains, leveraging the probabilistic nature of memristors. C-PGM relies on the device-to-device variation across multiple memristive CBAs, overcoming the limitations of previous approaches that rely on sequential operations, which are slower and have a reliability concern due to repeated switching. This new approach enables the fast processing and massive implementation of probabilistic units at the expense of chip area. In this study, the hardware-based C-PGM feasibly expresses small-scale probabilistic graphs and shows minimal error in aggregate probability calculations. The probability calculation capabilities of C-PGM are applied to steady-state estimation and the PageRank algorithm, which is implemented on a simulated large-scale C-PGM. The C-PGM-based steady-state estimation and PageRank algorithm demonstrate comparable accuracy to conventional methods while significantly reducing computational costs.

Audio Signal-Stimulated Multilayered HfOx/TiOy Spiking Neuron Network for Neuromorphic Computing.

As the key hardware of a brain-like chip based on a spiking neuron network (SNN), memristor has attracted more attention due to its similarity with biological neurons and synapses to deal with the audio signal. However, designing stable artificial neurons and synapse devices with a controllable switching pathway to form a hardware network is a challenge. For the first time, we report that artificial neurons and synapses based on multilayered HfOx/TiOy memristor crossbar arrays can be used for the SNN training of audio signals, which display the tunable threshold switching and memory switching characteristics. It is found that tunable volatile and nonvolatile switching from the multilayered HfOx/TiOy memristor is induced by the size-controlled atomic oxygen vacancy pathway, which depends on the atomic sublayer in the multilayered structure. The successful emulation of the biological neuron's integrate-and-fire function can be achieved through the utilization of the tunable threshold switching characteristic. Based on the stable performance of the multilayered HfOx/TiOy neuron and synapse, we constructed a hardware SNN architecture for processing audio signals, which provides a base for the recognition of audio signals through the function of integration and firing. Our design of an atomic conductive pathway by using a multilayered TiOy/HfOx memristor supplies a new method for the construction of an artificial neuron and synapse in the same matrix, which can reduce the cost of integration in an AI chip. The implementation of synaptic functionalities by the hardware of SNNs paves the way for novel neuromorphic computing paradigms in the AI era.

A memristive-photoconductive transduction methodology for accurately nondestructive memory readout

Crossbar resistive memory architectures enable high-capacity storage and neuromorphic computing, accurate retrieval of the stored information is a prerequisite during read operation. However, conventional electrical readout normally suffer from complicated process, inaccurate and destructive reading due to crosstalk effect from sneak path current. Here we report a memristive-photoconductive transduction (MPT) methodology for precise and nondestructive readout in a memristive crossbar array. The individual devices present dynamic filament form/fuse for resistance modulation under electric stimulation, which leads to photogenerated carrier transport for tunable photoconductive response under subsequently light pulse stimuli. This coherent signal transduction can be used to directly detect the memorized on/off states stored in each cell, and a prototype 4 * 4 crossbar memories has been constructed and validated for the fidelity of crosstalk-free readout in recall process.

Reservoir computing with a random memristor crossbar array.

Physical implementations of reservoir computing (RC) based on the emerging memristors have become promising candidates of unconventional computing paradigms. Traditionally, sequential approaches by time-multiplexing volatile memristors have been prevalent because of their low hardware overhead. However, they suffer from the problem of speed degradation and fall short of capturing the spatial relationship between the time-domain inputs. Here, we explore a new avenue for RC using memristor crossbar arrays (MCAs) with device-to-device variations, which serve as physical random weight matrices of the reservoir layers, enabling faster computation thanks to the parallelism of matrix-vector multiplication as an intensive operation in RC. To achieve this new RC architecture, ultralow-current, self-selective memristors are fabricated and integrated without the need of transistors, showing greater potential of high scalability and three-dimensional integrability compared to the previous realizations. The information processing ability of our RC system is demonstrated in tasks of recognizing digit images and waveforms. This work indicates that the "nonidealities" of the emerging memristor devices and circuits are a useful source of inspiration for new computing paradigms.

Implementation of two-step gradual reset scheme for enhancing state uniformity of 2D hBN-based memristors for image processing

In-memory computing facilitates efficient parallel computing based on the programmable memristor crossbar array. Proficient hardware image processing can be implemented by utilizing the analog vector-matrix operation with multiple memory states of the nonvolatile memristor in the crossbar array. Among various materials, 2D materials are great candidates for a switching layer of nonvolatile memristors, demonstrating low-power operation and electrical tunability through their remarkable physical and electrical properties. However, the intrinsic device-to-device (D2D) variation of memristors within the crossbar array can degrade the accuracy and performance of in-memory computing. Here, we demonstrate hardware image processing using the fabricated 2D hexagonal boron nitride-based memristor to investigate the effects of D2D variation on the hardware convolution process. The image quality is evaluated by peak-signal-to-noise ratio, structural similarity index measure, and Pratt’s figure of merit and analyzed according to D2D variations. Then, we propose a novel two-step gradual reset programming scheme to enhance the conductance uniformity of multiple states of devices. This approach can enhance the D2D variation and demonstrate the improved quality of the image processing result. We believe that this result suggests the precise tuning method to realize high-performance in-memory computing.

Nondefective Vacancy Enhanced Resistive Switching Reliability in Emergent van der Waals Metal Phosphorus Trisulfide-Based Memristive In-Memory Computing Hardware.

Two-dimensional-material-based memristors are emerging as promising enablers of new computing systems beyond von Neumann computers. However, the most studied anion-vacancy-enabled transition metal dichalcogenide memristors show many undesirable performances, e.g., high leakage currents, limited memory windows, high programming currents, and limited endurance. Here, we demonstrate that the emergent van der Waals metal phosphorus trisulfides with unconventional nondefective vacancy provide a promising paradigm for high-performance memristors. The different vacancy types (i.e., defective and nondefective vacancies) induced memristive discrepancies are uncovered. The nondefective vacancies can provide an ultralow diffusion barrier and good memristive structure stability giving rise to many desirable memristive performances, including high off-state resistance of 1012 Ω, pA-level programming currents, large memory window up to 109, more than 7-bit conductance states, and good endurance. Furthermore, a high-yield (94%) memristor crossbar array is fabricated and implements multiple image processing successfully, manifesting the potential for in-memory computing hardware.

Random Projection‐Based Locality‐Sensitive Hashing in a Memristor Crossbar Array with Stochasticity for Sparse Self‐Attention‐Based Transformer

AbstractSelf‐attention mechanism is critically central to the state‐of‐the‐art transformer models. Because the standard full self‐attention has quadratic complexity with respect to the input's length L, resulting in prohibitively large memory for very long sequences, sparse self‐attention enabled by random projection (RP)‐based locality‐sensitive hashing (LSH) has recently been proposed to reduce the complexity to O(L log L). However, in current digital computing hardware with a von Neumann architecture, RP, which is essentially a matrix multiplication operation, incurs unavoidable time and energy‐consuming data shuttling between off‐chip memory and processing units. In addition, it is known that digital computers simply cannot generate provably random numbers. With the emerging analog memristive technology, it is shown that it is feasible to harness the intrinsic device‐to‐device variability in the memristor crossbar array for implementing the RP matrix and perform RP‐LSH computation in memory. On this basis, sequence prediction tasks are performed with a sparse self‐attention‐based Transformer in a hybrid software‐hardware approach, achieving a testing accuracy over 70% with much less computational complexity. By further harnessing the cycle‐to‐cycle variability for multi‐round hashing, 12% increase in the testing accuracy is demonstrated. This work extends the range of applications of memristor crossbar arrays to the state‐of‐the‐art large language models (LLMs).

True random number generation using the spin crossover in LaCoO3

While digital computers rely on software-generated pseudo-random number generators, hardware-based true random number generators (TRNGs), which employ the natural physics of the underlying hardware, provide true stochasticity, and power and area efficiency. Research into TRNGs has extensively relied on the unpredictability in phase transitions, but such phase transitions are difficult to control given their often abrupt and narrow parameter ranges (e.g., occurring in a small temperature window). Here we demonstrate a TRNG based on self-oscillations in LaCoO3 that is electrically biased within its spin crossover regime. The LaCoO3 TRNG passes all standard tests of true stochasticity and uses only half the number of components compared to prior TRNGs. Assisted by phase field modeling, we show how spin crossovers are fundamentally better in producing true stochasticity compared to traditional phase transitions. As a validation, by probabilistically solving the NP-hard max-cut problem in a memristor crossbar array using our TRNG as a source of the required stochasticity, we demonstrate solution quality exceeding that using software-generated randomness.

Threshold learning algorithm for memristive neural network with binary switching behavior

On-chip learning is an effective method for adjusting artificial neural networks in neuromorphic computing systems by considering hardware intrinsic properties. However, it faces challenges due to hardware nonidealities, such as the nonlinearity of potentiation and depression and limitations on fine weight adjustment. In this study, we propose a threshold learning algorithm for a variation-tolerant ternary neural network in a memristor crossbar array. This algorithm utilizes two tightly separated resistance states in memristive devices to represent weight values. The high-resistance state (HRS) and low-resistance state (LRS) defined as read current of < 0.1 μA and > 1 μA, respectively, were successfully programmed in a 32 × 32 crossbar array, and exhibited half-normal distributions due to the programming method. To validate our approach experimentally, a 64 × 10 single-layer fully connected network were trained in the fabricated crossbar for an 8 × 8 MNIST dataset using the threshold learning algorithm, where the weight value is updated when a gradient determined by backpropagation exceeds a threshold value. Thanks to the large margin between the two states of the memristor, we observed only a 0.42 % drop in classification accuracy compared to the baseline network results. The threshold learning algorithm is expected to alleviate the programming burden and be utilized in variation-tolerant neuromorphic architectures.

Forming-less flexible memristor crossbar array for neuromorphic computing applications produced using low-temperature atomic layer deposition

The rapid development of wearable artificial intelligence devices based on memristor crossbar arrays has increased the demand for flexible electronics. However, fabricating crossbar arrays on flexible substrates faces inherent challenges, notably due to the complex fabrication process at low temperatures. Moreover, ensuring the stability and reliability of memristor device remains a crucial issue. To address these issues, this study introduced N-doped TaOx (N:TaOx) as a flexible memristor crossbar array fabricated via atomic layer deposition directly on a flexible substrate at an exceptionally low temperature (150 °C). The flexible PET/ITO/N:TaOx/TiN memristor device exhibited forming-less bipolar resistive switching properties with analog memory characteristics. This was accomplished by increasing the nitrogen doping concentration and effectively reducing oxygen-related defects in TaOx. The amorphous-phase flexible N:TaOx memristor demonstrated remarkable stability, enduring 500 switching cycles and retaining its state for 24 h during bending tests involving 104 bending cycles at 2.5 mm bending radius. Furthermore, a 6 × 6 flexible memristor crossbar array was fabricated successfully, with all 36 devices exhibiting well-defined memristor behavior and minimal variation attributed to the film's uniformity achieved through ALD process. Additionally, by programming the tunable conductance of each device in the array, characters of desired shapes can be formed and read. Regarding their synaptic behavior via long-term potentiation and depression, the proposed flexible memristor device showed an outstanding accuracy of 96.44 % in image recognition tasks under extreme bending conditions, employing the MNIST and Fashion-MNIST datasets. The N:TaOx memristor deposited at low temperatures thus exhibits significant potential for use in wearable neuromorphic hardware applications due to its high density, high performance, reliability, and precise image recognition.

Memristive crossbar-based circuit design of back-propagation neural network with synchronous memristance adjustment

The performance improvement of CMOS computer fails to meet the enormous data processing requirement of artificial intelligence progressively. The memristive neural network is one of the most promising circuit hardwares to make a breakthrough. This paper proposes a novel memristive synaptic circuit that is composed of four MOS transistors and one memristor (4T1M). The 4T1M synaptic circuit provides flexible control strategies to change memristance or respond to the input signal. Applying the 4T1M synaptic circuit as the cell of memristive crossbar array, based on the structure and algorithm of the back-propagation (BP) neural network, this paper proposes circuit design of the memristive crossbar-based BP neural network. By reusing the 4T1M memristive crossbar array, the computations in the forward-propagation process and back-propagation process of BP neural network are accomplished on the memristive crossbar-based circuit to accelerate the computing speed. The 4T1M memristive crossbar array can change all the cells’ memristance at a time, accordingly, the memristive crossbar-based BP neural network can realize synchronous memristance adjustment. The proposed memristive crossbar-based BP neural network is then evaluated through experiments involving XOR logic operation, iris classification, and MNIST handwritten digit recognition. The experimental results present fewer iterations or higher classification accuracies. Further, the comprehensive comparisons with the existing memristive BP neural networks highlight the advantages of the proposed memristive crossbar-based BP neural network, which achieves the fastest memristance adjustment speed using relatively few components.

Overshoot‐Suppressed Memristor Crossbar Array with High Yield by AlOx Oxidation for Neuromorphic System

AbstractThere is a need to design a hardware synapse array appropriate for enhancing the efficiency of neuromorphic computing systems while minimizing energy consumption. This study introduces a memristor device with an AlOx overshoot suppression layer (A‐OSL) to achieve a self‐compliance effect. By optimizing each cell within the 16 × 16 crossbar array, synaptic devices are successfully fabricated with reliable characteristics and 3‐bit multilevel capabilities. In addition, the oxygen composition of TiOx and the annealing conditions are optimized to reduce the forming voltage and minimize the variation in the switching voltage. As a result, stable forming‐free characteristics are obtained through A‐OSL insertion, a reduction in forming voltage, and TiOx oxygen composition optimization. Also, target weights are accurately transferred to the A‐OSL memristor crossbar array and conducted the inference process by applying spike signals to the array following the designated time step. The spiking neural network (SNN) is demonstrated by measuring vector‐matrix multiplication (VMM) of the 16 × 16 crossbar array. The VMM results exhibit a classification accuracy of 90.80% for the MNIST dataset, which is close to the accuracy achieved by software‐based approaches, amounting to 91.85%.

Reconfigurable Resistive Switching in VO2/La0.7Sr0.3MnO3/Al2O3 (0001) Memristive Devices for Neuromorphic Computing.

The coexistence of nonvolatile and volatile switching modes in a single memristive device provides flexibility to emulate both neuronal and synaptic functions in the brain. Furthermore, such a device structure may eliminate the need for additional circuit elements such as transistor-based selectors, enabling low-power consumption and high-density device integration in fully memristive spiking neural networks. In this work, we report dual resistive switching (RS) modes in VO2/La0.7Sr0.3MnO3 (LSMO) bilayer memristive devices. Specifically, the nonvolatile RS is driven by the movement of oxygen vacancies (Vo) at the VO2/LSMO interface and requires a higher biasing voltage, whereas the volatile RS is controlled by the metal-insulator transition (MIT) of VO2 under a lower biasing voltage. The simple device structure is electrically driven between the two RS modes and thus can operate as a one selector-one resistor (1S1R) cell, which is a desirable feature in memristive crossbar arrays to avoid the sneak-path current issue. The RS modes are found to be stable and repeatable and can be reconfigured by exploiting the interfacial and phase transition properties, and thus, they hold great promise for applications in memristive neural networks and neuromorphic computing.

Harnessing nonlinear conductive characteristic of TiO2/HfO2 memristor crossbar for implementing parallel vector–matrix multiplication

Memristor crossbar arrays are expected to achieve highly energy-efficient neuromorphic computing via implementing parallel vector–matrix multiplication (VMM) in situ. The similarities between memristors and neural synapses offer opportunities for realizing hardware-based brain-inspired computing, such as spike neural networks. However, the nonlinear I–V characteristics of the memristors limit the implementation of parallel VMM on passive memristor crossbar arrays. In our work, we propose to utilize differential conductance as a synaptic weight to implement linear VMM operations on a passive memristor array in parallel. We fabricated a TiO2/HfO2 memristor crossbar array, in which differential-conductance-based synaptic weight exhibits plasticity, nonvolatility, multi-states, and tunable ON/OFF ratio. The noise-dependent accuracy performance of VMM operations based on the proposed approach was evaluated, offering an optimization guideline. Furthermore, we demonstrated a spike neural network circuit capable of processing small spiking signals through the differential-conductance-based synapses. The experimental results showcase effective space-coded and time-coded spike pattern recognition. Importantly, our work opens up new possibilities for the development of passive memristor arrays, leading to increased energy and area efficiency in brain-inspired chips.

Fabrication and investigation of a memristive crossbar array artificial synapses based on electrochemical titanium oxide for neuroelectronics

The formation of free resistive switching between the low-resistance state (LRS) 100.2 ± 9.1 Ω and the high-resistance state (HRS) 890.3 ± 81.7 Ω was observed during 1000 switching cycles, the ratio of the resistance value of HRS to LRS was 8.9 ± 1.6. The dependence of the increase in the response current during paired pulse facilitation on the number of pulses and the magnitude of the voltage pulses is shown. The results obtained can be used in the development of technological foundations for the formation of high-performance multilevel artificial synapses for elements of neuroelectronics and hardware neural networks.

Stochastic neuro-fuzzy system implemented in memristor crossbar arrays.

Neuro-symbolic artificial intelligence has garnered considerable attention amid increasing industry demands for high-performance neural networks that are interpretable and adaptable to previously unknown problem domains with minimal reconfiguration. However, implementing neuro-symbolic hardware is challenging due to the complexity in symbolic knowledge representation and calculation. We experimentally demonstrated a memristor-based neuro-fuzzy hardware based on TiN/TaOx/HfOx/TiN chips that is superior to its silicon-based counterpart in terms of throughput and energy efficiency by using array topological structure for knowledge representation and physical laws for computing. Intrinsic memristor variability is fully exploited to increase robustness in knowledge representation. A hybrid in situ training strategy is proposed for error minimizing in training. The hardware adapts easier to a previously unknown environment, achieving ~6.6 times faster convergence and ~6 times lower error than deep learning. The hardware energy efficiency is over two orders of magnitude greater than field-programmable gate arrays. This research greatly extends the capability of memristor-based neuromorphic computing systems in artificial intelligence.

Multiphase Reset Induced Reliable Dual-Mode Resistance Switching of the Ta/HfO2/RuO2 Memristor.

Higher functionality should be achieved within the device-level switching characteristics to secure the operational possibility of mixed-signal data processing within a memristive crossbar array. This work investigated electroforming-free Ta/HfO2/RuO2 resistive switching devices for digital- and analog-type applications through various structural and electrical analyses. The multiphase reset behavior, induced by the conducting filament modulation and oxygen vacancy generation (annihilation) in the HfO2 layer by interacting with the Ta (RuO2) electrode, was utilized for the switching mode change. Therefore, a single device can manifest stable binary switching between low and high resistance states for the digital mode and the precise 8-bit conductance modulation (256 resistance values) via an optimized pulse application for the analog mode. An in-depth analysis of the operation in different modes and comparing memristors with different electrode structures validate the proposed mechanism. The Ta/HfO2/RuO2 resistive switching device is feasible for a mixed-signal processable memristive array.