Memristor Conductance Research Articles

Nanoscale Ni/Mo/MoO3/Ni memristor for synaptic applications

AbstractFor the first time, a physics‐based modelling of a nanoscale Ni/Mo/MoO3/Ni memristor is presented in this letter by inserting a ‘Mo:Capping layer’ between the top electrode (Ni) and the insulating layer (MoO3). The proposed memristor has stable hysteresis I–V characteristics as well as a significant reduction in ‘Forming voltage’ (VFORM) to 0.75 V. The simulated resistive switching responses using the COMSOL Multiphysics package demonstrate consistently low values of coefficient of variability (CV) with 14.31% and 14.85% for the SET and RESET modules, respectively, during cycle‐to‐cycle variations along with a low compliance current (ICC) of 193 µA. In addition to observing synaptic plasticity behaviour, it also examines how ramp‐rates impact ‘Potentiation’ and ‘Depression’ as memristor conductance (G) is closely related to synaptic weights.

Spatiotemporal Data Processing with Memristor Crossbar-Array-Based Graph Reservoir.

Memristor-based physical reservoir computing (RC) is a robust framework for processing complex spatiotemporal data parallelly. However, conventional memristor-based reservoirs cannot capture the spatial relationship between the time-varying inputs due to the specific mapping scheme assigning one input signal to one memristor conductance. Here, a physical "graph reservoir" is introduced using a metal cell at the diagonal-crossbar array (mCBA) with dynamic self-rectifying memristors. Input and inverted input signals are applied to the word and bit lines of the mCBA, respectively, storing the correlation information between input signals in the memristors. In this way, the mCBA graph reservoirs can map the spatiotemporal correlation of the input data in a high-dimensional feature space. The high-dimensional mapping characteristics of the graph reservoir achieve notable results, including a normalized root-mean-square error of 0.09 in Mackey-Glass time series prediction, a 97.21% accuracy in MNIST recognition, and an 80.0% diagnostic accuracy in human connectome classification.

A Memristor Crossbar-Based Lyapunov Equation Solver

An analog memristor crossbar based Lyapunov equation solver is proposed in this paper. It is an extension of memristor crossbar linear equation solver, but taking into account of the regularity with Lyapunov equation in the organization of crossbar. Nonideal effects due to co-design with CMOS analog circuits are studied in detail. Verification using a Verilog-AMS tool is performed to justify that with proper scaling on the memristor conductance values and other circuit signals, the solution quality of Lyapunov matrix equation can be improved.

A Hybrid Weight Quantization Strategy for Memristive Neural Networks

Due to the ability to store data and process information, the memristor-based neuromorphic system has attracted extensive attention. Its efficient parallel computing approach allows it to implement neural networks in hardware. However, due to the limitation of the range of memristor conductance, it is difficult to represent high-precision weights in memristive neural network. During the off-chip learning, it is crucial to find an efficient weight quantization scheme and map it to the memristor array. Therefore, a hybrid weight quantization strategy that combines uniform and non-uniform quantization is proposed to overcome these problems. Specifically, the curve fitting of pulse modulation for tantalum oxide-based memristor is carried out, and the mapping rules of weights are proposed to simplify the process of reading verification. Furthermore, the hybrid quantization strategy is proposed and applied to a multilayer perceptron and a convolutional neural network, respectively. The effectiveness and robustness of the hybrid quantization scheme are verified in the MNIST dataset. Experiments show that the proposed hybrid quantization scheme can achieve 99.26% accuracy at 4 bits and tolerate 20% noise interference. The simulation results in this paper also provide an effective solution for the hardware implementation of memristive neural networks.

Memristor Crossbar Circuits Implementing Equilibrium Propagation for On-Device Learning.

Equilibrium propagation (EP) has been proposed recently as a new neural network training algorithm based on a local learning concept, where only local information is used to calculate the weight update of the neural network. Despite the advantages of local learning, numerical iteration for solving the EP dynamic equations makes the EP algorithm less practical for realizing edge intelligence hardware. Some analog circuits have been suggested to solve the EP dynamic equations physically, not numerically, using the original EP algorithm. However, there are still a few problems in terms of circuit implementation: for example, the need for storing the free-phase solution and the lack of essential peripheral circuits for calculating and updating synaptic weights. Therefore, in this paper, a new analog circuit technique is proposed to realize the EP algorithm in practical and implementable hardware. This work has two major contributions in achieving this objective. First, the free-phase and nudge-phase solutions are calculated by the proposed analog circuits simultaneously, not at different times. With this process, analog voltage memories or digital memories with converting circuits between digital and analog domains for storing the free-phase solution temporarily can be eliminated in the proposed EP circuit. Second, a simple EP learning rule relying on a fixed amount of conductance change per programming pulse is newly proposed and implemented in peripheral circuits. The modified EP learning rule can make the weight update circuit practical and implementable without requiring the use of a complicated program verification scheme. The proposed memristor conductance update circuit is simulated and verified for training synaptic weights on memristor crossbars. The simulation results showed that the proposed EP circuit could be used for realizing on-device learning in edge intelligence hardware.

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AbstractThis work (DOI: 10.1002/inf2.12416) demonstrates an in‐memory search system based on the self‐selective memristors. First, by utilizing the intrinsic randomness of the memristor conductance, a hardware locality sensitive hashing (LSH) encoder is constructed to map the feature vectors into compact binary code. Subsequently, an ultra‐low‐power 2R ternary content addressable memory is demonstrated, serving as the high parallel distance computing engine. Based on the in‐memory search system, the typical data mining algorithms are demonstrated as the benchmark and the system shows 168 times energy saving comparing with the CPU with the software‐comparable accuracy. image

Thousands of conductance levels in memristors integrated on CMOS.

Neural networks based on memristive devices1-3 have the ability to improve throughput and energy efficiency for machine learning4,5 and artificial intelligence6, especially in edge applications7-21. Because training a neural network model from scratch is costly in terms of hardware resources, time and energy, it is impractical to do it individually on billions of memristive neural networks distributed at the edge. A practical approach would be to download the synaptic weights obtained from the cloud training and program them directly into memristors for the commercialization of edge applications. Some post-tuning in memristor conductance could be done afterwards or during applications to adapt to specific situations. Therefore, in neural network applications, memristors require high-precision programmability to guarantee uniform and accurate performance across a large number of memristive networks22-28. This requires many distinguishable conductance levels on each memristive device, not only laboratory-made devices but also devices fabricated in factories. Analog memristors with many conductance states also benefit other applications, such as neural network training, scientific computing and even 'mortal computing'25,29,30. Here we report 2,048 conductance levels achieved with memristors in fully integrated chips with 256 × 256 memristor arrays monolithically integrated on complementary metal-oxide-semiconductor (CMOS) circuits in a commercial foundry. We have identified the underlying physics that previously limited the number of conductance levels that could be achieved in memristors and developed electrical operation protocols to avoid such limitations. These results provide insights into the fundamental understanding of the microscopic picture of memristive switching as well as approaches to enable high-precision memristors for various applications. Fig. 1 HIGH-PRECISION MEMRISTOR FOR NEUROMORPHIC COMPUTING.: a, Proposed scheme of the large-scale application of memristive neural networks for edge computing. Neural network training is performed in the cloud. The obtained weights are downloaded and accurately programmed into a massive number of memristor arrays distributed at the edge, which imposes high-precision requirements on memristive devices. b, An eight-inch wafer with memristors fabricated by a commercial semiconductor manufacturer. c, High-resolution transmission electron microscopy image of the cross-section view of a memristor. Pt and Ta serve as the bottom electrode (BE) and top electrode (TE), respectively. Scale bars, 1 μm and 100 nm (inset). d, Magnification of the memristor material stack. Scale bar, 5 nm. e, As-programmed (blue) and after-denoising (red) currents of a memristor are read by a constant voltage (0.2 V). The denoising process eliminated the large-amplitude RTN observed in the as-programmed state (see Methods). f, Magnification of three nearest-neighbour states after denoising. The current of each state was read by a constant voltage (0.2 V). No large-amplitude RTN was observed, and all of the states can be clearly distinguished. g, An individual memristor on the chip was tuned into 2,048 resistance levels by high-resolution off-chip driving circuitry, and each resistance level was read by a d.c. voltage sweeping from 0 to 0.2 V. The target resistance was set from 50 µS to 4,144 µS with a 2-µS interval between neighbouring levels. All readings at 0.2 V are less than 1 µS from the target conductance. Bottom inset, magnification of the resistance levels. Top inset, experimental results of an entire 256 × 256 array programmed by its 6-bit on-chip circuitry into 64 32 × 32 blocks, and each block is programmed into one of the 64 conductance levels. Each of the 256 × 256 memristors has been previously switched over one million cycles, demonstrating the high endurance and robustness of the devices.

Bridge Memristor Super-Resolution Crossbars

A higher number of unique conductance levels in the memristor crossbar node ensures higher accuracy for analogue dot-product computations. Series and parallel combinations of memristors are used as a common approach to creating multilevel conductance superresolution nodes. The super-resolution nodes are tolerant to a wide range of memristor non-idealities. In this paper, we present a bridge-type design of a super-resolution node. Compared to previous work, the proposed design could achieve a resolution improvement of 5 to 9 times higher when individual memristor conductance levels change from 5 to 12 states. Although the bridge nodes preserve tolerance to memristor variability similar to that of a parallel superresolution node, they do so at lower area and power requirements. Bridge-based crossbar nodes were successfully tested in artificial and convolutional neural networks, showing near-idealistic inference accuracy.

Energy-efficient neural network design using memristive MAC unit

Artificial intelligence applications implemented with neural networks require extensive arithmetic capabilities through multiply-accumulate (MAC) units. Traditional designs based on voltage-mode circuits feature complex logic chains for such purposes as carry processing. Additionally, as a separate memory block is used (e.g., in a von Neumann architecture), data movements incur on-chip communication bottlenecks. Furthermore, conventional multipliers have both operands encoded in the same physical quantity, which is either low cost to update or low cost to hold, but not both. This may be significant for low-energy edge operations. In this paper, we propose and present a mixed-signal multiply-accumulate unit design with in-memory computing to improve both latency and energy. This design is based on a single-bit multiplication cell consisting of a number of memristors and a single transistor switch (1TxM), arranged in a crossbar structure implementing the long-multiplication algorithm. The key innovation is that one of the operands is encoded in easy to update voltage and the other is encoded in non-volatile memristor conductance. This targets operations such as machine learning which feature asymmetric requirements for operand updates. Ohm’s Law and KCL take care of the multiplication in analog. When implemented as part of a NN, the MAC unit incorporates a current to digital stage to produce multi-bit voltage-mode output, in the same format as the input. The computation latency consists of memory writing and result encoding operations, with the Ohm’s Law and KCL operations contributing negligible delay. When compared with other memristor-based multipliers, the proposed work shows an order of magnitude of latency improvement in 4-bit implementations partly because of the Ohm’s Law and KCL time savings and partly because of the short writing operations for the frequently updated operand represented by voltages. In addition, the energy consumption per multiplication cycle of the proposed work is shown to improve by 74%–99% in corner cases. To investigate the usefulness of this MAC design in machine learning applications, its input/output relationships is characterized using multi-layer perceptrons to classify the well-known hand-writing digit dataset MNIST. This case study implements a quantization-aware training and includes the non-ideal effect of our MAC unit to allow the NN to learn and preserve its high accuracy. The simulation results show the NN using the proposed MAC unit yields an accuracy of 93%, which is only 1% lower than its baseline.

XMAP: Programming Memristor Crossbars for Analog Matrix–Vector Multiplication: Toward High Precision Using Representable Matrices

Linear transformations are the dominating computation within many important applications. The natural multiply and accumulate feature of memristor crossbar arrays promise unprecedented processing capabilities to resistive dot-product engines (DPEs), which can accelerate approximate matrix-vector multiplication (MVM). Unfortunately, the precision of the analog computation may be degraded by parasitics, non-linear device characteristics, and variations. In this paper, we propose a framework called XMAP for mapping an arbitrary matrix into appropriate memristor conductance values (or state variables for non-linear devices). The specified conductance values are next programmed to the memristor hardware using accurate closed-loop tuning. XMAP is based on formulating the mapping problem as a mathematical optimization problem, which can be elegantly minimized using the concept of representable matrices, i.e., the matrices that can be represented on a crossbar. Compared with the state-of-the-art conversion algorithm, the computational accuracy is improved with up to 3.29X at the expense of overhead in run-time. The precision improvements translate into noteworthy application level benefits within signal compression and neural network inference.

Modeling the Dynamics of Spiking Networks with Memristor-Based STDP to Solve Classification Tasks

The problem with training spiking neural networks (SNNs) is relevant due to the ultra-low power consumption these networks could exhibit when implemented in neuromorphic hardware. The ongoing progress in the fabrication of memristors, a prospective basis for analogue synapses, gives relevance to studying the possibility of SNN learning on the base of synaptic plasticity models, obtained by fitting the experimental measurements of the memristor conductance change. The dynamics of memristor conductances is (necessarily) nonlinear, because conductance changes depend on the spike timings, which neurons emit in an all-or-none fashion. The ability to solve classification tasks was previously shown for spiking network models based on the bio-inspired local learning mechanism of spike-timing-dependent plasticity (STDP), as well as with the plasticity that models the conductance change of nanocomposite (NC) memristors. Input data were presented to the network encoded into the intensities of Poisson input spike sequences. This work considers another approach for encoding input data into input spike sequences presented to the network: temporal encoding, in which an input vector is transformed into relative timing of individual input spikes. Since temporal encoding uses fewer input spikes, the processing of each input vector by the network can be faster and more energy-efficient. The aim of the current work is to show the applicability of temporal encoding to training spiking networks with three synaptic plasticity models: STDP, NC memristor approximation, and PPX memristor approximation. We assess the accuracy of the proposed approach on several benchmark classification tasks: Fisher’s Iris, Wisconsin breast cancer, and the pole balancing task (CartPole). The accuracies achieved by SNN with memristor plasticity and conventional STDP are comparable and are on par with classic machine learning approaches.

A Highly Robust Binary Neural Network Inference Accelerator Based on Binary Memristors

Since memristor was found, it has shown great application potential in neuromorphic computing. Currently, most neural networks based on memristors deploy the special analog characteristics of memristor. However, owing to the limitation of manufacturing process, non-ideal characteristics such as non-linearity, asymmetry, and inconsistent device periodicity appear frequently and definitely, therefore, it is a challenge to employ memristor in a massive way. On the contrary, a binary neural network (BNN) requires its weights to be either +1 or −1, which can be mapped by digital memristors with high technical maturity. Upon this, a highly robust BNN inference accelerator with binary sigmoid activation function is proposed. In the accelerator, the inputs of each network layer are either +1 or 0, which can facilitate feature encoding and reduce the peripheral circuit complexity of memristor hardware. The proposed two-column reference memristor structure together with current controlled voltage source (CCVS) circuit not only solves the problem of mapping positive and negative weights on memristor array, but also eliminates the sneak current effect under the minimum conductance status. Being compared to the traditional differential pair structure of BNN, the proposed two-column reference scheme can reduce both the number of memristors and the latency to refresh the memristor array by nearly 50%. The influence of non-ideal factors of memristor array such as memristor array yield, memristor conductance fluctuation, and reading noise on the accuracy of BNN is investigated in detail based on a newly memristor circuit model with non-ideal characteristics. The experimental results demonstrate that when the array yield α ≥ 5%, or the reading noise σ ≤ 0.25, a recognition accuracy greater than 97% on the MNIST data set is achieved.

A Low-bit And Data-conversion-free Memristive Spiking Computing Network

Memristor crossbar holds promising potential in massively parallel data processing, as computing tasks beyond vector-matrix multiplication typically requires additional complex data conversion modules. In this work, we report a memristive spiking computing network (MSCN) without data conversion. Two memristor crossbars are used to perform vector-matrix multiplication, while spiking neurons are used to integrate the signals from each column of the memristor crossbars. Input and output signals are binary spikes (spiking or non-spiking); thus data conversions between the analog and digital domains are avoided. The MSCN is suitable for accelerating artificial neural network (ANN). A multi-layer perception (MLP) consisting of four layers is simulated based on the analog MSCN, and recognition accuracy of 98.55% under the MNIST test set is achieved. However, in the practical memristor, it is challenging to adjust conductance analogously and even challenging to implement multi-bit conductance states. Therefore, the memristor conductance states are further reduced to 3 bits and 1 bit. Encouragingly, recognition accuracies just slightly decrease to 98.36% and 97.96% for 3-bit and 1-bit conductance states, respectively, which is cost-effective considering the hardware reliability improvement.

Multichannel parallel processing of neural signals in memristor arrays.

Fully implantable neural interfaces with massive recording channels bring the gospel to patients with motor or speech function loss. As the number of recording channels rapidly increases, conventional complementary metal-oxide semiconductor (CMOS) chips for neural signal processing face severe challenges on parallelism scalability, computational cost, and power consumption. In this work, we propose a previously unexplored approach for parallel processing of multichannel neural signals in memristor arrays, taking advantage of their rich dynamic characteristics. The critical information of neural signal waveform is extracted and encoded in the memristor conductance modulation. A signal segmentation scheme is developed to adapt to device variations. To verify the fidelity of the processed results, seizure prediction is further demonstrated, with high accuracy above 95% and also more than 1000× improvement in power efficiency compared with CMOS counterparts. This work suggests that memristor arrays could be a promising multichannel signal processing module for future implantable neural interfaces.

Optimal Tuning of Memristor Conductance Variation in Spiking Neural Networks for Online Unsupervised Learning

In unsupervised learning (UL)-oriented spiking neural network (SNN) designs, the initial conductance variation of the synapses is usually necessary, with which temporally differentiated responses of the output neurons can be achieved given the same input patterns, in order to implement the important lateral inhibition function. We take a lithium silicate memristor as an example and demonstrate through a motion-style recognition task that, without regulating the initial conductance variation of memristor synapses, several types of errors will occur: too large conductance variance leads to the deactivation of some output neurons and the incomplete learning of the motion routes, while too small variance causes duplicated learnings of the same pattern. By tuning the memristor conductance variance through the forming voltages, it is found that the UL capacity can be optimized, indicating a promising approach to enhance the UL performance of a memristor-based SNN.

Low‐Conductance and Multilevel CMOS‐Integrated Nanoscale Oxide Memristors

AbstractUsing memristors, such as oxide and phase change resistive switches, as tunable resistors to construct analog computing hardware accelerators is gaining keen attention. Such accelerators have demonstrated the potential to significantly outperform digital computers in highly relevant applications such as machine learning and image processing. However, improvements in device‐level performance of memristors, including reducing power consumption and high current–induced metal migration in interconnects, need continued developments. Nanoscaling and complementary metal‐oxide semiconductor (CMOS) integration are also of significant importance in commercialization of such accelerators. Here tantalum oxide memristors scaled down to 25 nm sizes and integrated on CMOS transistor circuits are presented. The memristor conductance is programmable with a 6 order‐of‐magnitude operating range, especially with 3‐bits below 10 µS for low current operation. The stability of such levels and the size scaling of the operating parameters are further studied. These results will aid device engineering of memristors and bolster development of neuromorphic hardware accelerators.

Synaptic Learning and Forgetting Behavior in Ag/AlN/Al Memristor With ${\text{O}_{2}}$ Annealing Effect

The learning and forgetting behavior of AlN thin film with O 2 annealing effect memristor had been investigated in this study. Such synaptic behavior could be observed after AlN thin film executed O 2 annealing process. The oxygen-induced AlN thin film exhibited memristive effect in resistance with positive and negative current-voltage (I-V) measurement loops which had never been observed in AlN thin film without annealing effect. The O 2 annealing process could decrease the number of oxygen vacancies (V+o ) in interface between top electrode and active layer. A typical I-V measurement is shown in this study. If continuous positive voltage pulses applied, the device conductance would increase gradually which is called learning behavior of device. If negative voltage pulse applied, the device conductance would decrease gradually which is called forgetting behavior of device. The memristor conductance was thought to be closely associated with synaptic weights, the strength of synaptic connections. The learning and forgetting behavior of memristor is corresponding to LTP and LTD process in synaptic system. The ion diffusion played an important role in memristive properties which could form one or more local conductive filaments (CFs) in active layer. If the paths were gradually formed or broke, this would cause the memristor conductance changed gradually with measured voltage. The retention time and memristor conductance should depend on stimuli pulse shape, number and interval time.

Design and investigation of a chaotic neural network architecture for cryptographic applications

Artificial neural networks are an integral part of emerging technologies, and ongoing research has shown that they can be applied to a variety of applications. This paper proposes a new cryptographic algorithm using chaotic neural networks, whose function is enhanced by construction with polynomials that exhibit chaos, namely, nonlinear Hermite and Chebyshev polynomials. These polynomials incorporate a memristor conductance, which is used as an activation function in the chaotic neural networks. Further, a function of the weights obtained from the chaotic neural networks, is used to generate the initial values that are used in the cryptographic process. The encryption algorithm employed here is inspired by the Lai–Massey block cipher with cubic and two-dimensional logistic maps, and the evaluation of these chaotic equations is performed using correlation values. The correlation values between the cipher and plain text are also examined to determine the undecipherability of the message to be sent on a public channel.

Graphene Oxide Quantum Dots Based Memristors with Progressive Conduction Tuning for Artificial Synaptic Learning

AbstractMemristors as electronic artificial synapses have attracted increasing attention in neuromorphic computing. Emulation of both “learning” and “forgetting” processes requires a bidirectional progressive adjustment of memristor conductance, which is a challenge for cutting‐edge artificial intelligence. In this work, a memristor device with a structure of Ag/Zr0.5Hf0.5O2:graphene oxide quantum dots/Ag is presented with the feature of bidirectional progressive conductance tuning. The conductance of proposed memristor is adjusted through voltage pulse number, amplitude, and width. A series of voltage pulses with an amplitude of 0.6 V and a width of 30 ns is enough to modulate conductance. The impacts of pulses with different parameters on conductance modulation are investigated, and the potential relationship between pulse amplitude and energy is revealed. Furthermore, it is proved that the pulse with low energy can realize the almost linear conductance regulation, which is beneficial to improve the accuracy of pattern recognition. The bidirectional progressive conduction modulation mimics various plastic synapses, such as spike‐timing‐dependent plasticity and paired‐pulse facilitation. This progressive conduction tuning mechanism might be attributed to the coexistence of tunneling effect and extrinsic electrochemical metallization effect. This work provides one way for memristor to attain attractive features such as bidirectional tuning, low‐power consumption, and fast speed switching that is in urgent demand for further evolution of neuromorphic chips.

Temperature and field-dependent transport measurements in continuously tunable tantalum oxide memristors expose the dominant state variable

Applications of memristor devices are quickly moving beyond computer memory to areas of analog and neuromorphic computation. These applications require the design of devices with different characteristics from binary memory, such as a large tunable range of conductance. A complete understanding of the conduction mechanisms and their corresponding state variable(s) is crucial for optimizing performance and designs in these applications. Here we present measurements of low bias I–V characteristics of 6 states in a Ta/ tantalum-oxide (TaOx)/Pt memristor spanning over 2 orders of magnitude in conductance and temperatures from 100 K to 500 K. Our measurements show that the 300 K device conduction is dominated by a temperature-insensitive current that varies with non-volatile memristor state, with an additional leakage contribution from a thermally-activated current channel that is nearly independent of the memristor state. We interpret these results with a parallel conduction model of Mott hopping and Schottky emission channels, fitting the voltage and temperature dependent experimental data for all memristor states with only two free parameters. The memristor conductance is linearly correlated with N, the density of electrons near EF participating in the Mott hopping conduction, revealing N to be the dominant state variable for low bias conduction in this system. Finally, we show that the Mott hopping sites can be ascribed to oxygen vacancies, where the local oxygen vacancy density responsible for critical hopping pathways controls the memristor conductance.