Memristance Variation Research Articles

Electromagnetic Interference Effects of Continuous Waves on Memristors: A Simulation Study.

As two-terminal passive fundamental circuit elements with memory characteristics, memristors are promising devices for applications such as neuromorphic systems, in-memory computing, and tunable RF/microwave circuits. The increasingly complex electromagnetic interference (EMI) environment threatens the reliability of memristor systems. However, various EMI signals’ effects on memristors are still unclear. This paper selects continuous waves (CWs) as EMI signals. It provides a deeper insight into the interference effect of CWs on the memristor driven by a sinusoidal excitation voltage, as well as a method for investigating the EMI effect of memristors. The optimal memristor model is obtained by the exhaustive traversing of the possible model parameters, and the interference effect of CWs on memristors is quantified based on this model and the proposed evaluation metrics. Simulation results indicate that CW interference may affect the switching time, dynamic range, nonlinearity, symmetry, time to the boundary, and variation of memristance. The specific interference effect depends on the operating mode of the memristor, the amplitude, and the frequency of the CW. This research provides a foundation for evaluating EMI effects and designing electromagnetic protection for memristive neuromorphic systems.

Current-controlled grounded memristor emulator circuit based on analog multiplier

This paper proposes a current-controlled grounded memristor emulator circuit based on single four-quadrant analog multiplier, a resistor and a capacitor. The behavioral model of the proposed emulator circuit is analyzed, highlighting its characteristics. Experimental results are given to investigate its ability for different operating frequencies and they are in accordance with theoretical analysis and simulation results. By using a divider circuit, the memristance variation in the time domain is obtained. It is observed that the pinched hysteresis loop at high frequency loses symmetry due in part to the shift that introduces a multiplication of sinusoidal signals.

A training strategy for improving the robustness of memristor-based binarized convolutional neural networks

Memristor-based convolutional neural networks (CNNs) have been extensively studied in the field of edge computing, owing to the efficient characteristics of memristors, such as high integration density and powerful processing capability. However, constrained by the low yield of memristor array and the memristance variation, memristor-based CNNs have failed to be widely applied. Consequently, a training strategy is proposed to improve the robustness of memristor-based binarized neural networks for prompting embedded application. Simulation results on the MNIST dataset reveal that this strategy is able to improve the performance of a memristor-based two-layer CNN with device defects. Specifically, when the yield rate of the memristor array is 60%, the recognition rate of a two-layer memristor-based binarized convolutional neural network achieves around 91.19%, and when the characteristic of device variation is 28%, it reaches about 91.53%.

Noise and Memristance Variation Tolerance of Single Crossbar Architectures for Neuromorphic Image Recognition.

We performed a comparative study on the Gaussian noise and memristance variation tolerance of three crossbar architectures, namely the complementary crossbar architecture, the twin crossbar architecture, and the single crossbar architecture, for neuromorphic image recognition and conducted an experiment to determine the performance of the single crossbar architecture for simple pattern recognition. Ten grayscale images with the size of 32 × 32 pixels were used for testing and comparing the recognition rates of the three architectures. The recognition rates of the three memristor crossbar architectures were compared to each other when the noise level of images was varied from −10 to 4 dB and the percentage of memristance variation was varied from 0% to 40%. The simulation results showed that the single crossbar architecture had the best Gaussian noise input and memristance variation tolerance in terms of recognition rate. At the signal-to-noise ratio of −10 dB, the single crossbar architecture produced a recognition rate of 91%, which was 2% and 87% higher than those of the twin crossbar architecture and the complementary crossbar architecture, respectively. When the memristance variation percentage reached 40%, the single crossbar architecture had a recognition rate as high as 67.8%, which was 1.8% and 9.8% higher than the recognition rates of the twin crossbar architecture and the complementary crossbar architecture, respectively. Finally, we carried out an experiment to determine the performance of the single crossbar architecture with a fabricated 3 × 3 memristor crossbar based on carbon fiber and aluminum film. The experiment proved successful implementation of pattern recognition with the single crossbar architecture.

Four quadrant analog multiplier based memristor emulator using single active element

This paper presents a novel Four Quadrant Analog Multiplier (FQAM) circuit and its applications using a single active element Current Differencing Transconductance Amplifier (CDTA) and two NMOS. This circuit has a cascadability feature as it produces current and voltage outputs at high and low impedance ports, respectively. It offers additional features such as resistor-less realization, operability in voltage and trans-conductance mode, and configurable structure. Further, the FQAM circuit is configured to develop a memristor emulator based on the proposed mathematical analogy. The proposed memristor circuit contains active elements (one CDTA, two NMOS, and one Inverting Voltage buffer) and only one grounded capacitor. It offers tunability using the transconductance gain of the CDTA block. Also, the proposed memristor emulator circuit doesn’t contain any additional multiplier block. The emulator circuit can be operated in both the Incremental and the Decremental mode of memristance variation. The results demonstrate the non-volatile property as well as hysteresis behavior for the wide frequency range. The effects of statistical variation in passive component, threshold voltage, and aspect ratios on the proposed circuits using Monte-Carlo simulation have been estimated. Also, the impact of non-idealities and the parasitic effects of the CDTA on the proposed circuits are investigated. In last, the capacitor-less version of the memristor emulator and its hysteresis characteristics have been demonstrated. The simulation results obtained using HSPICE, are agreed well with the theoretical analysis.

Variability analysis of resistive ternary content addressable memories

SummaryResistive ternary content addressable memories (Re‐TCAMs) are considered a potential platform for in‐memory associative processing. Re‐TCAM permits the store and process of the data in the same physical area, allowing in‐memory computing. Given the unique properties of the non‐volatile memristive device, Re‐TCAM is capable of low search energy, large‐scale storage, and massively parallel processing. However, like any other semiconductor, memristor as a nanodevice suffers from fabrication process imperfections that provoke a significant variance in their high (RH) and low (RL) resistance states. These variations might lead to the malfunction of the Re‐TCAM array and affect its performance and reliability. This paper proposes a simplified mathematical formulation of the memristor state variability for 2T2M bit‐cell‐based Re‐TCAM array. We present a comprehensive statistical design, considering different circuit parameters and variance effects, such as tolerance of memristance variation, the memristor ratio ( ), transistor technology, and memory width. The impact of these parameters on the performance is formulated as the probability of error is extensively studied, and a closed‐form expression for the optimal threshold voltage is derived. The utility of the presented investigation is illustrated using a design example with real device parameters.

Improving the Variation-Tolerance of Memristor Synapse by Selecting the Optimal Memristance

Memristor crossbar array that has a lot of advantageous features such as non-volatile, high-density, and low-power, is potentially used for realizing artificial neural networks. One of the important factors affecting the performance of crossbar circuits is memristance variation. The variation of memristance causes the variation of synaptic weights resulting in the degradation of the performance of the neural networks. In this paper, the variation-tolerance of memristor synapse is improved by minimized the gradient of the synaptic weight function. To reduce the gradient of synaptic weight function, the memristance values of memristors must be close to the high resistance state. This can be achieved by selecting the value of bias resistance because memristance values of memristors in crossbar-based neural network are distributed around the bias resistance value. In the simulation result, we measure the recognition of crossbar circuit for recognizing the MNIST handwritten digits with the variation is in range of 0% to 10% and the value of bias resistance varies from 30KΩ to 80KΩ. For the bias resistance is as low as 30KΩ, the recognition rate of the crossbar circuit is as low as 17%, when the variation is 10%. When the bias resistance is 80KΩ, the recognition is 70%, when the variation is 10%. When the range of memristance is close to the high resistance state, the recognition rate is improved by 53% when the variation is 10%.

Memristor-CMOS Hybrid Circuit for Temporal-Pooling of Sensory and Hippocampal Responses of Cortical Neurons.

As a software framework, Hierarchical Temporal Memory (HTM) has been developed to perform the brain’s neocortical functions, such as spatial and temporal pooling. However, it should be realized with hardware not software not only to mimic the neocortical function but also to exploit its architectural benefit. To do so, we propose a new memristor-CMOS (Complementary Metal-Oxide-Semiconductor) hybrid circuit of temporal-pooling here, which is composed of the input-layer and output-layer neurons mimicking the neocortex. In the hybrid circuit, the input-layer neurons have the proximal and basal/distal dendrites to combine sensory information with the temporal/location information from the brain’s hippocampus. Using the same crossbar architecture, the output-layer neurons can perform a prediction by integrating the temporal information on the basal/distal dendrites. For training the proposed circuit, we used only simple Hebbian learning, not the complicated backpropagation algorithm. Due to the simple hardware of Hebbian learning, the proposed hybrid circuit can be very suitable to online learning. The proposed memristor-CMOS hybrid circuit has been verified by the circuit simulation using the real memristor model. The proposed circuit has been verified to predict both the ordinal and out-of-order sequences. In addition, the proposed circuit has been tested with the external noise and memristance variation.

Generalized modeling and character analyzing of composite fractional-order memristors in series connection

Memristor is a type of memory device representing the relation between charge q and flux $$\varphi $$ . Recently, memristor, as well as other memristive elements and their corresponding fractional elements, have become very attractive in many applications, due to their unique behavior which cannot be obtained by using conventional elements. However, there are few studies about composite behaviors or characteristics of multiple memristive elements connected in series or parallel, especially for the fractional-order memristors. This paper focuses on analyzing the composite characteristics of two fractional-order memristors connected in series as well as concerning the window function. Under the applied sinusoidal current source, two charge-controlled memristors connected in series are adopted to theoretically demonstrate the variation of memristance and v–i curves. The two fractional order $$\alpha $$ and $$\beta $$ are interpreted as two phase offset which makes the analysis much convenient. The obtained formulas of instantaneous memristance of composite memristor are derived and some influential factors are analyzed in detail. The further analyzing demonstrates that the composite memristor circuits behave as a new memristor with higher complexity and some typical phenomena are found especially for the pinched hysteresis loops in v–i plane.

Novel designs of spiking neuron circuit and STDP learning circuit based on memristor

Abstract The pure circuit implementation of STDP is a worthwhile work. In this study, a novel spiking neuron circuit and STDP learning circuit based on memristors are designed. The proposed spiking neuron circuit, which is based on conventional leaky integrate-and-fire neuron and utilizes the nonlinear variation of memristance, is served to generate spikes. Different release thresholds and amplitudes of the spikes can be obtained through tuning circuit parameters. Extending on the spiking neuron circuit, a STDP learning circuit is built to perform unsupervised learning behaviors. Furthermore, a crossbar array architecture is finally considered to fabricate multi-input multi-output spiking neural network which also perform STDP learning effectively. Circuit simulation results in PSPICE prove the availability of the two proposed circuits.

Sequential Memristor Crossbar for Neuromorphic Pattern Recognition

Most of human's intelligent behaviors such as inference, prediction, anticipation, etc. are based on the processing of sequential data from human's sensory systems. Thus, a sequential memory that can process sequential information is very essential to mimic brain's intelligent behaviors. In this paper, we propose a new sequential memristor crossbar which is regarded as the first memristor circuit that copes with the sequential data. The new crossbar is composed of two layers which are the base layer and the sequential one, respectively. The base layer can recognize only static items one by one. The sequential layer can detect the serial order of items and find the best match with the detected sequence among many reference sequences stored in the memristor array. The new crossbar can recognize the tested sequences of items as well as 88.6% on average for the memristance variation of 0%. The variation tolerance is also tested from 0-% variation to 20-% variation in the proposed sequential crossbar.

Linearized Programming of Memristors for Artificial Neuro-Sensor Signal Processing.

A linearized programming method of memristor-based neural weights is proposed. Memristor is known as an ideal element to implement a neural synapse due to its embedded functions of analog memory and analog multiplication. Its resistance variation with a voltage input is generally a nonlinear function of time. Linearization of memristance variation about time is very important for the easiness of memristor programming. In this paper, a method utilizing an anti-serial architecture for linear programming is proposed. The anti-serial architecture is composed of two memristors with opposite polarities. It linearizes the variation of memristance due to complimentary actions of two memristors. For programming a memristor, additional memristor with opposite polarity is employed. The linearization effect of weight programming of an anti-serial architecture is investigated and memristor bridge synapse which is built with two sets of anti-serial memristor architecture is taken as an application example of the proposed method. Simulations are performed with memristors of both linear drift model and nonlinear model.

신경회로망용 멤리스터 브릿지 회로에서 가중치 프로그램의 시간에 대한 선형화 효과

Memristor is a new kind of memory device whose resistance varies depending upon applied charge and whose previous resistance state is preserved even when its power is off. Ordinary memristor has a nonlinear programming characteristics about time when a constant voltage is applied. For the easiness of programming, it is desirable that resistance is programmed linearly about time. We had proposed previously a memristor bridge configuration with which weight can be programmed nicely in positive, negative or zero. In memristor bridge circuit, two memristors are connected in series with different polarity. Memristors are complementary each other and it follows that the memristance variation is linear with respect to time. In this paper, the linearization effect of weight programming of memristor bridge synapse is investigated and verified about both memristor from HP and a nonlinear memristor with a window function. Memristor bridge circuit would be helpful to conduct synaptic weight programming.

Research of coupling behavior based on series-parallel flux-controlled memristor

Memristor is a nanoscale element with low power consumption and high integration, having great potential in applications. A single memristor has rich electrical properties, and its series-parallel circuit exhibits more abundant dynamic behaviors. However, memristors' coupled effects cannot be ignored in high-density integrated environment. Therefore, this paper first deduces the mathematical model of coupled memristor in detail based on the coupled flux controlled memristors. Second, considering the different polarity connection and coupling strength, we discuss the coupled condition of two flux-controlled memristors in series and parallel connections. Then the detailed theoretical analysis is illustrated, and the variation of memristance in terms of voltage, time and flux as well as the relations between voltage and currents are examined via numerical simulations to further explore the influence of coupled effects on the memristive system. At the same time, a graphical user interface of series-parallel coupled circuit based on Matlab is designed. Through this interface, we can adjust the initial value of memristor and coupling coefficient, select different connection modes, obtain corresponding connection diagram and output waveform which intuitively show the dynamic behavior of different parameters directly and provide experimental reference for further study of the circuit design. Furthermore, this paper shows the influence of initial value on the normal working range of memristors in the presence of coupling. From the table 1 it can be easily obtained that when the memristors are connected in the same direction, the range of memristance without coupling is greater than that with coupling. And the situation is opposite when the memristors are connected in different directions. Finally, the hysteresis curve with different coupling coefficients and the change of memristance with time are shown via building the Pspice simulator of coupled memristors, so the coupling effects of memristor is confirmed by circuit simulations. Experimental results reflect that the coupling with the same polarity enhances the change of resistance, and the coupling with different polarity with slow down it. Such dynamical properties can be well utilized in memristive networks and provide a strong theoretical basis for the comprehensive consideration of the design of memristive system.