Memory Subsystem Research Articles

SEAMS

Memory approximation techniques are commonly limited in scope, targeting individual levels of the memory hierarchy. Existing approximation techniques for a full memory hierarchy determine optimal configurations at design-time provided a goal and application. Such policies are rigid: they cannot adapt to unknown workloads and must be redesigned for different memory configurations and technologies. We propose SEAMS: the first self-optimizing runtime manager for coordinating configurable approximation knobs across all levels of the memory hierarchy. SEAMS continuously updates and optimizes its approximation management policy throughout runtime for diverse workloads. SEAMS optimizes the approximate memory configuration to minimize energy consumption without compromising the quality threshold specified by application developers. SEAMS can (1) learn a policy at runtime to manage variable application quality of service ( QoS ) constraints, (2) automatically optimize for a target metric within those constraints, and (3) coordinate runtime decisions for interdependent knobs and subsystems. We demonstrate SEAMS’ ability to efficiently provide functions (1)–(3) on a RISC-V Linux platform with approximate memory segments in the on-chip cache and main memory. We demonstrate SEAMS’ ability to save up to 37% energy in the memory subsystem without any design-time overhead. We show SEAMS’ ability to reduce QoS violations by 75% with < 5% additional energy.

The Effect of Structured Exercise on Short-Term Memory Subsystems: New Insight on Training Activities.

It has been shown that exercise positively affects cognitive abilities, such as frontal functions and long-term memory processes. We tried to understand whether different exercises (i.e., an open-skill activity, a team game, vs. a closed-skill activity, a circuit) might specifically influence different short-term-memory (STM) subsystems of working memory. We examined the effect of a single bout of open- and closed-skill exercises on three STM tasks (i.e., verbal, visuo-spatial, and motor) in children attending the 3rd and 4th classes at primary school. One group was tested before and after (T0 and T1) an Italian class (control group), one group before and after 30-min exercise on a circuit, and one group before and after 30-min of a team game. The control group presented no improvement. The open-skill activity improved short-term memory performance in all the participants at T1 (p < 0.001 for children attending the 3rd class, and p = 0.007 for children attending the 4th class). In contrast, closed-skill activity improved short-term memory performance in older children (those attending the 4th class; p = 0.046) at T1. Importantly, this finding was found in a school setting and might have ecological validity. Therefore, the exercise protocol here used might help to structure specific training activities for both normal children and those with learning deficits to positively improve short-term memory abilities.

Mansard Roofline Model: Reinforcing the Accuracy of the Roofs

Continuous enhancements and diversity in modern multi-core hardware, such as wider and deeper core pipelines and memory subsystems, bring to practice a set of hard-to-solve challenges when modeling their upper-bound capabilities and identifying the main application bottlenecks. Insightful roofline models are widely used for this purpose, but the existing approaches overly abstract the micro-architecture complexity, thus providing unrealistic performance bounds that lead to a misleading characterization of real-world applications. To address this problem, the Mansard Roofline Model (MaRM), proposed in this work, uncovers a minimum set of architectural features that must be considered to provide insightful, but yet accurate and realistic, modeling of performance upper bounds for modern processors. By encapsulating the retirement constraints due to the amount of retirement slots, Reorder-Buffer and Physical Register File sizes, the proposed model accurately models the capabilities of a real platform (average rRMSE of 5.4%) and characterizes 12 application kernels from standard benchmark suites. By following a herein proposed MaRM interpretation methodology and guidelines, speed-ups of up to 5× are obtained when optimizing real-world bioinformatic application, as well as a super-linear speedup of 18.5× when parallelized.

On-Board Decision Making in Space with Deep Neural Networks and RISC-V Vector Processors

The use of deep neural networks (DNNs) in terrestrial applications went from niche to widespread in a few years, thanks to relatively inexpensive hardware for both training and inference, and large datasets available. The applicability of this paradigm to space systems, where both large datasets and inexpensive hardware are not readily available, is more difficult and thus still rare. This paper analyzes the impact of DNNs on the system-level capabilities of space systems in terms of on-board decision making (OBDM) and identifies the specific criticalities of deploying DNNs on satellites. The workload of DNNs for on-board image and telemetry analysis is analyzed, and the results are used to drive the preliminary design of a RISC-V vector processor to be employed as a generic platform to enable energy-efficient OBDM for both payload and platform applications. The design of the memory subsystem is carried out in detail to allow full exploitation of the computational resources in typically resource-constrained space systems.

Совместное использование технологий OpenMP и MPI на узлах вычислительного кластера

This work is devoted to the problem of implementing an efficient parallel program that solves the asigned task using the maximum available amount of computing cluster resources in order to obtain the corresponding gain in performance with respect to the sequential version of the algorithm. The main objective of the work was to study the possibilities of joint use of the parallelization technologies OpenMP and MPI, considering the characteristics and features of the problems being solved, to increase the performance of executing parallel algorithms and programs on a computing cluster. This article provides a brief overview of approaches to calculating the sequential programs complexity functions. To determine the parallel programs complexity, an approach based on operational analysis was used. The features of the sequential programs parallelization technologies OpenMP and MPI are described. The main software and hardware factors affecting the execution speed of parallel programs on the nodes of a computing cluster are presented. The main attention in this paper is paid to the study of the impact on performance of computational and exchange operations number ratio in programs. To implement the research, parallel OpenMP and MPI testing programs were developed, in which the total number of operations and the correlation between computational and exchange operations are set. A computing cluster consisting of several nodes was used as a hardware and software platform. Experimental studies have made it possible to confirm the effectiveness of the hybrid model of a parallel program in multi-node systems with heterogeneous memory using OpenMP in shared memory subsystems, and MPI in a distributed memory subsystems

A Compute Cache System for Signal Processing Applications

Nowadays, processing systems are constrained by the low efficiency of their memory subsystems. Although memories evolved into faster and more efficient devices through the years, they were still unable to keep up with the computational power offered by processors, i.e., feed the processors with the data they require at the rhythm it is consumed. Consequently, with the advent of Big Data, the need for fetching large amounts of data from memory became the most prominent performance bottleneck. Naturally, several approaches seeking to mitigate this problem have arisen through the years, such as application-specific accelerators and Near Data Processing (NDP) solutions. However, none were capable to offer a satisfactory general-purpose solution without imposing rather limiting constraints. For instance, NDP solutions often require the programmer to have low-level knowledge of how data is physically stored in memory. In this paper, we propose an alternative mechanism that operates at the cache level, leveraging both proximity to the data and the parallelism enabled by accessing an entire cache line per cycle. We detail the internal architecture of the Cache Compute System (CCS) and demonstrate its integration with a conventional high-performance ARM Cortex-A53 Central Processing Unit (CPU). Furthermore, we assess the performance benefits of the novel CCS using an extensive set of microbenchmarks as well as six kernels widely used in the context of Convolutional Neural Networks (CNNs) and clustering algorithms. Results show that the CCS provides performance improvements ranging from 3.9× to 40.6× regarding the six tested kernels.

Computing En-Route for Near-Data Processing

The data explosion and faster data analysis demand have spawned emerging applications that operate over myriads of data and exhibit large memory footprints with low data reuse rate. Such characteristics lead to enormous data movements across the memory hierarchy and pose significant pressure on modern communication fabrics and memory subsystems. To mitigate the worsening gap between high processor computation density and deficient memory bandwidth, memory networks, and near-data processing techniques are proposed to keep improving system performance and energy efficiency. In this article, we propose Active-Routing, an in-network near-data processing architecture for data-flow execution, which enables computation en-route by exploiting patterns of aggregation over intermediate results. The proposed architecture leverages the massive memory cube- and vault-level parallelism as well as network concurrency to optimize the aggregation operations along a dynamically built Active-Routing Tree. It also introduces page granular computation offloading to amortize the offloading overhead and improve the throughput. Compared to the state-of-the-art processing-in-memory architecture, the evaluations show that the baseline Active-Routing can achieve up to 7× speedup with an average of 60 percent performance improvement, and reduce the energy-delay product by 80 percent across various benchmarks. Further optimizations with vault-level parallelism and page granular offloading can achieve an extra order of magnitude improvement.

Computational Resource Consumption in Convolutional Neural Network Training – A Focus on Memory

Deep neural networks (DNNs) have grown in popularity in recent years thanks to the increase in computing power and the size and relevance of data sets. This has made it possible to build more complex models and include more areas of research and application. At the same time, the amount of data generated during the training process of these models puts great pressure on the capacity and bandwidth of the memory subsystem and, as a direct consequence, has become one of the biggest bottlenecks for the scalability of neural networks. Therefore, the optimizing of the workloads produced by DNNs in the memory subsystem requires a detailed understanding of access to the memory and the interactions between the processor, accelerator devices, and the system memory hierarchy. However, contrary to what would be expected, most DNN profilers work at a high level, so they only perform an analysis of the model and individual layers of the network leaving aside the complex interactions between all the hardware components involved in the training. This article shows the characterization performed using a convolutional neural network implemented in the two most popular frameworks: TensorFlow and Pytorch. Likewise, the behavior of the component interactions is discussed by varying the batch size for two sets of synthetic data and showing the results obtained by the profiler created for the study. Moreover, the results obtained when evaluating the AlexNet version on TensorFlow and its similarity in behavior when using a basic CNN are included.

Network-on-a-chip of a new microprocessor generation with the Elbrus architecture

The paper describes a network-on-chip of a new microprocessor generation with the Elbrus architecture, taking into account the peculiarities of physical design. The network-on-a-chip under consideration plays a central role in the scaling process of the microprocessor, interconnecting all the main components of the system and ensuring the transfer of all types of packets between devices. The characteristics of the network-on-a-chip determine the bandwidth and access time to the memory subsystem.

Investigating memory prefetcher performance over parallel applications: From real to simulated

AbstractMemory prefetcher algorithms are widely used in processors to mitigate the performance gap between the processors and the memory subsystem. The complexities behind the architectures and prefetcher algorithms, however, not only hinder the development of accurate architecture simulators, but also hinder understanding the prefetcher's contribution to performance, on both a real hardware and in a simulated environment. In this paper, we contribute to shed light on the memory prefetcher's role in the performance of parallel High‐Performance Computing applications, considering the prefetcher algorithms offered by both the real hardware and the simulators. We performed a careful experimental investigation, executing the NAS parallel benchmark (NPB) on a real Skylake machine, and as well in a simulated environment with the ZSim and Sniper simulators, taking into account the prefetcher algorithms offered by both Skylake and the simulators. Our experimental results show that: (i) prefetching from the L3 to L2 cache presents better performance gains, (ii) the memory contention in the parallel execution constrains the prefetcher's effect, (iii) Skylake's parallel memory contention is poorly simulated by ZSim and Sniper, and (iv) Skylake's noninclusive L3 cache hinders the accurate simulation of NPB with the Sniper's prefetchers.

Developmental neuroscience of memory: research status and future prospect

<p indent=0mm>Memory is crucial for the acquisition of the tremendous amount of knowledge and skills and thus it is the basis of human survival and development. Then, how do learning and memory performance and neural mechanisms change with age? Around the core issue, this article first summarized the research results in recent years, especially those about some important memory subsystems such as working memory and long-term memory (including explicit and implicit memory). Then we revealed the research status in the field of developmental neuroscience of memory and predicted the future direction. On the basis of the work mentioned above, we put forward following suggestions to promote research work in China: (i) making further studies on the neural mechanisms of learning and memory and solving critical problems in this field; (ii) strengthening research on brain mechanisms of learning and memory of children and the elderly; (iii) paying attention to longitudinal studies; (iv) establishing more comprehensive brain-behavior models; (v) strengthening applied studies.

Performance Evaluation of Memory-Centric ARMv8 Many-Core Architectures: A Case Study with Phytium 2000+

This article presents a comprehensive performance evaluation of Phytium 2000+, an ARMv8-based 64-core architecture. We focus on the cache and memory subsystems, analyzing the characteristics that impact the high-performance computing applications. We provide insights into the memory-relevant performance behaviours of the Phytium 2000+ system through micro-benchmarking. With the help of the well-known rooine model, we analyze the Phytium 2000+ system, taking both memory accesses and computations into account. Based on the knowledge gained from these micro-benchmarks, we evaluate two applications and use them to assess the capabilities of the Phytium 2000+ system. The results show that the ARMv8-based many-core system is capable of delivering high performance for a wide range of scientific kernels.

High-Performance Predictable NVM-Based Instruction Memory for Real-Time Embedded Systems

Worst case execution time and energy consumption are two of the most important design constraints of real-time embedded systems and memory subsystem has a major impact on both of them. Therefore, many recent studies have tried to improve the memory subsystem of embedded systems by using emerging non-volatile memories instead of conventional memories such as SRAM and DRAM. Indeed, the low leakage power dissipation and improved density of emerging non-volatile memories make them prime candidates for replacing the conventional memories. However, accessing these memories imposes performance and energy overhead and using them as the instruction memory could increase the worst case execution time, which would have a negative impact on the system. Furthermore, most previous studies that have tried to address such problems have focused on the data memory and therefore their solutions are not suitable for the instruction memory. In this paper, a new instruction memory architecture for non-volatile memories is proposed which reduces the effective memory access latency by employing memory access interleaving technique. Unlike common instruction access latency improvement techniques such as prefetching which usually increase the worst case execution time of the system, the proposed architecture is predictable and does not increase the worst case execution time of the system. Furthermore, it improves both average case execution time and energy consumption of the system and requires no changes to the application code. The proposed architecture has been evaluated using different applications from MiBench and Malardalen benchmark suites and the results show that compared to previous studies, the proposed architecture can improve the memory energy consumption, the average case execution time, and the worst case execution time of the system by 73, 61, and 27 percent respectively.

Bypassing Multicore Memory Bugs with Coarse-Grained Reconfigurable Logic

Multicore systems deploy sophisticated memory hierarchies to improve memory operations' throughput and latency, by exploiting multiple levels of cache hierarchy and several complex memory-access instructions. As a result, the functional verification of the memory subsystem is one of the most challenging tasks in the overall system design effort, leading to many bugs escaping into the released product. In this work we propose MemPatch, a novel reconfigurable hardware solution to bypass such escaped bugs. To design MemPatch, we first analyzed publicly available errata documents and classified memory-related bugs by root cause and symptoms. We then leveraged that learning to design a specialized, reconfigurable detection fabric, implementing finite state machines that can model the bug-triggering events at the microarchitectural level. Finally we complemented this detection logic with hardware offering multiple bug-bypassing options. Our evaluation of MemPatch mapped a multicore RISC-V out-of-order processor, augmented with our logic, to a Xilinx ZCU102 FPGA board. When configured to detect up to 32 distinct bugs, MemPatch entails 7.6% area and 7.3% power overheads. An estimate on a commercial ARM Cortex-A57 processor target indicates that the area overhead would be much lower, 1.0%. The performance impact was found to be no more than 1% in all cases.

RIO: ROB-Centric In-Order Modeling of Out-of-Order Processors

Architectural studies of the cache and memory hierarchy need a fast simulation model for the processor core that accurately conveys the impact of memory subsystem changes on application performance. We propose the RIO model (ROB-centric In-order model for Out-of-order cores), a single-pass core performance model based on finding the earliest possible future issue time for out-of-order execution. RIO can natively model second-order effects of overlapping and interacting miss events, significantly improving accuracy over interval simulation. Yet it is no more complex to implement and run, providing a compelling speedup over more detailed models. We implement RIO in Sniper and evaluate it on 2000+ application traces, and find it has an average absolute prediction error of 10.3 percent over Sniper's most detailed model, while simulating 2.8× faster on average (up to 5× on memory-bound workloads).

Affective forecasting: A selective relationship with working memory for emotion.

Affective forecasting (AF), the ability to predict one's future feelings, is important for decision making. We posit that AF entails the ability to maintain and evaluate an emotional feeling state, and thus requires affective working memory (AWM; Mikels & Reuter-Lorenz, 2019). To test this hypothesis, a series of studies investigated whether individual differences in AWM are related to AF ability. In the first study, we document that measures of AWM and AF are positively related, whereas an analogous measure of visual working memory is unrelated to AF in separate groups of participants. Two further within-group studies (1 preregistered) demonstrate that maintenance of affective information predicts AF performance, whereas maintenance of brightness information does not. Further, 2 additional measures of visual working memory (Corsi block-tapping and change detection) did not independently predict AF ability. Taken together the results demonstrate a reliable and selective relationship between AWM and AF, suggesting that AWM is a separable working memory subsystem and an elemental capacity that contributes to the type of higher-order emotional processes involved in AF. (PsycInfo Database Record (c) 2021 APA, all rights reserved).

Real-World Objects Are Represented in Visual Long-Term Memory Both as Unbound Features and as Bound Objects.

Real-World Objects Are Represented in Visual Long-Term Memory Both as Unbound Features and as Bound Objects.

Cooperative Memory Expansion via OS Kernel Support for Networked Computing Systems

The growing popularity of in-memory computing for bigdata analytics often causes performance bottlenecks to memory subsystem resided in operating systems (OS). This article purposes cooperative memory expansion (COMEX), an OS kernel extension. COMEX establishes a stable pool of memory collectively across nodes in a cluster and enhances OS's memory subsystem for memory aggregation from connected machines by allowing process's page table to track remote memory page frames without programmer effort or modifications to application codes. COMEX employs Remote Direct Memory Access (RDMA) for low-latency data transfer with destination kernel bypassed and does not rely on an old design of the I/O block subsystem usually adopted by all known remote paging. COMEX fits soundly in the emerging system design approach of resource disaggregation which breaks hard walls between server-centric machines into a new design paradigm of separated resource pools. The new architecture facilitates both system scaling-up and scaling-out, also eliminates imbalance resources existing in datacenters. We have implemented COMEX based on Linux kernel 3.10.87 and deployed on our 32 networked servers. Performance evaluation results under ten applications from two benchmark suites reveal the speedup of up to 170 times when application execution footprints are 10 times larger than available system memory.

The effect of a secondary task on drivers’ gap acceptance and situational awareness at junctions

The current studies explored the roles of the visuospatial and phonological working memory subsystems on drivers’ gap acceptance and memory for approaching vehicles at junctions. Drivers’ behaviour was measured in a high-fidelity driving simulator when at a junction, with, and without a visuospatial or phonological load. When asked to judge when to advance across the junction, gap acceptance thresholds, memory for vehicles and eye movements were not different when there was a secondary task compared to control. However, drivers’ secondary task performance was more impaired in the visuospatial than phonological domain. These findings suggest that drivers were able to accept impairment in the secondary task while maintaining appropriate safety margins and situational awareness. These findings can inform the development of in-car technologies, improving the safety of road users at junctions. Practitioner summary: Despite research indicating that concurrent performance on working memory tasks impairs driving, a matched visuospatial or phonological memory load did not change drivers’ gap acceptance or situational awareness at junctions. Drivers displayed appropriate compensatory behaviour by prioritising the driving task over the visuospatial secondary task. Abbreviations: ROW: right of way; RIG: random time interval generation

Real-Time Personalized Atrial Fibrillation Prediction on Multi-Core Wearable Sensors

In the recent Internet-of-Things (IoT) era where biomedical applications require continuous monitoring of relevant data, edge computing keeps gaining more and more importance. These new architectures for edge computing include multi-core and parallel computing capabilities that can enable prevention diagnosis and treatment of diseases in ambulatory or home-based setups. In this article, we explore the benefits of the parallelization capabilities and computing heterogeneity of new wearable sensors in the context of a personalized online atrial fibrillation (AF) prediction method for daily monitoring. First, we apply optimizations to a single-core design to reduce energy, based on patient-specific training models. Second, we explore multi-core and memory banks configuration changes to adapt the computation and storage requirements to the characteristics of each patient. We evaluate our methodology on the Physionet Prediction Challenge (2001) publicly available database, and assess the energy consumption of single-core (ARM Cortex-M3 based) and new ultra-low power multi-core architectures (open-source RISC-V based) for next-generation of wearable platforms. Overall, our exploration at the application level highlights that a parallelization approach for personalized AF in multi-core wearable sensors enables energy savings up to 24% with respect to single-core sensors. Moreover, including the adaptation of the memory subsystem (size and number of memory banks), in combination with deep sleep energy saving modes, can overall provide total energy savings up to 34%, depending on the specific patient.