Required Memory Size Research Articles

Interference cancellation technique for faster‐than‐Nyquist signalling

The faster-than-Nyquist (FTN) signalling is a bandwidth-efficient technology which has drawn attention in the bandwidth-starved world. However, inter-symbol interference is introduced by transmitting signals at a higher signalling rate than allowed by the Nyquist criterion. Decision feedback equalisation (DFE) cancellation is an efficient signal detection scheme for FTN-based communication system. However, since the DFE interference cancellation is executed by overall matrix computation, the required memory size is very large. In order to reduce the complexity of the interference cancellation process, a novel simple interference cancellation is proposed. Simulation results show that the scheme can perform better than DFE, and its complexity is very low because of the absence of QR decomposition.

Stepless tunable four-chip LED lighting control on a black body radiation curve using the generalized reduced gradient method

This study proposes an algorithm for calculating the outputs of a stepless, tunable, four-chip LED according to a black body radiation curve; the proposed algorithm is based on the generalized reduced gradient method. The lumen outputs of the four-chip LEDs were calculated in real time at color temperatures ranging between 2500 K and 6500 K without using a lookup table, enabling achieving high-quality lighting designs. Finally, the algorithms for the stepless dimming method, with average color shift Duv 0.0027, is proposed. This algorithm has much smaller memory size requirements for the microcontroller unit than the current method.

A Comment on “Fast Bloom Filters and Their Generalization”

A Bloom filter is a data structure that provides probabilistic membership checking. Bloom filters have many applications in computing and communications systems. The performance of a Bloom filter is measured by false positive rate, memory size requirement, and query (or memory look-up) overhead. A recent paper by Qiao et al. proposes the Fast Bloom Filter, also called Bloom-1, which requires only a single memory look-up for a membership test. Bloom-1 achieves a reduced query overhead at the expense of a slightly higher false positive rate for a given memory size. The false positive rate of Bloom-1 has been analyzed theoretically by Qiao et al. relying on a well-known, but flawed, approximation for the false positive rate for a Bloom filter. In this comment paper we show that the Qiao et al. analysis of Bloom-1 under-estimates the false positive rate for low loads. We provide a correct analysis of Bloom-1 yielding an expression for the exact false positive rate.

고속 패킷 분류를 위한 2차원 비트맵 트라이

인터넷 라우터에서 행해지는 패킷분류는 5가지 패킷 헤더를 검사하여 선속도로 처리해야하기 때문에, 라우터가 수행하기 어려운 기능 중 하나이다. 본 논문에서는 리프-푸싱 된 영역분할 사분트라이 기반 비트맵 트라이 구조 (leaf-pushed AQT bitmap trie)를 제안한다. 제안하는 구조는 영역분할 사분트라이(Area-based Quad Trie, AQT)에 기초하되 불필요한 칩-외부메모리 접근을 줄이고자 리프-푸싱(leaf-pushing)기법을 적용하고, 멀티 비트 트라이인 비트맵을 적용하여 패킷분류 속도와 확장성을 모두 향상시킨 구조이다. 성능 평가를 위하여 ACL FW, IPC 룰셋을 각각 1k, 5k, 10k로 크기를 증가시키며 실험을 진행하였다. 그 결과, 제안하는 구조에서는 룰 셋의 종류나 크기와는 상관없이 패킷분류를 위하여 필요한 칩-외부메모리 접근 횟수가 1번 이내임을 확인할 수 있었다. 또한, 비트맵 트라이를 적용함으로 인해, 리프-푸싱기반 영역분할 사분트라이와 비교하여 약 50%의 칩-내부메모리 접근이 요구됨을 보았으며, 또한 칩-내부메모리 요구량의 변화폭이 룰 셋이 증가함에 따라 안정적으로 변화하여 제안하는 구조의 확장성을 확인할 수 있었다. Packet classification carried out in Internet routers is one of the challenging tasks, because it has to be performed at wire-speed using five header fields at the same time. In this paper, we propose a leaf-pushed AQT bitmap trie. The proposed architecture applies the leaf-pushing to an area-based quad-trie (AQT) to reduce unnecessary off-chip memory accesses. The proposed architecture also applies a bitmap trie, which is a kind of multi-bit tries, to improve search performance and scalability. For performance evaluation, simulations are conducted by using rule sets ACL, FW, and IPC, with the sizes of 1k, 5k, and 10k. Simulation results show that the number of off-chip memory accesses is less than one regardless of set types or set sizes. Additionally, since the proposed architecture applies a bitmap trie, the required number of on-chip memory accesses is the 50% of the leaf-pushed AQT trie. In addition, our proposed architecture shows good scalability in the required on-chip memory size, where the scalability is identified by the stable change in the required memory sizes, as the size of rule sets increases.

Resolution enhancement of images for further pattern recognition applications

In storing large databases of images such as fingerprint and medical databases, the required memory size becomes a great challenge. This work demonstrates a framework for reducing the size of large image databases used in pattern recognition applications with decimation, and reconstructing the images with their original sizes using interpolation for feature extraction. For pattern recognition applications, a new trend based on Mel-Frequency Cepstral Coefficients (MFCCs) is presented in the paper. To reconstruct the images to their original sizes, interpolation methods like bilinear, bicubic, warped-distance, and neural methods are investigated and compared. The sensitivity of the extracted features from the images to the interpolation method used is studied. For the feature extraction process, the interpolated images are converted into one dimensional signals with lexicographic ordering and employed in time domain or transformed to Discrete Wavelet Transform (DWT), Discrete Sine Transform (DST), or Discrete Cosine Transform (DCT) domain. The MFCCs and polynomial shape coefficients are then extracted to generate the database of features, which can be used for pattern identification using neural networks. The pattern recognition is conducted by getting features from the pattern image under test. Experimental results show that feature extraction from an interpolated image to retain the original image dimensions can be used robustly for pattern recognition. In addition, the results reveal that the best domain for feature extraction is the DCT.

An Efficient Distributed Arithmetic-Based Realization of the Decision Feedback Equalizer

A distributed arithmetic (DA)-based decision feedback equalizer architecture for IEEE 802.11b PHY scenarios is presented. As the transmission data rate increases, the hardware complexity of the decision feedback equalizer increases due to requirement for large number of taps in feed forward and feedback filters. DA, an efficient technique that uses memories for the computation of inner product of two vectors, has been used since DA-based realization of filters can lead to great computational savings. For higher-order filters, the memory-size requirement in DA would be high, and so ROM decomposition has been employed. The speed is further increased by employing digit-serial input operation. Two architectures have been presented, namely the direct-memory architecture and reduced-memory architecture where the later is derived using the former. A third architecture has also been presented where the offset-binary coding scheme is employed along with the ROM decomposition and digit-serial variants of DA. Synthesis results on Altera Cyclone III EP3C55F484C6 FPGA show that the proposed DA-based implementations are free of hardware multipliers and use less number of hardware resources compared to the multiply-and-accumulate-based implementation.

ON CHIP MEMORY REDUCTION TECHNIQUE FOR DATA DOMINATED EMBEDDED SYSTEMS

This paper proposes an approach for optimization of on-chip memory size in data dominated embedded systems. Large amount of array processing is being involved in this category. In order to produce a cost effective system, efficient designing of memory module is quite critical. The memory module configuration being selected by the designer should be well suitable for the application. In this regard, this paper presents a methodology for effective optimization of on-chip memory. For sensitive applications involving large array processing, the entire processing has to be done using embedded modules. While using such module s, care should be taken to meet optimized profile for the design metrics. With help of loop transformation technique, relatively a good amount of memory size requirement is reduced for the arrays. This approach results in a very close memory estimate and an effective optimization. This methodology can be further extended to meet the high level memory optimization applications based on cache characteristics. Speech processing front end mechanism is implemented and shows that this approach gives up to an achievement 61.3% reduction of overall system memory requirement over the estimation approach. Results are provided in terms of comparison of the two approaches of memory estimation and optimization with respect to both of the program and data segments.

Phase-searching look-up table method for computer-generated holograms

A phase-searching look-up table (PS-LUT) method is proposed to dramatically reduce the memory size of the new look-up table (N-LUT) method as well as to keep its advantage of fast computational speed. Small quantities of samples are chosen as the basic phase points (BPPs) in the principle fringe pattern (PFP), and phases of the object points for BPPs are precalculated and stored in the table. The phases of object point for the whole PFP could be quickly obtained through a phase-searching method. With proper reference beam phases, PFP could be rapidly generated. The experimental results reveal that the computational speed of the proposed method is about 24 times faster than that of the ray-tracing method, and the required memory size is 1731 times less than that of the N-LUT method. To eliminate the coherent noise of the N-LUT and PS-LUT, the random PFP N-LUT (RN-LUT) and PS-LUT (RPS-LUT), in which the PFP is randomly chosen for every object point, are put forward. The reconstructed images with a spatial light modulator indicate that both the RN-LUT and RPS-LUT methods are extremely effective in improving the quality of the reconstructed images.

ScaleGPU: GPU Architecture for Memory-Unaware GPU Programming

Programmer-managed GPU memory is a major challenge in writing GPU applications. Programmers must rewrite and optimize an existing code for a different GPU memory size for both portability and performance. Alternatively, they can achieve only portability by disabling GPU memory at the cost of significant performance degradation. In this paper, we propose ScaleGPU, a novel GPU architecture to enable high-performance memory-unaware GPU programming. ScaleGPU uses GPU memory as a cache of CPU memory to provide programmers a view of CPU memory-sized programming space. ScaleGPU also achieves high performance by minimizing the amount of CPU-GPU data transfers and by utilizing the GPU memory's high bandwidth. Our experiments show that ScaleGPU can run a GPU application on any GPU memory size and also improves performance significantly. For example, ScaleGPU improves the performance of the hotspot application by ~48% using the same size of GPU memory and reduces its memory size requirement by ~75% maintaining the target performance.

Role and member selection in team formation using resource estimation for large-scale multi-agent systems

We propose an efficient team formation method for multi-agent systems consisting of self-interested agents in task-oriented domains where agents have no prior knowledge of the resources/abilities of the other agents. Internet services based on services computing and cloud computing, which have been rapidly increasing, are usually achieved by combining a number of service elements that are distributed over the Internet. We modelled the executions of these elements as teams of agents with the resources and abilities required in the corresponding service elements. This team formation method with the appropriate agents for the service elements makes the entire system efficient. Our proposed method is based on our previous parameter learning method that enables agents to identify their roles in forming a team but requires prior knowledge of all others' resources. This restricts the applicability to real systems. The contribution of this paper is twofold. First, we extended our original method by adding a resource estimation method. Second, we further improved the first extension for large scale multi-agent systems by introducing purviews, which are a relatively small set of agents that are potential members of the teams, for practical computational time and required memory size. We experimentally evaluated our first method by comparing it with the previous method and the task allocation using the contract net protocol (CNP). Then, after increasing the number of agents, we evaluated our second extended method and investigated how the number of agents and the size of the purview affected the overall performances. Results showed that the learning speed was faster in the proposed method so it outperformed other methods in a practical sense even though it did not require prior knowledge of resources in other agents in busy, large-scale, multi-agent systems.

Low-cost scratchpad memory organizations using heterogeneous cell sizes for low-voltage operations

Modern digital signal processors (DSPs) execute diverse applications ranging from digital filters to video decoding. These applications have drastically different arithmetic precision and scratch pad memory (SPM) size requirements. To minimize power consumption, DSPs often support aggressive dynamic voltage/frequency scaling (DVFS) techniques, requiring on-chip memory, such as SPM, to operate at low voltages. However, increasing process variations with aggressive technology scaling have significantly increased the failure rate of on-chip memory designed with small transistors operating at low voltages. Consequently, designs must use either larger and/or more transistors to have memory cells satisfy a target minimum operating voltage (VMIN) under a failure rate constraint. Yet using larger and/or more transistors for the SPM, which consumes a large fraction of the chip area, is costly. In this paper, we first propose SPM designs that exploit (i) the characteristics of applications and (ii) the tradeoffs between memory cell size and VMIN. Our approach can reduce the SPMs chip area by up to 17% and VMIN by up to 52.5mV. Second, we exploit the error-tolerant characteristics of some applications. Our proposed SPM can support lower VMIN with less mean square error than a conventional SPM with shortened word width. For error-sensitive applications that require high precision, we can lower VMIN at the cost of reduced memory capacity. This approach may negatively impact the performance of applications with large memory footprints. However, we demonstrate that such applications are typically constrained by their execution latency requirements and are likely to operate at higher voltages/frequencies than applications with smaller memory footprints to satisfy their real-time execution constraints.

Improve Scheduling Task based Task Grouping in Cloud Computing System

In recently years, the information communication technology (ICT) appeared new paradigm of utility computing called cloud computing. The consumer cloud is always important of high performance for cloud computing service and satisfy service agree level (SLA). In cloud computing, there is a need of further improvement in task scheduling algorithm to group of tasks, which will reduce the response time and enhance computing resource utilization. This grouping strategy considers the processing capacity, memory size and service type requirement of each task to realize the optimization for cloud computing environment. It also improves computation/communication ratio and utilization of available resources by grouping the user tasks before resource allocation. The experimental results were conducted in a simulation cloud computing environment by generator services and tasks request for consumer cloud. The results show that gives comparator between our strategies and improve activity based costing algorithm.

A Proposed Scalable Design and Simulation of Wireless Sensor Network-Based Long-Distance Water Pipeline Leakage Monitoring System

Anomalies such as leakage and bursts in water pipelines have severe consequences for the environment and the economy. To ensure the reliability of water pipelines, they must be monitored effectively. Wireless Sensor Networks (WSNs) have emerged as an effective technology for monitoring critical infrastructure such as water, oil and gas pipelines. In this paper, we present a scalable design and simulation of a water pipeline leakage monitoring system using Radio Frequency IDentification (RFID) and WSN technology. The proposed design targets long-distance aboveground water pipelines that have special considerations for maintenance, energy consumption and cost. The design is based on deploying a group of mobile wireless sensor nodes inside the pipeline and allowing them to work cooperatively according to a prescheduled order. Under this mechanism, only one node is active at a time, while the other nodes are sleeping. The node whose turn is next wakes up according to one of three wakeup techniques: location-based, time-based and interrupt-driven. In this paper, mathematical models are derived for each technique to estimate the corresponding energy consumption and memory size requirements. The proposed equations are analyzed and the results are validated using simulation.

분할된 RRT 공간을 이용한 Simulink/Stateflow모델 테스트케이스 생성

This paper proposes a black-box based test case generation method for Simulink/Stateflow model utilizing the RRT algorithm which is a method to efficiently solve the path planning for complicated systems. The proposed method in the paper tries to solve the reachability problem with the RRT algorithm, which has to be solved for black-box based test case generations. A major problem of the RRT based test case generation algorithms is that the cost such as running time and required memory size is too much for complicated Stateflow model. The typical RRT algorithm expands rapidly-exploring random tree (RRT) in a single state space. But the proposed method expands it in dynamic state space based on the state of Simulink model, consequently reducing the cost. In the paper, a new definition of RRT state space, a distance measure and a test case generation algorithm are proposed. The performance of proposed method is verified through the experiment against Stateflow model.

Online belief propagation algorithm for probabilistic latent semantic analysis

Probabilistic latent semantic analysis (PLSA) is a topic model for text documents, which has been widely used in text mining, computer vision, computational biology and so on. For batch PLSA inference algorithms, the required memory size grows linearly with the data size, and handling massive data streams is very difficult. To process big data streams, we propose an online belief propagation (OBP) algorithm based on the improved factor graph representation for PLSA. The factor graph of PLSA facilitates the classic belief propagation (BP) algorithm. Furthermore, OBP splits the data stream into a set of small segments, and uses the estimated parameters of previous segments to calculate the gradient descent of the current segment. Because OBP removes each segment from memory after processing, it is memory-efficient for big data streams. We examine the performance of OBP on four document data sets, and demonstrate that OBP is competitive in both speed and accuracy for online expectation maximization (OEM) in PLSA, and can also give a more accurate topic evolution. Experiments on massive data streams from Baidu further confirm the effectiveness of the OBP algorithm.

Iterative Multiuser Detection of Spectrally Efficient FDMA CPM

This paper presents two new iterative multiuser detection algorithms for spectrally efficient frequency division multiple access continuous phase modulation in additive white Gaussian noise. The detectors are derived from the sum-product algorithm and the factor graph framework, performing approximate maximum a posteriori (MAP) bit detection. A factor graph of the actual multiuser detection problem is considered, rather than only factor graphs of the individual single user detection problems combined with ad-hoc inter-user interference cancellation. The practical implementation of the detectors is based on the assumption that a suitable set of sum-product messages can be approximated by a Gaussian distribution. This methodology allows to considerably reduce the computational complexity and memory size requirements as compared to a straightforward application of the sum-product rules. The proposed algorithms further succeed in achieving a good error performance.

Final-State Control Using a Time-Symmetric Polynomial Input

For information devices such as hard disk drives, actuators must be controlled as quickly and precisely as possible. The design of the feedforward input is very important in satisfying these requirements. Therefore, we have proposed design methods based on final-state control so as to reduce its spectrum at the desired frequency points. Furthermore, the final-state control method has been extended to generate the feedforward input using a polynomial. By using a polynomial, the required memory size can be drastically reduced because only the coefficients of the polynomial must be stored. However, when the step number of the input increases, the method may not produce a correct solution because of a numerically ill-posed problem. In this paper, we propose a design method for the final-state control based on a time-symmetric polynomial input. The simulation results show that the proposed method contributes to the improvement of not only the numerically ill-posed problem but also the performance.

Final-State Control Using Polynomial and Time-Series Data

For information devices such as hard disk drives, actuators must be controlled quickly and precisely as much as possible. To satisfy these requirements, feedforward input design is very important. For this problem, we have proposed a frequency-shaped final-state control method. This method can obtain a feedforward input that has lower spectrum at desired frequency points so as to reduce residual vibration after positioning. Furthermore, the method has been extended to generate the feedforward input by a polynomial. By using the polynomial, the required memory size can be drastically reduced because it only requires to store the coefficients of polynomial. However, in the frequency-shaped final-state control method by polynomial input, it is not guaranteed that the solution always exist theoretically. In order to solve this problem, final-state control methods in which the feedforward input is generated by both of a polynomial and time-series data are proposed. The effectiveness of the proposed methods are verified by simulation using the plant model of the HDD benchmark problem. The simulation results show that the proposed method outperform the conventional methods.

Transient Analysis of Plane Wave Reflection from a Lorentz Half Space

A time domain technique based on numerical inversion of Laplace transform is extended and applied to transient analysis of pulses reflected from a Lorentz half space both for TE and TM cases. Its correctness and effectiveness are validated by comparing our results with those published in the literature. With this technique, the TM case when the incident angle is equal to 450 does not need to be processed separately and can be treated as a general case for any incident angle. This technique brings good accuracy in both late and early time, a simple algorithm, short calculation time, small required memory size and readily controlled error.

Numerical simulation of the solidification of pure melt by a phase-field model using an adaptive computation domain

In this paper, we present a phase-field model with a grid based on the Finite-Difference Method, for improvement of computational efficiency and reducing the memory size requirement. The numerical technique, which is based on the temperature change of the pure material, enables us to use, in the initial steps of the computation, a very small computational domain. Subsequently, in the course of the simulation of the solidification process, the computation domain expands around the dendrite. The computation showed that the dendrite with well-developed secondary arms can be obtained with low computation time and moderate memory demand. The computational efficiency of this numerical technique, the microstructural evolution during the solidification, and competitive growth between side-branches are discussed.