Memory Power Consumption Research Articles

A CASE FOR HYBRID INSTRUCTION ENCODING FOR REDUCING CODE SIZE IN EMBEDDED SYSTEM-ON-CHIPS BASED ON RISC PROCESSOR CORES

Embedded computing differs from general purpose computing in several aspects. In most embedded systems, size, cost and power consumption are more important than performance. In embedded System-on-Chips (SoC), memory is a scarce resource and it poses constraints on chip space, cost and power consumption. Whereas fixed instruction length feature of RISC architecture simplifies instruction decoding and pipeline implementation, its undesirable side effect is code size increase caused by large number of unused bits. Code size reduction minimizes memory size, chip space and power consumption all of which are significant for low power portable embedded systems. Though code size reduction has drawn the attention of architects and developers, the solutions currently used are more of cure than of prevention. Considering the huge number of embedded applications, there is a need for a dedicated processor optimized for low power and portable embedded systems. In the study, we propose a variation of Hybrid Instruction Encoding (HIE) for the embedded processors. Our scheme uses fixed number of multiple instruction lengths with provision for hybrid sizes for the offset and the immediate fields thereby reducing the number of unused bits. We simulated the HIE for the MIPS32 processors and measured code sizes of various embedded applications of MiBench and MediaBench benchmarks using an offline tool developed newly. We noticed up to 27% code reduction for large and medium sized embedded applications respectively. This results in reduction of on-chip memory capacity up to 1 mega bytes that is very significant for SoC based embedded applications. Considering the large market share of embedded systems, it is worth investing in a new architecture and development of dedicated HIE-RISC processor cores for portable embedded systems based on SoCs.

Mechanism of power consumption inhibitive multi-layer Zn:SiO2/SiO2 structure resistance random access memory

In this paper, multi-layer Zn:SiO2/SiO2 structure is introduced to reduce the operation power consumption of resistive random access memory (RRAM) device by modifying the filament formation process. And the configuration of multi-layer Zn:SiO2/SiO2 structure is confirmed and demonstrated by auger electron spectrum. Material analysis together with conduction current fitting is applied to qualitatively evaluate the carrier conduction mechanism on both low resistance state and high resistance state. Finally, single layer and multilayer conduction models are proposed, respectively, to clarify the corresponding conduction characteristics of two types of RRAM devices.

Optimizing GPU energy efficiency with 3D die-stacking graphics memory and reconfigurable memory interface

The performance of graphics processing unit (GPU) systems is improving rapidly to accommodate the increasing demands of graphics and high-performance computing applications. With such a performance improvement, however, power consumption of GPU systems is dramatically increased. Up to 30% of the total power of a GPU system is consumed by the graphic memory itself. Therefore, reducing graphics memory power consumption is critical to mitigate the power challenge. In this article, we propose an energy-efficient reconfigurable 3D die-stacking graphics memory design that integrates wide-interface graphics DRAMs side-by-side with a GPU processor on a silicon interposer. The proposed architecture is a “3D+2.5D” system, where the DRAM memory itself is 3D stacked memory with through-silicon via (TSV), whereas the integration of DRAM and the GPU processor is through the interposer solution (2.5D). Since GPU computing units, memory controllers, and memory are all integrated in the same package, the number of memory I/Os is no longer constrained by the package’s pin count. We can reduce the memory power consumption by scaling down the supply voltage and frequency of memory interface while maintaining the same or even higher peak memory bandwidth. In addition, we design a reconfigurable memory interface that can dynamically adapt to the requirements of various applications. We propose two reconfiguration mechanisms to optimize the GPU system energy efficiency and throughput, respectively, and thus benefit both memory-intensive and compute-intensive applications. The experimental results show that the proposed GPU memory architecture can effectively improve GPU system energy efficiency by 21%, without reconfiguration. The reconfigurable memory interface can further improve the system energy efficiency by 26%, and system throughput by 31% under a capped system power budget of 240W.

Data Structure Optimization for Power- Efficient IP Lookup Architectures

Power consumption has become a limiting factor in designing next generation network routers. Recent observation shows that IP lookup engines dominate the power consumption of core routers. Previous work on reducing power consumption of routers mainly focused on network- and system-level optimizations. This paper represents the first thorough study on the data structure optimization for lowering the power consumption in static random access memory (SRAM)-based IP lookup engines. Three different SRAM-based IP lookup architectures are discussed: nonpipelined, simple pipelined, and memory-balanced pipelined architectures. For each architecture, we formulate the problem of power minimization by revisiting the time-space tradeoff in multibit tries. Two distinct multibit trie algorithms are investigated: the expanded trie and the tree bitmap trie, which are widely used in SRAM-based IP lookup solutions. A theoretical framework is proposed to determine the optimal strides for building a multibit trie so that the worst-case power consumption of the IP lookup architecture is minimized. Experiments using real-life routing tables including both IPv4 and IPv6 data sets demonstrate that careful selection of strides in building the multibit tries can reduce the power consumption dramatically. We believe our methodology can be applied to other variants of multibit tries and can help in designing more power-efficient SRAM-based IP lookup architectures.

ADDRESSING MEMORY EFFECT FOR RAIL-TO-RAIL COMPARATOR WITH NEAR-THRESHOLD SUPPLY VOLTAGE

Ultra-low voltage comparators with rail-to-rail input ranges are critical components in the design of low-voltage low-power analog to digital converters (ADCs). This paper investigates the memory effect of a commonly used comparator when its power supply is scaled down to near transistor threshold voltage levels. It also studies when such memory effects are most likely to occur during the conversion sequences of successive approximation register (SAR) ADCs. Subsequently an improved comparator design is presented to overcome the memory effect with near-threshold voltage power supply. The impacts of the proposed design modification on comparator speed, offset voltage and power consumptions are discussed. Based on a 0.13 μm CMOS technology and with a 0.5 V power supply, the proposed comparator is compared with the original comparator in terms of memory effect, speed, power consumption and input offset voltage. The integral and differential nonlinearity (INL and DNL) of 10-bit SAR ADCs with using the proposed and original comparators are also compared.

Optical contrast and laser-induced phase transition in GeCu2Te3 thin film

Fast crystallization and low power amorphization are essential to achieve rapid data recording and low power consumption in phase-change memory. This work investigated the laser-induced phase transition behaviors of GeCu2Te3 film based on the reflectance of amorphous and crystalline states. The GeCu2Te3 film showed a reflectance decrease upon crystallization, which was the opposite behavior in Ge2Sb2Te5 film. The crystallization starting time of the as-deposited GeCu2Te3 film was as fast as that of the as-deposited Ge2Sb2Te5 film. Furthermore, the GeCu2Te3 crystalline film was found to be reamorphized by laser irradiation at lower power and shorter pulse width than the Ge2Sb2Te5.

Reactive Ion Etching of Si<SUB><I>x</I></SUB>Sb<SUB>2</SUB>Te in CF<SUB>4</SUB>/Ar Plasma for Nonvolatile Phase-Change Memory Device

Si(x)Sb2Te material system is novel for phase-change random access memory applications. Its properties are more outstanding than the widely used material Ge2Sb2Te5. Etching process is one of the critical steps in the device fabrication. The etching characteristics of phase-change material Si(x)Sb2Te were studied with CF4/Ar gas mixture by a reactive ion etching system. The changes of etching rate, etching profile and surface root-mean-square roughness resulted from variation of the gas-mixing ratio were investigated under constant pressure (50 mTorr) and applying power (200 W). Si0.34Sb2Te is with the highest phase-change speed and the lowest power consumption in the PCRAM memory among these compositions, which means it is the most promising candidate for the PCRAM applications. So the most optimized CF4/Ar gas ratio for Si0.34Sb2Te was studied, the value is 25/25. The etching rate is 155 nm/min, and the selectivity of Si0.34Sb2Te to SiO2 is as high as 3.4 times. Furthermore, the smooth surface was achieved with this optimized gas ratio.

A data aware 9T static random access memory cell for low power consumption and improved stability

ABSTRACTReducing the power consumption in static random access memory can significantly improve the system power efficiency, reliability, and performance. In this paper, we propose a data aware static random access memory cell to reduce the power consumption during read and write operation. The proposed cell contains nine transistors with separate read/write ports. The write operation in the proposed cell is controlled by an additional write signal instead of word line. Because of isolation of the storage nodes with bit lines, read signal‐to‐noise margin is equal to ideal hold signal‐to‐noise margin of the conventional cell. The proposed cell saves approximately more than 43% active power compared with the 6T cell and other published cells. The proposed cell gives faster write access and low leakage current compared with the conventional and other cells. About 99% standby column power reduction, with 128 cells, is observed in the proposed cell. Copyright © 2013 John Wiley & Sons, Ltd.

A Low-Power Packet Memory Architecture with a Latency-Aware Packet Mapping Method

A packet memory stores packets in internet routers and it requires typically RTT×C for the buffer space, e.g. several GBytes, where RTT is an average round-trip time of a TCP flow and C is the bandwidth of the router's output link. It is implemented with DRAM parts which are accessed in parallel to achieve required bandwidth. They consume significant power in a router whose scalability is heavily limited by power and heat problems. Previous work shows the packet memory size can be reduced to $\frac{RTT\times C}{\sqrt{N}}$, where N is the number of long-lived TCP flows. In this paper, we propose a novel packet memory architecture which splits the packet memory into on-chip and off-chip packet memories. We also propose a low-power packet mapping method for this architecture by estimating the latency of packets and mapping packets with small latencies to the on-chip memory. The experimental results show that our proposed architecture and mapping method reduce the dynamic power consumption of the off-chip memory by as much as 94.1% with only 50% of the packet buffer size suggested by the previous work in realistic scenarios.

Techniques for Compensating Memory Errors in JPEG2000

This paper presents novel techniques to mitigate the effects of SRAM memory failures caused by low voltage operation in JPEG2000 implementations. We investigate error control coding schemes, specifically single error correction double error detection code based schemes, and propose an unequal error protection scheme tailored for JPEG2000 that reduces memory overhead with minimal effect in performance. Furthermore, we propose algorithm-specific techniques that exploit the characteristics of the discrete wavelet transform coefficients to identify and remove SRAM errors. These techniques do not require any additional memory, have low circuit overhead, and more importantly, reduce the memory power consumption significantly with only a small reduction in image quality.

Low-Power Time Deinterleaver for ISDB-T Receiver

A time deinterleaver structure for Terrestrial Integrated Services Digital Broadcasting (ISDB-T) is presented to reduce power consumption in synchronous dynamic random-access memory (SDRAM). ISDB-T exploits long time interleaving, which requires many long delay buffers at the deinterleaving of the receiver. The conventional single-pointer structure reduces the number of the pointer registers, but it shows inefficiency with SDRAM. The proposed structure allocates the delay buffers appropriately for reducing the number of SDRAM accesses and row activations and, as a result, the SDRAM power consumption. Experimental result shows that SDRAM power consumption is reduced by 24%.

Application of ordered mesoporous SiO2 film for low power consumption in phase-change memory

This article presents an application of ordered mesoporous films to phase-change memory (PCM). Though ordered mesoporous SiO2 films have attracted attention due to their regular arrangement of nanometer-sized pores, they have not yet become an integral component in any application and have not been produced in a practical manner. Also, even though PCMs are potential next-generation memory devices, they have not made large market due to high power consumption, heat interference, and other shortcomings. In this work, ordered mesoporous SiO2 films were applied to an interlayer dielectric in PCM as a thermal insulating layer, resulting in one-quarter lower power consumption in PCM devices through the reduction of the power consumed in the RESET operation.

Complete System Power Estimation Using Processor Performance Events

This paper proposes the use of microprocessor performance counters for online measurement of complete system power consumption. The approach takes advantage of the "trickle-down” effect of performance events in microprocessors. While it has been known that CPU power consumption is correlated to processor performance, the use of well-known performance-related events within a microprocessor such as cache misses and DMA transactions to estimate power consumption in memory and disk and other subsystems outside of the microprocessor is new. Using measurement of actual systems running scientific, commercial and productivity workloads, power models for six subsystems (CPU, memory, chipset, I/O, disk, and GPU) on two platforms (server and desktop) are developed and validated. These models are shown to have an average error of less than nine percent per subsystem across the considered workloads. Through the use of these models and existing on-chip performance event counters, it is possible to estimate system power consumption without the need for power sensing hardware.

Material Engineering for Low Power Consumption and Multi-Level Storage in Lateral Phase-Change Memory

The influence of the phase-change materials on the performance of memory devices for low power consumption and multi-level storage was investigated in this work. Doping N into chalcogenide phase-change materials resulted in higher resistivity and low-response to the temperature. The former characteristic leaded to high heating efficiency for phase change via self-heating and thus reduced the power consumption to about 1/20. The latter characteristic enabled easy control of phase change process in the memory device for multi-level storage. 16 distinct resistance levels were demonstrated in our lateral device by adopting a top heater structure

A survey of architectural techniques for DRAM power management

Recent trends of CMOS technology scaling and wide-spread use of multicore processors have dramatically increased the power consumption of main memory. It has been estimated that modern data-centres spend more than 30% of their total power consumption in main memory alone. This excessive power dissipation has created the problem of 'memory power wall' which has emerged as a major design constraint inhibiting further performance scaling. Recently, several techniques have been proposed to address this issue. The focus of this paper is to survey several architectural techniques designed for improving power efficiency of main memory systems, specifically DRAM systems. To help the reader in gaining insights into the similarities and differences between the techniques, this paper also presents a classification of the techniques on the basis of their characteristics. The aim of this paper is to equip the engineers and architects with knowledge of the state of the art DRAM power saving techniques and motivate them to design novel solutions for addressing the challenges presented by the memory power wall problem.

Nano Superlattice-like Materials as Thermal Insulators for Phase-Change Random Access Memory

ABSTRACTNanoscale superlattice-like (SLL) dielectric was employed to reduce the power consumption of the Phase-change random access memory (PCRAM) cells. In this study, we have simulated and found that the cells with the SLL dielectric have a higher peak temperature compared to that of the cells with the SiO2 dielectric after constant pulse activation, due to the interface scattering mechanism. Scaling of the SLL dielectric has resulted in higher peak temperatures, which can be even higher after material/structural modifications. Furthermore, the SLL dielectric has good material properties that enable the cells to have high endurance. This shows the effectiveness of the SLL dielectric for advanced memory applications.

Register allocation for write activity minimization on non-volatile main memory for embedded systems

Non-volatile memories are good candidates for DRAM replacement as main memory in embedded systems and they have many desirable characteristics. Nevertheless, the disadvantages of non-volatile memory co-exist with its advantages. First, the lifetime of some of the non-volatile memories is limited by the number of erase operations. Second, read and write operations have asymmetric speed or power consumption in non-volatile memory. This paper focuses on the embedded systems using non-volatile memory as main memory. We propose register allocation technique with re-computation to reduce the number of store instructions. When non-volatile memory is applied as the main memory, reducing store instructions will reduce write activities on non-volatile memory. To re-compute the spills effectively during register allocation, a novel potential spill selection strategy is proposed. During this process, live range splitting is utilized to split certain long live ranges such that they are more likely to be assigned into registers. In addition, techniques for re-computation overhead reduction is proposed on systems with multiple functional units. With the proposed approach, the lifetime of non-volatile memory is extended accordingly. The experimental results demonstrate that the proposed technique can efficiently reduce the number of store instructions on systems with non-volatile memory by 33% on average.

Adaptive granularity memory systems

We propose adaptive granularity to combine the best of fine-grained and coarse-grained memory accesses. We augment virtual memory to allow each page to specify its preferred granularity of access based on spatial locality and error-tolerance tradeoffs. We use sector caches and sub-ranked memory systems to implement adaptive granularity. We also show how to incorporate adaptive granularity into memory access scheduling. We evaluate our architecture with and without ECC using memory intensive benchmarks from the SPEC, Olden, PARSEC, SPLASH2, and HPCS benchmark suites and micro-benchmarks. The evaluation shows that performance is improved by 61% without ECC and 44% with ECC in memory-intensive applications, while the reduction in memory power consumption (29% without ECC and 14% with ECC) and traffic (78% without ECC and 66% with ECC) is significant.

1.8 V Low-Transient-Energy Adaptive Program-Voltage Generator Based on Boost Converter for 3D-Integrated NAND Flash SSD

In this paper we present an adaptive program-voltage generator for 3D-integrated solid state drives (SSDs) based on a boost converter. The converter consists of a spiral inductor, a high-voltage MOS circuit, and an adaptive-frequency and duty-cycle (AFD) controller. The spiral inductor requires an area of only 5 × 5 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> in an interposer. The high-voltage MOS circuit employs a mature NAND flash process. The AFD controller, implemented in a conventional low-voltage MOS process, dynamically optimizes clock frequencies and duty cycles at different values of output voltage, V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">OUT</sub> . The power consumption, rising time, and circuit area of the program-voltage generator are 88%, 73%, and 85% less than those of a program-voltage generator with a conventional charge pump, respectively. The total power consumption of each NAND flash memory is reduced by 68%. We also present the design methodology of the high-voltage MOS circuit of the boost converter with a conventional NAND flash process, in which charge-pump-based program-voltage generators are implemented.

A comprehensive study of energy efficiency and performance of flash-based SSD

Use of flash memory as a storage medium is becoming popular in diverse computing environments. However, because of differences in interface, flash memory requires a hard-disk-emulation layer, called FTL (flash translation layer). Although the FTL enables flash memory storages to replace conventional hard disks, it induces significant computational and space overhead. Despite the low power consumption of flash memory, this overhead leads to significant power consumption in an overall storage system. In this paper, we analyze the characteristics of flash-based storage devices from the viewpoint of power consumption and energy efficiency by using various methodologies. First, we utilize simulation to investigate the interior operation of flash-based storage of flash-based storages. Subsequently, we measure the performance and energy efficiency of commodity flash-based SSDs by using microbenchmarks to identify the block-device level characteristics and macrobenchmarks to reveal their filesystem level characteristics.