Memory Management Unit Research Articles

A 1.71-million transistor CMOS CPU chip with a testable cache architecture

A CISC CPU chip for the business computer is described. It contains an integer unit (IU), a double-precision floating-point unit (FPU), an address generation unit (AGU), and a Harvard-style memory unit with cache. The memory includes two independent memory management units (DMMU and IMMU), an 8-kB D-cache, a 32-B store buffer (SB), and a bus-controller unit (BCU). An on-chip PLL (phase-locked loop) synchronizes external and internal clock edges with a skew of 1-ns. The chip is fabricated in a 0.8- mu m CMOS double-polysilicon double-metal technology. A 77- mu m/sup 2/ SRAM (static random-access memory) cell uses a high resistance load formed by the second polysilicon layer. The 16.3-mm*12.7-mm chip contains 1.71-M transistors. In 40-MHz operation, power consumption is 6 W with a 5-V supply. The design is verified by simulations at several levels, using a microsimulator for evaluating parallelism of a large horizontal microprogram. >

Memory management support for tiled array organization

Organization of two dimensional array data into sub-arrays, sometimes called tiles, has been known to provide better performance than either row or column ordering since the late 1960s. Yet the tiling of arrays is little used today. Although some image processing and graphics memory systems have provided tile access modes, tiling has never been provided in a general purpose way.A novel method is described which adds support for tiled arrays to an otherwise conventional paged memory management unit. The result is that pages contain two dimensional tiles of data rather than one dimensional strips, making tiled virtual memory transparently available to general purpose application programs. Extending this new tiling method, the same benefits are shown to support sub-arrays with three or more dimensions. Finally, the image memory management unit of the Kodak Prophecy Color Publishing System is shown as an example implementation of tiled virtual memory.

The Mips R4000 processor

The R4000, a highly integrated, 64-b RISC microprocessor that provides a simple solution to the increasing demands on the size of address space while maintaining full compatibility with previous Mips processors, is described. The microprocessor's on-chip central processing unit, floating point unit, memory management unit, primary caches, system interface logic, secondary cache control logic with flexible interface, the programmable system interface for high-performance multiprocessor servers and low-cost desktop systems, the flexible multiprocessor support, and the 1.2 million transistors implemented in CMOS technology are discussed. The R4000's superpipelining techniques allow it to process more instructions simultaneously than the previous generation of microprocessors. It is shown that, according to SPEC benchmark tests, it achieves the highest performance of any microprocessor chip. >

The design and implementation of VOOM: a parallel virtual Object Oriented machine

The architecture of a highly-parallel general-purpose computer system supporting the Object-Oriented model of computation is presented. The basic features of the architecture are described with the aid of a low-level Virtual Machine, which has served as a basis for hardware implementations. The proposed parallel architecture consists of self-contained computers interconnected through a packet-switching network. Each node is a microcomputer comprising: (a) an execution unit, which provides direct support to the object-oriented style by processing messages; (b) a pre-fetch unit which realizes an early-bind scheme; (c) a memory management unit which is responsible for object management and memory recycling; and (d) a communication unit, which implements inter-node message passing and intra-node scheduling.

The architecture of a memory management unit for object-oriented systems

We describe the rationale for the design and the architecture of a Memory Management Unit (MMU) for object-oriented systems. The CAMOES 1 MMU supports arbitrary size protected objects mapped on a single virtual address space. Support for object invocations is provided in the form of an operations cache closely coupled with the addressing hardware. The MMU only executes in hardware those functions crucial for performance; other functions and, namely, the management of internal buffers and associative memories, and object management policies, are handled in software. This functional organisation is suitable for current generation processors based on RISC principles and is able to support open multi-lingual environments.

Microprocessor architectures and systems: RISC, CISC and DSP

Part 1 Complex instruction set computers: enter the MC68000 complex instructions, Microcode and Nanocode the MC68000 hardware M68000 asynchronousbus M6800 synchronousbus the user/supervisor concept the MC68010 virtual memory processor MC68010 supervisor resource the MC68008. Part 2 32-bit CISC processors: enter HCMOS technology the MC68020 32-bit performance standard coprocessor interface MC68881 and MC68882 floating point coprocessors the MC68851 paged memory management unit (PMMU) the MC68030, the first commercial 50 MHz. Part 3 The rise challenge: the 80/20 rule the initial RISC research the Berkeley model the Stanford model the catalysts the M88000 family the MC88100 programming model the MC88100 instruction set MC88100 external functions M88200 cache MMU the MBUS protocol M88000 master/checker fault tolerance. Part 4 Digital signal processing: the DSP56000 family move commands. Part 5 Memory, memory management and caches: shadow RAM DRAM v SRAM optimizing the DRAM interface memory management multitasking and user/supervisor conflicts. Part 6 Real time software interrupts and exceptions: interrupting an MC88100 MC88100 interrupt service routines interrupting the DSP56000 triadic instruction sets register windowing the M68300 family. Part 7 Multiprocessing: SISD - single instruction, single data SIMD - single instruction, multiple data MIMD - multiple instruction, multiple data MISD - multiple instruction, single data constructing a MIMD architecture processor bandwidths. Part 8 Application ideas: MC68020 and MC68030 design techniques for high-reliability applications transparent update techniques for digital filters using the DSP56000 motor and servo control. Part 9 Semiconductor technology: semiconductor technology silicon technology CMOS and bipolar technology. Part 10 The changing design cycle: the changing design cycle the shortening design cycle simulation v emulation. Part 11 Generation: enter the MC68040 the instruction execution unit the bus interface unit the M68300 family DSP96000 combining integration and performance once a new approach to emulation integration and higher performance. Part 12 Selecting a microprocessor architecture: meeting performance needs development support considering all the options. Appendices: benchmarking binary compatibility standards.

A 70‐MHz, 32‐bit BiCMOS processor

AbstractA 70‐MHz, 32‐bit BiCMOS processor has been developed. This paper describes the architecture and the high‐speed technology, mainly the arithmetic unit, of the very‐high‐speed BiCMOS processor. This processor includes a 32‐bit ALU, register file with four ports, arithmetic unit composed of ±32‐bit barrel shifter and so on, ROM storing microprograms, memory management unit, cache controller, and clock generator. The chip integrates 529,000 transistors (including bipolar transistors of 1.5 percent) within 12.98 mm × 12.98 mm chip. The BiCMOS circuit technology is applied to the register file, arithmetic circuit, clock generator, and so on, to achieve the 70‐MHz BiCMOS processor under typical conditions. Thus, the effectiveness of employing the BiCMOS technology for very‐high‐speed digital LSIs, such as microprocessors, has been verified.

Computing perspectives: the rise of the VLSI processor

Around 1970 Intel discovered it could put 2,000 transistorsor perhaps a few moreon a single NMOS chip. In retrospect, this may be said to mark the beginning of very large-scale integration (VLSI), ...

Motorola's 88000 family architecture

The initial members of the 88000 family of high-performance 32-bit microprocessor are the 88100 processor and the 88200 cache and memory management unit (CMMU). The processor manipulates integer and floating-point data and initiates instruction and data memory transactions. The CMMU minimizes the latency of main memory requests by maintaining a cache for data transaction and a cache for memory management translations. A typical system consists of one processor and two identical cache chips, one servicing instruction fetch requests, the other servicing data read and write requests. The overall design process for the 88000 family is described, and the integer instructions are discussed. Decisions made with respect to the processor, cache, and software are examined. Some data on the use of the instruction set by the available compilers and the efficiency of the cache and memory systems are presented. >

Microprocessor memory management units

This tutorial describes the current crop of commercial memory management units (MMUs) for 32-bit microprocessors. The discussion includes both complex- and reduced-instruction-set computers (CISCs and RISCs). The rationale, principles, and issues related to hardware support for memory management and virtual memory are reviewed. The design and features of high-end microprocessor MMUs are reviewed and compared with respect to a common set of criteria. Special attention is paid to Unix requirements and multiprocessor, multiple MMU considerations. The MMUs covered are Intel 80386, i486, and i860; Motorola's 68851 (MMU for the 68020), 68030, 68040, and 88200 (MMU for the 88000 series); the Fujitsu MB86920 (Sparc MMU); and the MIPS R2000/R3000.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

I860 microprocessor internal architecture

How many different types of commercial jet aircraft have been built since 1950? In fact, there have been only a handful of commercial jets, although there have been many variants. The same is true of microprocessors. There have been many variations on relatively few themes. Recent developments in semiconductor technology, the influence of RISC architectures, and the migration of mainframe characteristics to silicon have led to the appearance of some radically new designs. The Intel i860 is one such processor. This article describes the important features of the 64-bit i860: its pipelined organization, floating-point unit, its inherent parallelism, memory management unit, on-chip cache and graphics unit. These features, together with its 80 MFLOPS peak single-precision performance, make the i860 a formidable new computing engine.

A highly integrated 40-MIPS (peak) 64-b RISC microprocessor

A 1-million transistor 64-b microprocessor has been fabricated using 0.8- mu m double-metal CMOS technology. A 40-MIPS (million instructions per second) and 20-MFLOPS (million floating-point operations per second) peak performance at 40 MHz is realized by a self-clocked register file and two translation lookaside buffers (TLBs) with word-line transition detection circuits. The processor contains an integer unit based on the SPARC (scalable processor architecture) RISC (reduced instruction set computer) architecture, a floating-point unit (FPU) which executes IEEE-754 single- and double-precision floating-point operations a 6-KB three-way set-associative physical instruction cache, a 2-KB two-way set-associative physical data cache, a memory management unit that has two TLBs, and a bus control unit with an ECC (error-correcting code) circuit. >

Algorithms and architectures for dynamic programming on Markov chains

Algorithms and architectures are developed for dynamic programming on finite-state Markov chains. The results are applied to phase tracking of a phase-jitter carrier, Viterbi decoding of convolutional codes, and isolated-word recognition using hidden Markov models and dynamic time warping. It is argued that a computing ring, which is really a cyclic systolic array of cells, provides a good tradeoff between performance and complexity for implementation in VLSI. The computing ring may be pipelined with a preprocessor and a memory management unit to achieve a modular design.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

A content addressable memory management unit with on-chip data cache

The design of a single chip (WE-32201) that includes both a content-addressable memory-based management unit and a large data/instruction cache is described. The chip belongs to AT&T's WE-32200 chip set and is fabricated using a 1 mu m twin tub CMOS process. It boosts the performance of the entire chip set significantly by providing high memory bandwidth and virtual-memory-management support. The combination of high-performance circuit design and system architectural design techniques makes the chip a major enhancement to the chip set.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

KCM: a knowledge crunching machine

KCM (Knowledge Crunching Machine) is a high-performance back-end processor which, coupled to a UNIX * desk-top workstation, provides a powerful and user-friendly Prolog environment catering for both development and execution of significant Prolog applications. This paper gives a general overview of the architecture of KCM stressing some new features like a 64-bit tagged architecture, shallow backtracking and an original memory management unit. Some early benchmark results obtained on prototype machines are presented. They show that KCM, which runs at a peak speed of 833 Klips on list concatenation, compares favorably with other dedicated Prolog machines and available commercial systems running on fast general purpose processors.

The design of the 88000 RISC family

The design and implementation of the RISC (reduced-instruction-set computer) 88000 system in high-speed, complementary metal-oxide semiconductor (HCMOS) technology is described. The total system consists of the 88100 processor and two 88200 cache memory management units (CMMUs). The various features and components of the 88000 are discussed.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

A VLSI chip set for a multiprocessor workstation. II. A memory management unit and cache controller

For pt.I see ibid., vol.24, no.6, p.1688-98 (1989). The authors describe a memory management unit and a cache controller (MMU/CC) for a 40-70-MIPS multiprocessor workstation. The MMU/CC implements a novel memory management scheme, in-cache address translation, which does not require a translation lookaside buffer. It also implements a snooping bus protocol to maintain data consistency across all caches in the system. The chip is implemented in a 1.6- mu m double-layer-metal CMOS technology and is being used in a multiprocessor workstation (SPUR) successfully executing a UNIX-like network-based operating system called Sprite as well as many applications, including LISP programs.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

MUTABOR, a coprocessor supporting memory management in an object-oriented architecture

The author describes MUTABOR, a micro-programmable coprocessor that works with a 68020 CPU to control and update a 4096-entry address translation cache that achieves an excellent hit rate. He defines the requirements for an object-oriented memory-management unit, and outlines the architecture of MUTABOR and the object-addressing mechanism. He also discusses the design decisions concerning the address translation cache, which were based on simulation results.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Integrating an on-chip MMU into a highly pipelined architecture

The Memory Management Unit (MMU) is responsible for virtual to physical address translation in a demand paged virtual memory environment. Integrating an MMU with a highly pipelined CPU and physical caches, on a single chip, requires special architectural and design considerations. An on-chip MMU enables the access of the on-chip caches by physical addresses. A working example of a microprocessor, the NS32532, incorporating a four stage execution pipeline, 0.5K byte instruction cache, 1K byte data cache and an MMU with a 64 entry, fully associative Translation Lookaside Buffer, is described. Specifically, architectural decisions and tradeoffs for an on-chip MMU functioning in a pipelined environment are discussed.

Tuning architecture at run-time

We describe the structure and operational mode of a coprocessor system which, when incorporated in a microprogrammed syetem to carry out Dynamic Vertical Migration, improves execution speed for any program. The coprocessor includes an interconnection mechanism between the machine code and the instruction set microcode. The interconnections (Intermediate instructions) are created in parallel with machine instruction execution and so do not increase normal execution time. This intermediate code is stored dynamically in coprocessor memory, saving the fetching and decoding phases in subsequent executions, speeding up the execution of repetitive machine code.The coprocessor structure is organized around three basic elements: Interconnection Memory, Interconnection Memory Management Unit and Coprocessor Control Unit. A software simulator has been developed to analyse coprocessor behaviour and a theoretical model has been formulated from the results ot these analyses.