Memory Management Scheme Research Articles

Leveraging Data Deduplication to Improve the Performance of Primary Storage Systems in the Cloud

With the explosive growth in data volume, the I/O bottleneck has become an increasingly daunting challenge for big data analytics in the Cloud. Recent studies have shown that moderate to high data redundancy clearly exists in primary storage systems in the Cloud. Our experimental studies reveal that data redundancy exhibits a much higher level of intensity on the I/O path than that on disks due to relatively high temporal access locality associated with small I/O requests to redundant data. Moreover, directly applying data deduplication to primary storage systems in the Cloud will likely cause space contention in memory and data fragmentation on disks. Based on these observations, we propose a performance-oriented I/O deduplication, called POD, rather than a capacity-oriented I/O deduplication, exemplified by iDedup, to improve the I/O performance of primary storage systems in the Cloud without sacrificing capacity savings of the latter. POD takes a two-pronged approach to improving the performance of primary storage systems and minimizing performance overhead of deduplication, namely, a request-based selective deduplication technique, called Select-Dedupe, to alleviate the data fragmentation and an adaptive memory management scheme, called iCache, to ease the memory contention between the bursty read traffic and the bursty write traffic. We have implemented a prototype of POD as a module in the Linux operating system. The experiments conducted on our lightweight prototype implementation of POD show that POD significantly outperforms iDedup in the I/O performance measure by up to 87.9 percent with an average of 58.8 percent. Moreover, our evaluation results also show that POD achieves comparable or better capacity savings than iDedup.

MicMR: An efficient MapReduce framework for CPU–MIC heterogeneous architecture

With the high-speed development of processors, coprocessor-based MapReduce is widely studied. In this paper, we propose micMR, an efficient MapReduce framework for CPU–MIC heterogeneous architecture. micMR mainly provides the following new features. First, the two-level split and the SIMD friendly map are designed for utilizing the Vector Process Units on MIC. Second, heterogeneous pipelined reduce is developed for improving the efficiency of resource utilization. Third, a memory management scheme is designed for accessing <key, value> pairs in both the host and the MIC memory efficiently. In addition, optimization techniques, including load balancing, SIMD hash, and asynchronous task transfer, are designed for achieving more speedups. We have developed micMR not only in a single node with CPU and MIC but also in a CPU–MIC heterogeneous cluster. The experimental results show that micMR is up to 8.4x and 45.8x faster than Phoenix++, a high-performance MapReduce system for symmetric multiprocessing system, and up to 2.0x and 5.1x faster than Hadoop in a CPU–MIC cluster.

Durable Address Translation in PCM-based Flash Storage Systems

Phase change memory (PCM) is a promising DRAM alternative because of its non-volatility, high density, low standby power and close-to-DRAM performance. These features make PCM an attractive solution to optimize the management of NAND flash memory in embedded systems. However, PCM's limited write endurance hinders its application in embedded systems. Therefore, how to manage flash memory with PCM-particularly guarantee PCM a reasonable lifetime-becomes a challenging issue. In this paper, we propose to partially replace DRAM using PCM to optimize the management of flash memory metadata for better system reliability in the presence of power failure and system crash. To prolong PCM's lifetime, we present a write-activity-aware PCM-assisted flash memory management scheme, called PCM-FTL. By differentiating sequential and random I/O behaviors, a novel two-level mapping mechanism and a customized wear-leveling scheme are developed to reduce writes to PCM and extend its lifetime. We evaluate PCM-FTL with a variety of general-purpose and mobile I/O workloads. Experimental results show that PCM-FTL can significantly reduce write activities and achieve an even distribution of writes in PCM with very low overhead.

Memory Management Scheme to Improve Utilization Efficiency and Provide Fast Contiguous Allocation without a Statically Reserved Area

Fast allocation of large blocks of physically contiguous memory plays a crucial role to boost the performance of multimedia applications in modern memory-constrained portable devices, such as smartphones, tablets, etc. Existing systems have addressed this issue by provisioning a large statically reserved memory area (SRA) in which only dedicated applications can allocate pages. However, this in turn degrades the performance of applications that are prohibited to utilize the SRA due to the reduced available memory pool. To overcome this drawback while maintaining the benefits of the SRA, we propose a new memory management scheme that uses a special memory region, called page-cache-preferred area (PCPA), in concert with a quick memory reclaiming algorithm. The key of the proposed scheme is to enhance the memory utilization efficiency by enabling to allocate page-cached pages of all applications in the PCPA until predetermined applications require to allocate big chunks of contiguous memory. At this point, clean page-cached pages in the PCPA are rapidly evicted without write-back to a secondary storage. Compared to the SRA scheme, experimental results show that the average launch time of real-world applications and the execution time of I/O-intensive benchmarks are reduced by 9.2% and 24.7%, respectively.

Efficient Memory-Addressing Algorithms for FFT Processor Design

This paper explores efficient memory management schemes for memory-based architectures of the fast Fourier transform (FFT). A data relocation scheme that merges multiple banks to lower the area requirement and power dissipation of memory-based FFT architectures is proposed. The proposed memory-addressing method can effectively deal with single-port, merged-bank memory with high-radix processing elements. Compared with conventional memory-based FFT designs using dual-port memory, the derived architecture has better performance in terms of area and power consumption. The proposed scheme is extended to a cached-memory FFT architecture to further reduce power dissipation. An 8192-point cached-memory FFT processor is implemented for digital video broadcasting-terrestrial/handheld applications by using 0.18- $\mu $ m 1P6M CMOS technology. Experimental results show that the proposed memory scheme consumes 10.1%–29.3% less area and 9.6%–67.9% less power compared with those of the multibank design.

Individual‐specific management of reference data in adaptive ensembles for face re‐identification

During video surveillance, face re-identification allows recognition and targeting of individuals of interest from faces captured across a network of video cameras. In such applications, face recognition is challenging because faces are captured under limited spatial and temporal constraints. In addition, facial models for recognition are commonly designed using a limited number of representative reference samples from faces captured under specific conditions, regrouped into facial trajectories. Given new reference samples (provided by an operator or through some self-updating process), updating facial models may allow maintenance of a high level of performance over time. Although adaptive ensembles have been successfully applied to robust modelling of an individual's facial appearance, reference data samples from a trajectory must be stored for validation. In this study, a memory management strategy based on Kullback-Leiber (KL) divergence is proposed to rank and select the most relevant validation samples over time in adaptive individual- specific ensembles. When new reference samples become available for an individual, updates to the corresponding ensemble are validated using a mixture of new and previously-stored samples. Only the samples with the highest KL divergence are preserved in memory for future adaptations. This strategy is compared with reference classifiers using videos from the face in action data. Simulation results show that the proposed strategy tends to select discriminative samples from wolf-like individuals for validation. It allows maintenance of a high level of performance, while reducing the number of samples per individual by up to 80%.

Receiver memory management method for HARQ in LTE-based satellite communication system

Summary For the successful deployment of the long term evolution (LTE)-based mobile satellite service, the price of a user terminal is one of the major factors. A user terminal for the LTE-based satellite communication needs to be implemented with a similar hardware size that is used for a terrestrial LTE user terminal. However, for quality of service provision, the satellite user terminal needs a larger size of memories than the terrestrial terminal does. This is very evident by considering that the N-channel stop and wait hybrid automatic repeat request requires proportionally increasing memory size by the propagation delay, resulting in unmanageable amount of memories in the satellite system. To resolve this problem, we propose an efficient memory management method at the user terminal when the size of memory is insufficient. The simulation results in this paper reveal that the proposed method can increase the throughput about 20.7% when a user terminal is operated under very low throughput condition with an insufficient memory size, compared with the case without memory management scheme. In addition, we show that the additional throughput gain can be obtained by the packet scheduling using the information of receiver memory status. Copyright © 2015 John Wiley & Sons, Ltd.

An adaptive ensemble-based system for face recognition in person re-identification

Recognizing individuals of interest from faces captured with video cameras raises several challenges linked to changes in capture conditions (e.g., variation in illumination and pose). Moreover, in person re-identification applications, the facial models needed for matching are typically designed a priori, with a limited amount of reference samples captured under constrained temporal and spatial conditions. Tracking can, however, be used to regroup the system responses linked to a facial trajectory (facial captures from a person) for robust spatio-temporal recognition, and to update facial models over time using operational data. In this paper, an adaptive ensemble-based system is proposed for spatio-temporal face recognition (FR). Given a diverse set of facial captures in a trajectory of a target individual, an ensemble of 2-class classifiers is designed. A pool of ARTMAP classifiers is generated using a dynamic PSO-based learning strategy, and classifiers are selected and combined using Boolean combination. To train classifiers, target samples are combined with a set of reference non-target samples selected from the cohort and universal models using One-Sided Selection. During operations, facial trajectories are captured, and each individual-specific ensemble of the system seeks to detect target individuals, and possibly self-update their facial models. To update an ensemble, a learn-and-combine strategy is employed to avoid knowledge corruption, and a memory management strategy based on Kullback---Leibler divergence allows to rank and select stored validation samples over time to bound the system's memory consumption. Spatio-temporal fusion is performed by accumulating classifier predictions over a time window, and a second threshold allows to self-update facial models. The proposed systems were validated with videos from the Face in Action and COX-S2V datasets, that feature both abrupt and gradual patterns of change. At the transaction level, results show that the proposed system allows to increase AUC accuracy by about 3 % for scenarios with abrupt changes, and by about 5 % with gradual changes. Subject-based analysis reveals the difficulties of face recognition with different poses, affecting more significantly the lamb- and goat-like individuals. Compared to reference spatio-temporal fusion approaches, results show that the proposed accumulation scheme produces the highest discrimination.

Integrating Lock-Free and Combining Techniques for a Practical and Scalable FIFO Queue

Concurrent FIFO queues can be generally classified into lock-free queues and combining-based queues. Lock-free queues require manual parameter tuning to control the contention level of parallel execution, while combining-based queues encounter a bottleneck of single-threaded sequential combiner executions at a high concurrency level. In this paper, we introduce a different approach using both lock-free techniques and combining techniques synergistically to design a practical and scalable concurrent queue algorithm. As a result, we have achieved high scalability without any parameter tuning: on an 80-thread average throughput in our experimental results, our queue algorithm outperforms the most widely used Michael and Scott queue by 14.3 times, the best-performing combining-based queue by 1.6 times, and the best performing $\times$ 86-dependent lock-free queue by 1.7 percent. In addition, we designed our algorithm in such a way that the life cycle of a node is the same as that of its element. This has huge advantages over prior work: efficient implementation is possible without dedicated memory management schemes, which are supported only in some languages, may cause a performance bottleneck, or are patented. Moreover, the synchronized life cycle between an element and its node enables application developers to further optimize memory management.

Lazy-RTGC

Due to many attractive and unique properties, NAND flash memory has been widely adopted in mission-critical hard real-time systems and some soft real-time systems. However, the nondeterministic garbage collection operation in NAND flash memory makes it difficult to predict the system response time of each data request. This article presents Lazy-RTGC , a real-time lazy garbage collection mechanism for NAND flash memory storage systems. Lazy-RTGC adopts two design optimization techniques: on-demand page-level address mappings, and partial garbage collection. On-demand page-level address mappings can achieve high performance of address translation and can effectively manage the flash space with the minimum RAM cost. On the other hand, partial garbage collection can provide the guaranteed system response time. By adopting these techniques, Lazy-RTGC jointly optimizes both the average and the worst system response time, and provides a lower bound of reclaimed free space. Lazy-RTGC is implemented in FlashSim and compared with representative real-time NAND flash memory management schemes. Experimental results show that our technique can significantly improve both the average and worst system performance with very low extra flash-space requirements.

Safe and efficient hybrid memory management for Java

Java uses automatic memory management, usually implemented as a garbage-collected heap. That lifts the burden of manually allocating and deallocating memory, but it can incur significant runtime overhead and increase the memory footprint of applications. We propose a hybrid memory management scheme that utilizes region-based memory management to deallocate objects automatically on region exits. Static program analysis detects allocation sites that are safe for region allocation, i.e., the static analysis proves that the objects allocated at such a site are not reachable after the region exit. A regular garbage-collected heap is used for objects that are not region allocatable. The region allocation exploits the temporal locality of object allocation. Our analysis uses coarse-grain source code annotations to disambiguate objects with non-overlapping lifetimes, and maps them to different memory scopes. Region-allocated memory does not require garbage collection as the regions are simply deallocated when they go out of scope. The region allocation technique is backed by a garbage collector that manages memory that is not region allocated. We provide a detailed description of the analysis, provide experimental results showing that as much as 78% of the memory is region allocatable and discuss how our hybrid memory management system can be implemented efficiently with respect to both space and time.

Speeding up the high-accuracy surface modelling method with GPU

In order to find a solution for accurate, topographic data-demanding applications, such as catchment hydrologic modeling and assessments of anthropic activities impact on environmental systems, high-accuracy surface modeling (HASM) method is developed. Although it can produce a digital elevation model (DEM) surface of higher accuracy than classical methods, e.g. inverse distance weighted, spline and kriging, HASM requires numerous iterations to solve large linear systems, which impede its applications in high-resolution and large-scale surface interpolation. This paper aims to demonstrate the utilization of graphics’ processing units (GPUs) device to accelerate HASM in constructing large-scale and high-resolution DEM surfaces. We parallelized the linear system algorithm for solving HASM with Compute Unified Device Architecture, a parallel programming model developed by NVIDIA. We designed a memory-saving strategy to enable the HASM algorithm to run on GPUs. The speedup ratio of GPU-based algorithm was tested and compared with CPU-based algorithm through simulations of both ideal Gaussian synthetic surface and real topographic surface in the loess plateau of Gansu province. The GPU-parallelized algorithm can attain an over 10× speedup ratio with the CPU-based algorithm as a reference. The speedup ratio increases with the scale and resolution of the dataset. The memory management strategy efficiently reduces the memory usage by more than eight times the grid cell number. Implementing HASM in the GPUs device enables modeling large-scale and high-resolution surfaces in a reasonable time period and implies the potential benefits from the use of GPUs as massive, parallel co-processors for arithmetic-intensive data-processing applications.

Secure garbage collection: Preventing malicious data harvesting from deallocated Java objects inside the Dalvik VM

We study the problem of data exposure in main memory caused by insecure deallocation, which is still the default in all common memory management schemes. We propose declarative approaches to handle unreasonably long data lifetime at the programming language level, and present several directions on how current platforms can be improved to minimize the lifetime of confidential data. For the particularly difficult case of Java with its automated garbage collection approach, we present a specific implementation of our approach for the Dalvik VM runtime environment. We give the application level programmer of Android more control over memory by making garbage collection predictable, and by providing the ability to explicitly override and free memory. While the performance impact arising from our approach is negligible in most scenarios, we prove its effectiveness by validating that no freed Java objects can be traced in RAM at runtime anymore.

MMap: Fast Billion-Scale Graph Computation on a PC via Memory Mapping.

Graph computation approaches such as GraphChi and TurboGraph recently demonstrated that a single PC can perform efficient computation on billion-node graphs. To achieve high speed and scalability, they often need sophisticated data structures and memory management strategies. We propose a minimalist approach that forgoes such requirements, by leveraging the fundamental memory mapping (MMap) capability found on operating systems. We contribute: (1) a new insight that MMap is a viable technique for creating fast and scalable graph algorithms that surpasses some of the best techniques; (2) the design and implementation of popular graph algorithms for billion-scale graphs with little code, thanks to memory mapping; (3) extensive experiments on real graphs, including the 6.6 billion edge YahooWeb graph, and show that this new approach is significantly faster or comparable to the highly-optimized methods (e.g., 9.5× faster than GraphChi for computing PageRank on 1.47B edge Twitter graph). We believe our work provides a new direction in the design and development of scalable algorithms. Our packaged code is available at http://poloclub.gatech.edu/mmap/.

Design of a Reconfigurable RFID Sensing Tag as a Generic Sensing Platform Toward the Future Internet of Things

This paper introduces a semipassive, reconfigurable UHF RF identification (RFID) sensing tag operating as the generic sensing platform (GSP) and the sensing nodes of the future Internet of Things (IoT). For generic real-time data acquisition, this new platform offers multiple inexpensive, plug-and-play sensing channels for the appended physical sensors. This new tag can be dynamically reconfigured to operate as a continuous data transmitting/receiving platform (online mode) or a data logging device (offline mode). In the offline mode, for accommodating and managing the high volume of data acquired by the tag sensors, a novel memory management scheme is designed and implemented. Furthermore, the platform employs an innovative data communication strategy that is compatible with the current electronic product code (EPC) Gen-2 communications protocols to facilitate the sensing data communications and other information exchange between the sensing node and the routing tier of IoT. Finally, the designed tag has been successfully deployed and tested in an experimental IoT setup for its performance evaluation as a GSP.

Partially-supervised learning from facial trajectories for face recognition in video surveillance

Face recognition (FR) is employed in several video surveillance applications to determine if facial regions captured over a network of cameras correspond to a target individuals. To enroll target individuals, it is often costly or unfeasible to capture enough high quality reference facial samples a priori to design representative facial models. Furthermore, changes in capture conditions and physiology contribute to a growing divergence between these models and faces captured during operations. Adaptive biometrics seek to maintain a high level of performance by updating facial models over time using operational data. Adaptive multiple classifier systems (MCSs) have been successfully applied to video-to-video FR, where the face of each target individual is modeled using an ensemble of 2-class classifiers (trained using target vs. non-target samples). In this paper, a new adaptive MCS is proposed for partially-supervised learning of facial models over time based on facial trajectories. During operations, information from a face tracker and individual-specific ensembles is integrated for robust spatio-temporal recognition and for self-update of facial models. The tracker defines a facial trajectory for each individual that appears in a video, which leads to the recognition of a target individual if the positive predictions accumulated along a trajectory surpass a detection threshold for an ensemble. When the number of positive ensemble predictions surpasses a higher update threshold, then all target face samples from the trajectory are combined with non-target samples (selected from the cohort and universal models) to update the corresponding facial model. A learn-and-combine strategy is employed to avoid knowledge corruption during self-update of ensembles. In addition, a memory management strategy based on Kullback–Leibler divergence is proposed to rank and select the most relevant target and non-target reference samples to be stored in memory as the ensembles evolves. For proof-of-concept, a particular realization of the proposed system was validated with videos from Face in Action dataset. Initially, trajectories captured from enrollment videos are used for supervised learning of ensembles, and then videos from various operational sessions are presented to the system for FR and self-update with high-confidence trajectories. At a transaction level, the proposed approach outperforms baseline systems that do not adapt to new trajectories, and provides comparable performance to ideal systems that adapt to all relevant target trajectories, through supervised learning. Subject-level analysis reveals the existence of individuals for which self-updating ensembles with unlabeled facial trajectories provides a considerable benefit. Trajectory-level analysis indicates that the proposed system allows for robust spatio-temporal video-to-video FR, and may therefore enhance security and situation analysis in video surveillance.

GREEN ROUTINGSTRATEGY FOR DYNAMICALLY ARRANGED HOMOGENEOUS WSN- MSCT2

Wireless networks play a crucial role in the communication systems nowadays. Wireless networks are being increasingly used in the communication among devices of the most varied types and sizes. User mobility, affordability, flexibility and ease of use are few of many reasons for making them very appealing to new applications and more users everyday. A Wireless Sensor Network (WSN) is composed of sensor nodes spread over the field to sense the data. The sensed data must be gathered &amp; transmitted to Base Station (BS) for end user queries. The used sensor nodes being in- expensive having low computation power &amp; limited energy so are not as much reliable as their expensive macro sensor counter parts but their size and cost enable hundred to thousand of micro sensors to achieve high quality fault tolerant system. In an environment where in each round all sensor nodes have to send data to base station; it is required to effectively utilize energy of sensor nodes so as to increase the life- time of the system. The use of data aggregation &amp; fusion as proposed in LEACH increases system lifetime by a factor of 8 as compared to conventional routing protocols. In this work, our main focus is the static sensors are randomly selected and the base stations have their information all a priori. Basically, the sensors are in direct communication range of each other and can transmit to and receive from the base station. The nodes periodically sense the environment and have always data to send in each round of communication. The nodes fuse/ aggregate the data they receive from the others with their own data, and produce only one packet regardless of how many packets they receive. The problem is to find a routing scheme or an efficient protocol to deliver data packets collected from sensor nodes to the base station. It maximizes the lifetime of the sensor network under the system model given above. However, the definition of quality of service of the sensor network provides is not specified. Secondly, where the nodes are densely deployed, the quality of the system is affected as soon as a significant amount of nodes die, since adjacent nodes record identical or related data. In this case, the lifetime of the network is the time elapsed until half of the nodes or some specified portion of the nodes die. In general terms, the time in rounds where the last node depletes all of its energy defines the lifetime of the overall sensor network. Taking these different possible requirements under consideration, our work provides a proper timing of all deaths for all algorithms in detail as well as chooses the shortest possible path for communication with better memory management scheme and leaves the decision which one to choose to system designers.

Memory Management for Big Data Mining – Cache Hit Rate Estimation of LessFU

Abstract We have developed a network monitor which can find IP packets sent by Internet Virus from Internet backbone traffic. A data mining engine which can handle 10 M transactions per second is the main component of the monitor. Although the data mining engine have to analyze over 200G byte data in theory, a memory management strategy named LessFU removes non-essential data to realize efficient processing. Our past experiments which use real Internet traffic shows the advantage of our approach. However, there exits no method to evaluate the cache hit rate of LessFU. Since the cache hit rate results in serious consequences on the data mining results, this paper proposes a method to estimate the cache hit rate of LessFU. The experimental results which show the advantage of the proposed method are also reported in this paper.

Optimization of Face Recognition Algorithms for Smartphone Environment

The face recognition algorithm has been investigated as a robust solution for biometric authentication. It is used in a wide range of applications such as surveillance, access control, airport immigration system and application of user recognition in a smartphone, etc. (The security of face recognition system can be trusted, because they were used unique biometric data) Face recognition system tends to give a higher degree of recognition performance only when image acquisition process was restricted environment. In this paper, we explore face detection and face recognition algorithms for smartphone environment. The basic requirements include appropriate data format and collection of feature data to achieve efficiency of algorithm. Our experiment presents a face detection and recognition algorithm for smartphone environment. The essential part for proposed system includes; (1) integer representation from floating point calculation on desktop computer and smartphone, (2) optimization of memory management scheme and (3) efficient face detection performance on complex background scene by Modified Census Transform.

Cooperating Virtual Memory and Write Buffer Management for Flash-Based Storage Systems

Flash memory is becoming the preferred choice of secondary storage in mobile devices and embedded systems. The performance of Flash memory is dictated by asymmetric speeds of read and write, limited number of erase times, and the absence of in-place updates. To improve the performance of Flash-based storage systems, the write buffer has been provided in Flash memories recently. At the same time, new virtual memory management strategies have been proposed in recent studies that consider the characteristics of Flash memory. Currently, approaches on these two memory layers are considered separately, which fail to explore the full potential of these two layers. In this paper, we propose cooperative management schemes for virtual memory and write buffer to maximize the performance of Flash-memory-based systems. Management on virtual memory is designed to exploit write buffer status via reordering of the write sequences. The proposed write buffer management scheme works seamlessly with the proposed virtual memory management scheme. Experimental results show that significant improvement in I/O performance and reduction of the number of erase and write operations can be achieved compared to the state-of-art approaches.