Memory Management Mechanism Research Articles

Hetero-DB: Next Generation High-Performance Database Systems by Best Utilizing Heterogeneous Computing and Storage Resources

With recent advancement on hardware technologies, new general-purpose high-performance devices have been widely adopted, such as the graphics processing unit (GPU) and solid state drive (SSD). GPU may offer an order of higher throughput for applications with massive data parallelism, compared with the multicore CPU. Moreover, new storage device SSD is also capable of offering a much higher I/O throughput and lower latency than a traditional hard disk device (HDD). These new hardware devices can significantly boost the performance of many applications; thus the database community has been actively engaging in adopting them into database systems. However, the performance benefit cannot be easily reaped if the new hardwares are improperly used. In this paper, we propose Hetero-DB, a high-performance database system by exploiting both the characteristics of the database system and the special properties of the new hardware devices in system’s design and implementation. Hetero-DB develops a GPU-aware query execution engine with GPU device memory management and query scheduling mechanism to support concurrent query execution. Furthermore, with the SSD-HDD hybrid storage system, we redesign the storage engine by organizing HDD and SSD into a two-level caching hierarchy in Hetero-DB. To best utilize the hybrid hardware devices, the semantic information that is critical for storage I/O is identified and passed to the storage manager, which has a great potential to improve the efficiency and performance. Hetero-DB aims to maximize the performance benefits of GPU and SSD, and demonstrates the effectiveness for designing next generation database systems.

Smart Containers and Skeleton Programming for GPU-Based Systems

In this paper, we discuss the role, design and implementation of smart containers in the SkePU skeleton library for GPU-based systems. These containers provide an interface similar to C++ STL containers but internally perform runtime optimization of data transfers and runtime memory management for their operand data on the different memory units. We discuss how these containers can help in achieving asynchronous execution for skeleton calls while providing implicit synchronization capabilities in a data consistent manner. Furthermore, we discuss the limitations of the original, already optimizing memory management mechanism implemented in SkePU containers, and propose and implement a new mechanism that provides stronger data consistency and improves performance by reducing communication and memory allocations. With several applications, we show that our new mechanism can achieve significantly (up to 33.4 times) better performance than the initial mechanism for page-locked memory on a multi-GPU based system.

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In this work, an approach to generate test programs for functional verification of memory management units of microprocessors is proposed. The approach is based on formal specification of memory access instructions, namely load and store instructions, and memory devices such as cache units and address translation buffers. The use of formal specifications helps automate development of test program generators and makes verification systematic due to clear definition of testing goals. In the suggested approach, test programs are constructed by using combinatorial techniques, which means that stimuli - sequences of loads and stores - are created by enumerating all feasible combinations of instructions, situations (instruction execution paths) and dependencies (sets of conflicts between instructions). It is of importance that test situations and dependencies are automatically extracted from specifications. The approach has been used in a number of industrial projects and allowed to discover critical bugs in memory management mechanisms.

A methodology to automatically optimize dynamic memory managers applying grammatical evolution

Modern consumer devices must execute multimedia applications that exhibit high resource utilization. In order to efficiently execute these applications, the dynamic memory subsystem needs to be optimized. This complex task can be tackled in two complementary ways: optimizing the application source code or designing custom dynamic memory management mechanisms. Currently, the first approach has been well established, and several automatic methodologies have been proposed. Regarding the second approach, software engineers often write custom dynamic memory managers from scratch, which is a difficult and error-prone work. This paper presents a novel way to automatically generate custom dynamic memory managers optimizing both performance and memory usage of the target application. The design space is pruned using grammatical evolution converging to the best dynamic memory manager implementation for the target application. Our methodology achieves important improvements (62.55% and 30.62% better on average in performance and memory usage, respectively) when its results are compared to five different general-purpose dynamic memory managers.

Session details: Memory management mechanisms

Session details: Memory management mechanisms

Fast intelligent watermarking of heterogeneous image streams through mixture modeling of PSO populations

In intelligent watermarking (IW), evolutionary computing (EC) is employed in order to automatically set the embedding parameters of digital watermarking systems for each image. However, the computational complexity of EC techniques makes IW unfeasible for large scale applications involving heterogeneous images. In this paper, we propose a dynamic particle swarm optimization (DPSO) technique which relies on a memory of Gaussian mixture models (GMMs) of solutions in the optimization space. This technique is employed in the optimization of embedding parameters of a multi-level (robust/fragile) bi-tonal watermarking system in high data rate applications. A compact density representation of previously-found DPSO solutions is created through GMM in the optimization space, and stored in memory. Solutions are re-sampled from this memory, re-evaluated for new images and have their distribution of fitness values compared with that stored in the memory. When the distributions are similar, memory solutions are employed in a straightforward manner, avoiding costly re-optimization operations. A specialized memory management mechanism allows to maintain and adapt GMM distributions over time, as the image stream changes. This memory of GMMs allows an accurate representation of the topology of a stream of optimization problems. Consequently, new cases of optimization can be matched against previous cases more precisely (when compared with a memory of static solutions), leading to considerable decrease in computational burden. Simulation results on heterogeneous streams of images indicate that compared to full re-optimization for each document image, the proposed approach allows to decrease the computational requirement linked to EC by up to 97.7% with little impact on the accuracy for detecting watermarks. Comparable results were obtained for homogeneous streams of document images.

A trusted environment construction method for security-sensitive software

This paper presents a trusted-environment construction method based on the underlying hardware. This method aims at protecting the security-sensitive software in the aspects of software loading, running, and storing in the general operating system. It extends the trust chain of the traditional trusted computing technology to reach the target software, ensuring trusted loading. The extended memory management mechanism effectively prevents memory dumping and memory tampering for the high-sensitivity data. The file monitoring mechanism protects files from vicious operation made by attackers. Flexible-expanded storage environment provides the target software with static storing protection. Experimental system verifies that the method is suitable for general operating system and can effectively protect security-sensitive software with low overhead.

전력공급이 안정된 장치들을 위한 자바 COS에 관한 연구

기존의 스마트카드에 자바 플랫폼이 탑재된 자바 카드는 리더기를 통하여 전원이 잠시 공급될 때 어플리케이션을 적재하고 실행된다. 하지만 오늘날 여러 종류의 자바 카드는 USIM 카드와 같이 이동단말기 상에 내장되어 단말기로부터 항상 전원을 공급받을 수 있다. 이와 같이 항시 전원이 공급이 될 경우, 자바 카드들의 성능개선이 가능하다. 본 논문에서는 항시 전원 공급을 받는 자바 카드의 메모리 관리 메카니즘을 보다 효과적으로 운용함으로써 성능 향상된 애플릿 설치 및 실행이 가능한 자바카드 운영체제 시스템을 제안한다. Legacy Java card which adapts a Java platform loads and executes an application when electronics power is provided. However, recently the most Java cards are embedded into a mobile terminal as USIM cards, therefore the power is continually provided for the smart cards. In this case, operation of a Java card system needs to consider its operating system to be advanced in memory management, object management and transaction mechanism. In this paper, we present a high performance Java Card system which is able to have efficient installation, loading and execution of application by applying a new memory management of the smart card that has safe power system.

Automatic Memory Management for Embedded Real-Time Java Processor Jpor-32

Abstract Currently, Java has been gradually applied in embedded real-time areas like robotics, control system, etc. owning to its advantages like robustness, security, etc. In order to improve the performance of Java's execution engine for embedded real-time applications, JPOR-32, an embedded real-time Java processor, is designed. Based on it, this paper presents the automatic memory management (AMM) mechanism for embedded real-time Java processor. JPOR-32 provides architectural support as well as instruction level support for AMM. Its preprocessing mechanism reduces the complexity of the implementation of AMM, enhances the run-time efficiency, and promotes predictability of the worst-case execution time. The system design of JPOR-32 makes AMM of class azea avoided, and the optimized design of instruction set provides effective support for space checking and garbage collection scheduling. This paper also proposes an object reference format which provides supports for objects tracing, heap scanning, synchr...

Dynamic memory mapping delivers additional flexibility to virtual resource management

The Department of Computer Science and Technology, Peking University, Beijing, China, has shown that a novel Dynamic Memory Mapping (DMM) model brings about additional flexibility to virtual resource management, leading to the feature-adjustable design of a virtual machine monitor (VMM). The study is reported in Issue 53 (June, 2010) of SCIENCE CHINA Information Sciences because of its significant research value. Memory is one of the most frequently accessed components in virtual machine (VM) systems. Because a VM’s memory requirement varies according to the running applications, disregarding the dynamic changes can result in suboptimal use of memory resources, which negatively affects the VM’s performance. However, because the infrastructures of current technologies are usually independent of each other, they exhibit poor extensibility, integrity, and maintainability. To improve the flexibility and extensibility of the VMM, we need to implement a dynamic memory management mechanism in the VMM, while preserving the high efficiency of memory accesses from virtual machines. To resolve these problems, this work proposes a DMM model [1]. The DMM model is a low-level memory management mechanism, which allows dynamic change of the mapping between the pseudo-physical memory as seen from VMs and the machine memory, while the virtual machine is running. On one hand, DMM is independent of, yet compatible with, various virtualization architectures, while on the other, it presents a uniform upward interface for supporting high-level memory management policies. As a result, the DMM layer incorporates high-level policies and low-level implementations by making both of them adjustable. In this work, Prof. Wang, Prof. Luo and their group present the principle of the DMM model, and explain the procedures of various memory management policies under this model, such as demand paging, virtual memory and memory sharing. They also implement the DMM model in KVM, an open source VMM. They first designed a memory pool, a set of machine pages provided by the VMM to a particular virtual machine whose size could be expanded or shrunk while operating. To make the model work in a real system, they manipulated a page-level protection mechanism to propagate memory-mapping updates to the shadow page tables, which is the only way for a VM to access its virtualized memory. They also utilized reverse mapping, a data structure that maps a machine page back to all the shadow page table entries that have mapped it, to facilitate the mapping propagation. The DMM model has several advantages over the current memory management mechanism in VMMs. The first is platform independency—the model is defined abstractly, thus is independent of implementations and computer architectures. The second is flexibility—the DMM model provides a uniform interface for integrating advanced memory management policies. Through the general mechanism, they can work together without conflict. Last but not least, the modular and layered design of the DMM reduces the complexity of a VMM’s code base, and therefore improves the security and dependability of the system. A journal reviewer noted:“This paper addresses the inefficiency in the design of current virtual machine monitors. Their approach is novel and systematic, and incurs only minor overheads. The result is of academic significance and practical value”. Another reviewer said, “It enriches and expands the capacity and capability of virtualization. It offers us new methods to deploy and manage large numbers of virtual machines”. A series of papers about virtual machine system optimization written by Prof. Wang, Prof. Luo and their group have been published in SCIENCE CHINA Information Sciences [2], IEEE Cluster [3], ACM SIGOPS Operating System Review [4]. The authors are affiliated to the Institute of Network Computing and Information Systems (NCIS, http://ncis.pku.edu.cn) at Peking University. This institute, led by Prof. LI XiaoMing, conducts research mainly in the fields of high productivity computing, search engine and Web mining, distributed systems, internet and mobile computing, and database technology.

Dynamic memory paravirtualization transparent to guest OS

This paper introduces dynamic paravirtualization, which imitates paravirtualization and aims at reducing VM exits of full virtualization with hardware support. In dynamic paravirtualization, VMM (virtual machine monitor) dynamically monitors and replaces the hot instructions, which cause most VM exits. It is transparent to the guest OS such that the legacy OSes can benefit from this optimization. Our study focuses on reducing the overhead of memory virtualization—dynamic memory paravirtualization (DMP). We implant a new memory management mechanism in VMM such that all user-mode page faults can be handled by the guest OS directly without VM exits. We implement a prototype of dynamic memory paravirtulization based on a version of KVM using Intel VT. Our experimental results show that our technique essentially eliminates the overhead of VM exits caused by page faults. Dynamic memory paravirtualization can achieve the effectiveness of paravirtualization without changing the source code of guest OS.

SCoPE: Towards a Systolic Array for SVM Object Detection

This paper presents SCoPE (systolic chain of processing elements), a first step towards the realization of a generic systolic array for support vector machine (SVM) object classification in embedded image and video applications. SCoPE provides efficient memory management, reduced complexity, and efficient data transfer mechanisms. The proposed architecture is generic and scalable, as the size of the chain, and the kernel module can be changed in a plug and play approach without affecting the overall system architecture. These advantages provide versatility, scalability and reduced complexity that make it ideal for embedded applications. Furthermore, the SCoPE architecture is intended to be used as a building block towards larger systolic systems for multi-input or multi-class classification. Simulation results indicate real-time performance, achieving face detection at ~33 frames per second on an FPGA prototype.

Declarative aspects of memory management in the concurrent collections parallel programming model (abstract only)

Concurrent Collections (CnC) is a declarative parallel language that allows the application developer to express their parallel application as a collection of high-level computations called steps that communicate via single-assignment data structures called items. A CnC program is specified in two levels. At the bottom level, an existing imperative language implements the computations within the individual computation steps. At the top level, CnC describes the relationships (ordering constraints) among the steps. The memory management mechanism of the existing imperative language manages data whose lifetime is within a computation step. A key limitation in the use of CnC for long-running programs is the lack of memory management and garbage collection for data items with lifetimes that are longer than a single computation step. Although the goal here is the same as that of classical garbage collection, the nature of problem and therefore nature of the solution is distinct. The focus of this paper is the memory management problem for these data items in CnC. We introduce a new declarative slicing annotation for CnC that can be transformed into a reference counting procedure for memory management. Preliminary experimental results obtained from a Cholesky example show that our memory management approach can result in space reductions for CnC data items of up to 28x relative to the baseline case of standard CnC without memory management.

A Turbo Coding System for High Speed Communications

This paper presents a new turbo coding scheme for high data rate applications. It uses a special interleaver structure that is naturally suited for parallel processing and a multiple-round early stopping test involving both sign check and a CRC code. A memory (storage) management mechanism is included as a critical part of the decoder. The proposed coding scheme offers new design options and tradeoffs that are not available to conventional convolutional turbo codes (CTCs). In particular, it becomes possible for the decoder to employ an efficient inter-block collaborative decoding algorithm, passing the information obtained from stopping test proved blocks to other unproved blocks. It also becomes important to have a proper decoding schedule. The combined effect is improved performance and reduction in the average decoding latency. We show that the memory manager has a modular-like effect in that additional memory units render enhanced performance due not only to less forced early stopping but to possible increases of the interleaving depth. It also provides additional design tradeoff amongst performance, speed and required memory size. Depending on the decoding schedule, the degree of parallelism and other decoding resources available, the proposed scheme admits a variety of decoder architectures that meet a large range of speed and performance demands.

The Cognition of Deception: The Role of Executive Processes in Producing Lies

The cognitive processes used in deception have been largely overlooked in the literature on deception. The author's position in this review is that effortful executive processes (inhibition, working memory, and other mental management mechanisms) are central cognitive components for lie production. The author provides evidence from 3 bodies of literature: studies on lie detection, developmental research on cognition related to children's deception, and imaging research describing neural correlates of deception. In addition, the author reviews the available theories that implicate executive functions as core processes in deception. The author also discusses implications of this research as they relate to future research and applications on the psychology of deception.

GIST: an interactive, GPU-based level set segmentation tool for 3D medical images

While level sets have demonstrated a great potential for 3D medical image segmentation, their usefulness has been limited by two problems. First, 3D level sets are relatively slow to compute. Second, their formulation usually entails several free parameters which can be very difficult to correctly tune for specific applications. The second problem is compounded by the first. This paper describes a new tool for 3D segmentation that addresses these problems by computing level-set surface models at interactive rates. This tool employs two important, novel technologies. First is the mapping of a 3D level-set solver onto a commodity graphics card (GPU). This mapping relies on a novel mechanism for GPU memory management. The interactive rates level-set PDE solver give the user immediate feedback on the parameter settings, and thus users can tune free parameters and control the shape of the model in real time. The second technology is the use of intensity-based speed functions, which allow a user to quickly and intuitively specify the behavior of the deformable model. We have found that the combination of these interactive tools enables users to produce good, reliable segmentations. To support this observation, this paper presents qualitative results from several different datasets as well as a quantitative evaluation from a study of brain tumor segmentations.

CAS-DSM: A Compiler Assisted Software Distributed Shared Memory

Traditional software Distributed Shared Memory (DSM) systems rely on the virtual memory management mechanisms to detect accesses to shared memory locations and maintain their consistency. The resulting involvement of the OS (kernel) and the associated overhead which is significant, can be avoided by careful compile time analysis and code instrumentation. In this paper, we propose such a Compiler Assisted Software support approach (CAS-DSM). In the CAS-DSM implementation, the involvement of the OS kernel is avoided by instrumenting the application code at the source level. The overhead caused by the execution of the instrumented code is reduced through several aggressive compile time optimizations. Finally, we also address the issue of reducing certain overheads in polling-based implementation of receiving asynchronous messages. We used SUIF, a public domain compiler tool, to implement compile time analysis, instrumentation and optimizations. We modified CVM, a publicly available software DSM to support the instrumentation inserted by the compiler. Detailed performance evaluation of CAS-DSM is reported using a set of Splash/Splash2 parallel application benchmarks on a distributed memory IBM SP-2 machine. CAS-DSM achieved moderate to good performance improvements for most of the applications compared to the original CVM implementation. Reducing the overheads in polling-based implementation improves the performance of CAS-DSM significantly resulting in an overall improvement of 12-52% over the original CVM implementation.

A CASE FOR SINGLE SYSTEM IMAGE CLUSTER OPERATING SYSTEMS: THE KERRIGHED APPROACH

In this paper, we present fundamental mechanisms for global process and memory management in an efficient single system image cluster operating system designed to execute workloads composed of high performance sequential and parallel applications. Their implementation in Kerrighed, our proposed distributed operating system, is composed of a set of Linux modules and a patch of less than 200 lines of code to the Linux kernel. Kerrighed is a unique single system image cluster operating system providing the standard Unix interface as well as distributed OS mechanisms such as load balancing on all cluster nodes. Our support for standard Unix interface includes support for multi-threaded applications and a checkpointing facility for both sequential and shared memory parallel applications. We present an experimental evaluation of the Kerrighed system and demonstrate the feasibility of the single system image approach at the kernel level.

Operating system support for multimedia systems

Distributed multimedia applications will be an important part of tomorrow's application mix and require appropriate operating system (OS) support. Neither hard real-time solutions nor best-effort solutions are directly well suited for this support. One reason is the co-existence of real-time and best effort requirements in future systems. Another reason is that the requirements of multimedia applications are not easily predictable, like variable bit rate coded video data and user interactivity. In this article, we present a survey of new developments in OS support for (distributed) multimedia systems, which include: (1) development of new CPU and disk scheduling mechanisms that combine real-time and best effort in integrated solutions; (2) provision of mechanisms to dynamically adapt resource reservations to current needs; (3) establishment of new system abstractions for resource ownership to account more accurate resource consumption; (4) development of new file system structures; (5) introduction of memory management mechanisms that utilize knowledge about application behavior; (6) reduction of major performance bottlenecks, like copy operations in I/O subsystems; and (7) user-level control of resources including communication.

A fast asynchronous GVT algorithm for shared memory multiprocessor architectures

The computation of Global Virtual Time is of fundamental importance in Time Warp based Parallel Discrete Event Simulation Systems. Shared memory multiprocessor architectures can support interprocess communication with much smaller overheads than distributed memory systems. This paper presents a new, completely asynchronous, Gvt algorithm which provides very fast and accurate Gvt estimation with significantly lower overhead than previous approaches. The algorithm presented is able to support more efficient memory management, termination, and other global control mechanisms. The Gvt algorithm described enables any Time Warp entity to compute Gvt at any time without slowing down other entities, in particular, those executing on the critical path. Experimental results are presented for a shared memory Time Warp system that employs a two tiered distributed memory management scheme. The proof of the correctness and the accuracy of the algorithm are also presented. Finally, some suggestions on possible further optimization of the implementation are given.