Field Programmable Gate Array Memory Research Articles

An FPGA-Accelerated Parallel Digital Beamforming Core for Medical Ultrasound Sector Imaging.

Plane-wave transmission followed by parallel receive beamforming is popular among high frame rate (HFR) ultrasound (US) imaging methods. However, due to technological limitations, HFR imaging is not widely successful in clinical US. The proposed work aims to design a field-programmable gate array (FPGA)-accelerated parallel beamforming core for medical US sector imaging systems. This architecture supports up to 128 channels and forms 28 beams per plane wave transmission in parallel. A block random access memories (BRAMs)-based, 28-read one-write (28R1W) multi-ported delay line architecture is actualized to realize the delay line. In addition, to optimize the FPGA memory, the required beam focusing delays are stored in an external static random access memory (SRAM) and are loaded into the internal delay line registers by a cycle stealing direct memory access (DMA). The FPGA prototype validation and verification are performed on the custom-designed Xilinx-Kintex-7 XC7C410T FPGA-based US imaging platform. The results showed that for a field of view (FOV) of 90° with 0.5° resolution, 640×480 imaging size, a ft/s of 714 is achieved. The performance of the proposed parallel beamformer architecture is compared with existing development works and concluded that the architecture is superior due to its occupancy of FPGA hardware resources and the processing speed.

Low-Cost Strategy to Detect Faults Affecting Scrubbers in SRAM-Based FPGAs

SRAM-based Field Programmable Gate Arrays (FPGAs) are vulnerable to SEUs. For applications demanding high reliability this problem is often solved by integrating in the system a scrubber, a circuit that periodically scans the FPGA configuration memory and reconfigures it if an error is detected. Since the scrubber is usually implemented in the same FPGA device, it is also vulnerable to SEUs, thus the scrubber reliability is increased by adopting standard fault tolerance techniques. These solutions guarantee the scrubber reliability, but generally require a large area overhead.In this paper, we present a novel low-cost strategy capable to detect faults in the FPGA configuration memory implementing the scrubber. The proposed technique is based on time redundancy, forcing the scrubber output to produce an error indication for each word read from the FPGA memory, in order to detect the faults affecting the portion of FPGA memory implementing the scrubber. The implementation of our proposed strategy presents a negligible impact in terms of area overhead (4.17%) and a limited increase in power consumption (22.9%) over the original (unprotected) scrubber. As for the impact on system performance introduced by our strategy, it is of approximately the 38.2% over the unprotected scrubber, but it can be significantly lowered by reducing the frequency at which the scrubber is applied to test the FPGA.

Array-Specific Dataflow Caches for High-Level Synthesis of Memory-Intensive Algorithms on FPGAs

Designs implemented on field-programmable gate arrays (FPGAs) via high-level synthesis (HLS) suffer from off-chip memory latency and bandwidth bottlenecks. FPGAs can access both large but slow off-chip memories (DRAM), and fast but small on-chip memories (block RAMs and registers). HLS tools allow exploiting the memory hierarchy in a scratchpad-like fashion, requring a significant manual effort. We propose an automation of the FPGA memory management in Xilinx <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">Vitis HLS</i> through a fully-configurable C++ source-level cache. Each DRAM-mapped array can be associated with a private level 2 (L2) cache with one or more ports, and each port can optionally provide a level 1 cache. The L2 cache runs in a separate dataflow task with respect to the application accessing it. This solution isolates off-chip memory accesses and data buffering into dedicated dataflow tasks, resembling the load, compute, store design paradigm, but without the drawback of manual algorithm refactoring. Experimental results collected from an FPGA board show that our cache speeds up the execution of a variety of benchmarks by up to 60 times compared to the out-of-the-box solution provided by HLS, requiring very limited optimization effort. Our caches are not meant to compete with manually optimized implementations quality of results (QoR), but rather to significantly save design effort, in exchange for some QoR, to make the HLS flow a bit more software-like, allowing the designer to focus on algorithmic optimizations, rather than on explicit memory management. Moreover, caching could be the only feasible memory optimization for algorithms with data-dependent or irregular memory access patterns, but with good data locality.

An Efficient Hardware Design for a Low-Latency Traffic Flow Prediction System Using an Online Neural Network

Neural networks are computing systems inspired by the biological neural networks in human brains. They are trained in a batch learning mode; hence, the whole training data should be ready before the training task. However, this is not applicable for many real-time applications where data arrive sequentially such as online topic-detection in social communities, traffic flow prediction, etc. In this paper, an efficient hardware implementation of a low-latency online neural network system is proposed for a traffic flow prediction application. The proposed model is implemented with different Machine Learning (ML) algorithms to predict the traffic flow with high accuracy where the Hedge Backpropagation (HBP) model achieves the least mean absolute error (MAE) of 0.001. The proposed system is implemented using floating point and fixed point arithmetics on Field Programmable Gate Array (FPGA) part of the ZedBoard. The implementation is provided using BRAM architecture and distributed memory in FPGA in order to achieve the best trade-off between latency, the consumption of area, and power. Using the fixed point approach, the prediction times using the distributed memory and BRAM architectures are 150 ns and 420 ns, respectively. The area delay product (ADP) of the proposed system is reduced by 17 × compared with the hardware implementation of the latest proposed system in the literature. The execution time of the proposed hardware system is improved by 200 × compared with the software implemented on a dual core Intel i7-7500U CPU at 2.9 GHz. Consequently, the proposed hardware model is faster than the software model and more suitable for time-critical online machine learning models.

RETRACTED: Optimized allocation of FPGA memory for image processing

Memory is the most restricting component for use in the Field Programmable Gate Array (FPGA) for elevated level picture preparation, which requires total casing (s) to be put away in the general area. Since the FPGA on-chip memory work is restricted, utilizing these assets adequately is essential to meet the exhibition, size, and intensity utilization limitations. This article aims to diminish asset utilization and force utilization, explore the picture preparing significant level prompting energy preservation, and understand the portion of on-chip memory assets included the FPGA altogether. The proposed memory engineering strategy, notwithstanding equipment depiction language, the plan of the significant levels of combination, is generally memory inhabitance, you can lessen the force utilization. On-chip formal force model dependent on the memory design choices will demonstrate whether the dividing calculation is higher than in how the regular procedure. Contrasted with business FPGA blend and elevated level union instruments, our outcomes, the proposed calculation shows that can bring about higher effectiveness, the number and size of edges that can be obliged in the uplink outline increment, about buffer% diminished unique force utilization. In the utilization of optical stream and mean movement following speaking to modern calculations, division calculation, as appeared by our exploratory information, without influencing the exhibition, it can lessen the separate all-out force.

Accelerating Stochastic Gradient Descent Based Matrix Factorization on FPGA

Matrix Factorization (MF) based on Stochastic Gradient Descent (SGD) is a powerful machine learning technique to derive hidden features of objects from observations. In this article, we design a highly parallel architecture based on Field-Programmable Gate Array (FPGA) to accelerate the training process of the SGD-based MF algorithm. We identify the challenges for the acceleration and propose novel algorithmic optimizations to overcome them. By transforming the SGD-based MF algorithm into a bipartite graph processing problem, we propose a 3-level hierarchical partitioning scheme that enables conflict-minimizing scheduling and processing of edges to achieve significant speedup. First, we develop a fast heuristic graph partitioning approach to partition the bipartite graph into induced subgraphs; this enables to efficiently use the on-chip memory resources of FPGA for data reuse and completely hide the data communication between FPGA and external memory. Second, we partition all the edges of each subgraph into non-overlapping matchings to extract the maximum parallelism. Third, we propose a batching algorithm to schedule the execution of the edges inside each matching to reduce the memory access conflicts to the on-chip RAMs of FPGA. Compared with non-optimized FPGA-based baseline designs, the proposed optimizations result in up to 60× data dependency reduction, 4.2× bank conflict reduction, and 15.4× speedup. We evaluate the performance of our design using a state-of-the-art FPGA device. Experimental results show that our FPGA accelerator sustains a high computing throughput of up to 217 billion floating-point operations per second (GFLOPS) for training very large real-life sparse matrices. Compared with highly-optimized GPU-based accelerators, our FPGA accelerator achieves up to 12.7× speedup. Based on our optimization methodology, we also implement a software-based design on a multi-core platform, which demonstrates 1.3× speedup compared with the state-of-the-art multi-core implementation.

DSP-Efficient Hardware Acceleration of Convolutional Neural Network Inference on FPGAs

Field-programmable gate array (FPGA)-based accelerators for convolutional neural network (CNN) inference have received significant attention in recent years. The reported designs tend to adopt a similar underlying approach based on multiplier-accumulator (MAC) arrays, which yields strong demand for the available on-chip DSP blocks, while leaving FPGA logic and memory resources underutilized. The practical outcome is that the computational roof of the accelerator is bound by the number of DSP blocks offered by the target FPGA. In addition, integrating the CNN accelerator with other functional units that may also need DSP blocks would degrade the inference performance. Leveraging the robustness of inference accuracy to limited arithmetic precision, we propose a transformation to the convolution computation, which leads to transformation of the accelerator design space and relaxes the pressure on the required DSP resources. Through analytical and empirical evaluations, we demonstrate that our approach enables us to strike a favorable balance between utilization of the FPGA on-chip memory, logic, and DSP resources, due to which, our accelerator considerably outperforms state of the art. We report the effectiveness of our approach on a variety of FPGA devices, including Cyclone-V, Stratix-V, and Arria-10, which are used in large number of applications, ranging from embedded settings to high performance computing. Our proposed technique yields 1.5x throughput improvement and 4x DSP resource reduction compared to the best frequency domain convolution-based accelerator, and 2.5x boost in raw arithmetic performance and 8.4x saving in DSPs compared to a state-of-the-art sparse convolution-based accelerator.

Proton- and Neutron-Induced Single-Event Upsets in FPGAs for the PANDA Experiment

Single-event upsets (SEUs) affecting the configuration memory of a 28-nm field-programmable gate array (FPGA) have been studied through experiments and Monte Carlo modeling. This FPGA will be used in the front-end electronics of the electromagnetic calorimeter in PANDA (Antiproton Annihilation at Darmstadt), an upcoming hadron-physics experiment. Results from proton and neutron irradiations of the FPGA are presented and shown to be in agreement with previous experimental results. To estimate the mean time between SEUs during operation of PANDA, a Geant4-based Monte Carlo model of the phenomenon has been used. This model describes the energy deposition by particles in a silicon volume, the subsequent drift and diffusion of charges in the FPGA memory cell, and the eventual collection of charges in the sensitive regions of the cell. The values of the two free parameters of the model, the sensitive volume side $d = 87$ nm and the critical charge $Q_{\text {crit}} = 0.23$ fC, were determined by fitting the model to the experimental data. The results of the model agree well with both the proton and neutron data and are also shown to correctly predict the cross sections for upsets induced by other particles. The model-predicted energy dependence of the cross section for neutron-induced upsets has been used to estimate the rate of SEUs during initial operation of PANDA. At a luminosity of $1\cdot 10^{31}$ cm $^{-2}\,\,\text{s}^{-1}$ , the predicted mean time between upsets (MTBU) is between 120 and 170 h per FPGA, depending on the beam momentum.

Combining Multiple Optimized FPGA-based Pulsar Search Modules Using OpenCL

Field-Programmable Gate Arrays (FPGAs) are widely used in the central signal processing design of the Square Kilometer Array (SKA) as hardware accelerators. The frequency domain acceleration search (FDAS) module is an important part of the SKA1-MID pulsar search engine. To develop for a yet to be finalized hardware, for cross-discipline interoperability and to achieve fast prototyping, OpenCL as a high-level FPGA synthesis approaches employed to create the sub-modules of FDAS. The FT convolution and the harmonic-summing plus some other minor sub-modules are elements in the FDAS module that have been well-optimized separately before. In this paper, we explore the design space of combining well-optimized designs, dealing with the ensuing need to trade-off and compromise. Pipeline computing is employed to handle multiple input arrays at high speed. The hardware target is to employ multiple high-end FPGAs to process the combined FDAS module. The results show interesting consequences, where the best individual solutions are not necessarily the best solutions for the speed of a pipeline where FPGA resources and memory bandwidth need to be shared. By proposing multiple buffering techniques to the pipeline, the combined FDAS module can achieve up to 2[Formula: see text] speedup over implementations without pipeline computing. We perform an extensive experimental evaluation on multiple high-end FPGA cards hosted in a workstation and compare to a technology comparable mid-range GPU.

Hardware implementation of digital image skeletonization algorithm using FPGA for computer vision applications

Nowadays embedded multimedia devices are designed for computationally intensive applications such as image processing in various multimedia systems. Image processing algorithms should be implemented on hardware platforms for improving the performance. Reconfigurable hardware implementation using Field Programmable Gate Arrays (FPGAs) provides low latency with high performance in real time applications. FPGAs offer the reprogrammability of an application specific solution while retaining the performance advantage. In real time applications as image sizes increase rapidly, only hardware systems must be used with low complex software. In this paper, main perspective of developing and implementing skeletonization algorithm as a part of computer vision, pattern recognition application is focused and presented. A simple algorithm to skeletonize the 2-D image using MATLAB is developed. An architecture and implementation of this skeletonization algorithm for 2-D gray scale images is proposed. For analyzing pixel values 3 × 3 windowing operator is used. The proposed architecture is tested for an image size of 8 × 8, but the approach presented in this paper can be used for images of any size (M × N), if the FPGA memory is sufficiently large. The implementation was carried out on Xilinx Vertex 5 board.

Hi-DMM: High-Performance Dynamic Memory Management in High-Level Synthesis

High-level synthesis (HLS) of field programmable gate array (FPGA)-based accelerators has been proposed in order to simplify accelerator design process with respect to design time and complexity. However, modern HLS tools do not consider dynamic memory allocation constructs in high-level programming languages like C and limit themselves to static memory allocation. This paper proposes a dynamic memory allocation and management scheme, called Hi-DMM, for inclusion in commercial HLS design flows. Hi-DMM performs source-to-source transformation of user C code with dynamic memory constructs into C-source code with the dynamic memory allocator and management scheme developed in this paper. The transformed C-source code is amenable to synthesis by commercial tools like Vivado HLS. Relying on buddy tree-based allocation schemes and efficient hardware implementation of the allocators, Hi-DMM achieves 4x speed-up in both fine-grained and coarse-grained memory allocation compared to previous works. Experimental results obtained by including Hi-DMM with Vivado-HLS show that dynamic memory allocation of FPGA memory resources can be achieved at a much lower latency with minimal resource overhead, paving the way for synthesis of dynamic memory constructs in commercial HLS flows.

SEU mitigation exploratory tests in a ITER related FPGA

Data acquisition hardware of ITER diagnostics if located in the port cells of the tokamak, as an example, will be irradiated with neutrons during the fusion reactor operation. Due to this reason the majority of the hardware containing Field Programmable Gate Arrays (FPGA) will be placed after the ITER bio-shield, such as the cubicles instrumentation room. Nevertheless, it is worth to explore real-time mitigation of soft-errors caused by neutrons radiation in ITER related FPGAs. A Virtex-6 FPGA from Xilinx (XC6VLX365T-1FFG1156C) is used on the ATCA-IO-PROCESSOR board, included in the ITER Catalog of Instrumentation & Control (I & C) products – Fast Controllers. The Virtex-6 is a re-programmable logic device where the configuration is stored in Static RAM (SRAM), the functional data is stored in dedicated Block RAM (BRAM) and the functional state logic in Flip-Flops. Single Event Upsets (SEU) due to the ionizing radiation of neutrons cause soft errors, unintended changes (bit-flips) of the logic values stored in the state elements of the FPGA. Real-time SEU monitoring and soft errors repairing, when possible, were explored in this work. An FPGA built-in Soft Error Mitigation (SEM) controller detects and corrects soft errors in the FPGA Configuration Memory (CM). BRAM based SEU sensors with Error Correction Code (ECC) detect and repair the respective BRAM contents. Real-time mitigation of SEU can increase reliability and availability of data acquisition hardware for nuclear applications. The results of the tests performed using the SEM controller and the SEU sensors are presented for a Virtex-6 FPGA (XC6VLX240T-1FFG1156C) when irradiated with neutrons from the Portuguese Research Reactor (RPI), a 1MW nuclear fission reactor, operated by IST in the neighborhood of Lisbon. Results show that the proposed SEU mitigation technique is able to repair the majority of the detected SEU soft-errors in the FPGA memory.

(FPL 2015) Scavenger

High-level abstractions separate algorithm design from platform implementation, allowing programmers to focus on algorithms while building complex systems. This separation also provides system programmers and compilers an opportunity to optimize platform services on an application-by-application basis. In field-programmable gate arrays (FPGAs), platform-level malleability extends to the memory system: Unlike general-purpose processors, in which memory hardware is fixed at design time, the capacity, associativity, and topology of FPGA memory systems may all be tuned to improve application performance. Since application kernels may only explicitly use few memory resources, substantial memory capacity may be available to the platform for use on behalf of the user program. In this work, we present Scavenger, which utilizes spare resources to construct program-optimized memories, and we also perform an initial exploration of methods for automating the construction of these application-specific memory hierarchies. Although exploiting spare resources can be beneficial, naïvely consuming all memory resources may cause frequency degradation. To relieve timing pressure in large block RAM (BRAM) structures, we provide microarchitectural techniques to trade memory latency for design frequency. We demonstrate, by examining a set of benchmarks, that our scalable cache microarchitecture achieves performance gains of 7% to 74% (with a 26% geometric mean on average) over the baseline cache microarchitecture when scaling the size of first-level caches to the maximum.

EMBIRA: An Accelerator for Model-Based Iterative Reconstruction

Tomographic reconstruction, which involves computing a 3-D volume from its 2-D projections, is an important problem in imaging with wide-ranging applications, including medical scanners, electron microscopy, nondestructive testing, and transportation security. Model-based iterative reconstruction (MBIR) is a popular approach to 3-D reconstruction that has demonstrated the state-of-the-art reconstruction quality on several applications, and has been deployed in commercial healthcare systems. However, software implementations of MBIR on commodity general-purpose processors demonstrate poor performance due to its high compute and data requirements and cache unfriendly data access patterns. In this paper, we develop an efficient MBIR accelerator (EMBIRA) that achieves significant performance and energy improvement over software implementations. EMBIRA utilizes arrays of three types of specialized processing elements that match MBIR’s computation patterns, and is further operated as a two-level nested pipeline to fully exploit the parallelism present in the algorithm. Another important source from which EMBIRA derives its efficiency is by constraining the sequence in which voxels 1 in the 3-D volume are reconstructed. This enables better data reuse within the accelerator, thereby significantly reducing the number of off-chip memory accesses. To demonstrate the benefits of EMBIRA, we implemented a prototype on an Altera DE5 field-programmable gate array (FPGA) platform that includes an Altera Stratix V GX FPGA and DDR3 memory. Our implementation of EMBIRA, operating at 165 MHz, achieved $51.8\times $ ( $5.8\times $ ) improvement in performance, and $355\times $ ( $199\times $ ) improvement in energy, compared with optimized sequential (multithreaded) software implementations on a 48-core 2.3-GHz AMD Opteron-based server. 1 Each location in the 3-D volume represents a voxel. It is analogous to a pixel in a 2-D image.

Optimized FPGA based continuous wavelet transform

A memory efficient field programmable gate array (FPGA) method is described that facilitates the processing of the continuous wavelet transform (CWT) arithmetic operations. The CWT computations were performed in Fourier space and implemented on FPGA following several optimization schemes. First, the adapted wavelet function was stored in a lookup table instead of computing the equation each time. Second, the utilization of FPGA memory was highly optimized by only storing the nonzero values of the wavelet function. This reduces 89% of the memory storage and allows fitting the entire design into the FPGA. Third, the design decreases the number of multiplications and shortens the time to produce the CWT coefficients. The proposed design was tested using EEG data and demonstrated to be suitable for extracting features from the event related potentials. Fourth, wavelet function scales were eliminated which saves further resources. The achieved computation speed allows for real time CWT application.

Power-Efficient RAM Mapping Algorithms for FPGA Embedded Memory Blocks

Contemporary field-programmable gate array (FPGA) design requires a spectrum of available physical resources. As FPGA logic capacity has grown, locally accessed FPGA embedded memory blocks have increased in importance. When targeting FPGAs, application designers often specify high-level memory functions, which exhibit a range of sizes and control structures. These logical memories must be mapped to FPGA embedded memory resources such that physical design objectives are met. In this paper, a set of power-efficient logical-to-physical RAM mapping algorithms is described, which converts user-defined memory specifications to on-chip FPGA memory block resources. These algorithms minimize RAM dynamic power by evaluating a range of possible embedded memory block mappings and selecting the most power-efficient choice. Our automated approach has been validated with both simulation of power dissipation and measurements of power dissipation on FPGA hardware. A comparison of measured power reductions to values determined via simulation confirms the accuracy of our simulation approach. Our power-aware RAM mapping algorithms have been integrated into a commercial FPGA compiler and tested with 34 large FPGA benchmarks. Through experimentation, we show that, on average, embedded memory dynamic power can be reduced by 26% and overall core dynamic power can be reduced by 6% with a minimal loss (1%) in design performance. In addition, it is shown that the availability of multiple embedded memory block sizes in an FPGA reduces embedded memory dynamic power by an additional 9.6% by giving more choices to the computer-aided design algorithms