Memory Cell Application Research Articles

A New Threshold Voltage Model for Short-Channel Junctionless Inverted T-Shaped Gate FETs (JLITFET)

On the basis of the quasi-three-dimensional scaling equation, equivalent number of gates, and minimum bottom-central potential, a novel threshold voltage model for the short-channel junctionless inverted T-shaped gate FETs (JLITFET) is presented. It is shown that the thin thickness of the inverted T-shaped silicon base (ITSB) is superior to the thick one in respect of suppressing SCEs and reducing the threshold voltage roll-off. With the same width of ITSB, the large height of fins is required to resist SCEs and reduce the threshold voltage degradation as the channel length is decreased. In comparison to both junctionless double-gate FET and junctionless FinFET, the JLITFET will suffer the least threshold voltage degradation among the three FETs due to its smallest scaling length. With its computational efficiency, the model can be easily used for the memory cell application for the JLITFET.

Atomic thermal motion effect on efficiency of a high-speed quantum memory

We discuss the influence of atomic thermal motion on the efficiency of multimode quantum memory in two configurations: over the free expand of atoms cooled beforehand in a magneto-optical trap, and over complete mixing of atoms in a closed cell at room temperature. We consider the high-speed quantum memory, and assume that writing and retrieval are short enough, and the displacements of atoms during these stages are negligibly small. At the same time we take in account thermal motion during the storage time, which, as well known, must be much longer than durations of all the other memory processes for successful application of memory cell in communication and computation. We will analyze this influence in terms of eigenmodes of the full memory cycle and show that distortion of the eigenmodes, caused by thermal motion, leads to the efficiency reduction. We will demonstrate, that in the multimode memory this interconnection has complicated character.

A New Subthreshold Current Model for Junctionless Trigate MOSFETs to Examine Interface-Trapped Charge Effects

On the basis of the effects of interface-trapped charges on the flat-band voltage, quasi-3-D scaling equation, and Pao-Sah’s integral, a novel subthreshold current model is presented for the junctionless trigate (JLTG) MOSFETs to examine interface-trapped charge effects (ITCEs). It indicates that a thin gate oxide can effectively reduce the subthreshold current degradation caused by the ITCEs. In contrast to the thin gate oxide, a thick silicon is required to alleviate the subthreshold current degradation caused by the ITCEs. For the short-channel behavior, the positive-/negative-trapped charges can enhance/alleviate short-channel effects (SCEs) for the device. As opposed to SCEs, the long-channel JLTG transistor suffers severe ITCEs than the short-channel device. Besides, the JL double-gate device with less gate coverage of the channel can reduce more subthreshold current degradation caused by the ITCEs than both the JLTG and JL quadruple-gate devices. Due to its computational efficiency, the model can be easily used to explore the hot-carrier-induced current behavior for the fully depleted JLTG MOSFETs for its memory cell application.

A Novel Quasi-3D Interface-Trapped-Charge-Degraded Threshold Voltage Model for Omega-Gate <inline-formula> <tex-math notation="TeX">$(\Omega{G})$</tex-math></inline-formula> MOSFETs

With the effects of equivalent oxide charges on the flat-band voltage, we report a novel quasi-3D interface-trapped-charge-degraded threshold voltage model for omega-gate (ΩG) MOSFETs based on the quasi-3D scaling equation, including the equivalent number of gates. It is found that a thin gate oxide is required to reduce threshold voltage degradation by the trapped charges. For the positive/negative trapped charges, the damaged device with a thick/thin silicon film suffers from small/large threshold voltage degradation. In addition, a large/ small oxide-to-gate underlap coverage factor can be adjusted to improve the threshold voltage degradation by the positive/negative trapped charges. For the short-channel behavior, a damaged device with the negative trapped charges is better than the one with the positive trapped charges. The model can be used to explore the hot-carrier-induced threshold voltage degradation of the ΩG MOSFET for its memory cell application.

A Compact Interface-Trapped-Charge-Induced Subthreshold Current Model for Surrounding-Gate MOSFETs

With the effects of equivalent oxide charges on the flatband voltage, we report a compact interface-trapped-charge-induced subthreshold current model for the surrounding-gate (SRG) MOSFETs based on the scaling equation and the drift-diffusion approach. It is found that a thin gate oxide can effectively reduce the subthreshold current degradation caused by the positive/negative trapped charges. In contrast to the thin gate oxide, a thick silicon film is required to alleviate the subthreshold current degradation caused by the negative trapped charges. In comparison with the fresh device, the damaged device with negative/positive trapped charges can decrease/increase more subthreshold current roll-up caused by the short-channel effects (SCEs). The model can be used to explore the hot-carrier-induced subthreshold current degradation for the SRG MOSFETs for its memory cell application.

A New Interface-Trapped-Charge-Degraded Subthreshold Current Model for Quadruple-Gate MOSFETs

By accounting for the effects of equivalent oxide charges on the flat-band voltage, a novel interface-trapped-charge-degraded subthreshold current model is presented for the quadruple-gate (QG) MOSFETs based on the quasi-3-D scaling equation and Pao-Sah's integral. It indicates that a thin gate oxide can effectively reduce the subthreshold current degradation caused by the trapped charges. In contrast to the thin gate oxide, a thick silicon film is required to alleviate the subthreshold current degradation caused by the negative trapped charges. For the short-channel behavior, the damaged device with negative and positive trapped charges can decrease and increase subthreshold current roll up caused by the short-channel effects, respectively. Due to computational efficiency, the model can be easily used to explore the hot-carrier-induced current behavior for the fully depleted QG MOSFETs for its memory cell application.

GIDL in Doped and Undoped FinFET Devices for Low-Leakage Applications

Investigation of gate-induced drain leakage (GIDL) in thick-oxide dual-gate doped- and undoped-channel FinFET devices through 3-D process and device simulations is presented. For a given gate length (LG) and gate dielectric thickness, the placement and grading of the drain junction and the channel doping are shown to have a tremendous impact on GIDL. Suppression of GIDL by as much as two orders of magnitude can be realized by formation of steep underlapped junctions for both doped- and undoped-channel devices. The prospect of low leakage levels in doped-channel high- VT FinFETs makes them suitable for memory cell applications.

MISFET structures with barium titanate as a dielectric layer for application in memory cells

This work shows investigations of La 2O 3 containing BaTiO 3 thin films deposited on Si substrates by Radio Frequency Plasma Sputtering (RF PS) of sintered BaTiO 3 + La 2O 3 (2 wt.%) target. Round, aluminum (Al) electrodes were evaporated on top of the deposited layers. Thus, metal–insulator–semiconductor (MIS) structures were created with barium titanate thin films playing the role of an insulator. The MIS structures enabled a subsequent electrical characterization of the studied film by means of current–voltage (I–V) and capacitance–voltage (C–V) measurements. Several electronic parameters, i.e., ε ri , ρ, V FB , Δ V H were extracted from the obtained characteristics. Moreover, the paper describes technology process of MISFETs fabrication and possibility of their application as memory cells. The influence of voltage stress on transfer and output I–V characteristics of the transistors are presented and discussed.

Multilevel resistive switching in Ti/CuxO/Pt memory devices

The multilevel resistive switching (RS) behaviors of the Ti/CuxO/Pt device were investigated by controlling the operated parameters of current and voltage bias in this study. We demonstrated that at least five-level memory states for data storage could be determined by controlling the current compliance, the span of voltage sweeping, and the amplitude of voltage pulse imposed on the memory device. During the dc voltage sweeping mode, not only the multilevel ON-states but also the multilevel OFF-states were achieved for the multilevel storage. The RS mechanism of the Ti/CuxO/Pt device is proposed to be related to the formation/rupture of the conducting filaments, arising from the interfacial oxygen ion migration between the Ti top electrode and CuxO films. Moreover, a possible conduction scenario for the multilevel RS behaviors is also suggested. Owing to all the multilevel memory states are distinguishable and possess the nondestructive readout property, it implies that the Ti/CuxO/Pt device has the promising potential for the future multilevel-capability memory cell application.

Switching Device Based on a Thin Film of an Azo-Containing Polymer for Application in Memory Cells

Results obtained on a conductive multilevel device realized with a 100 nm azo-polymer film are reported. The capability to switch between three different conductance states makes the device versatile both for Write Once Read Many and Write Many Read Many memory cell application. The analysis of the - curves indicates that the hysteretic conductance change with the external voltage can be explained in terms of different hopping distances existing between the nearest neighbors intervening in the two conformational states of the molecular structure.

Plasma etching of lead germanate (PGO) ferroelectric thin film

The lead germanate (PGO) thin film has been proposed for FeRAM devices, especially for one transistor ferroelectric memory cell application. To realize such applications, it is important not only to form the PGO thin film, but also to etch/pattern such thin film. In this work, plasma etching of PGO thin films was investigated by using chlorine or fluorine gas chemistries in an electron cyclotron resonance plasma reactor. Etch rates were studied as a function of etching conditions. The results indicated that a chemical effect, rather than a pure physical sputtering, was the dominant factor during the plasma etching of PGO material. It was also found that under the same etching conditions, a Cl2/Ar chemistry was more effective in PGO etching than a CF4/Ar chemistry. Under the etching conditions studied, there was no obvious plasma etching damage to the composition of the PGO thin films. However, the surface oxygen and chlorine concentration increased after the etching, indicating there might be some etch-induced surface residue. Such residue was thermally unstable, and can be greatly reduced by a postetch anneal in O2.

Epitaxial oxide thin films on Si(001)

Over the years, the development of epitaxial oxides on silicon has been a great technological challenge. Amorphous silicon oxide layer forms quickly at the interface when the Si surface is exposed to oxygen, making the intended oxide heteroepitaxy on Si substrate extremely difficult. Epitaxial oxides such as BaTiO3 (BTO) and SrTiO3 (STO) integrated with Si are highly desirable for future generation transistor gate dielectric and ferroelectric memory cell applications. In this article, we review the recent progress in the heteroepitaxy of oxide thin films on Si(001) substrate by using the molecular beam epitaxy technique at Motorola Labs. Structural, interfacial and electrical properties of the oxide thin films on Si have been characterized using in situ reflection high energy electron diffraction, x-ray diffraction, spectroscopic ellipsometry, atomic force microscopy, Auger electron spectroscopy, x-ray photoelectron spectroscopy, high-resolution transmission electron microscopy, high-resolution transmission electron energy loss spectroscopy, capacitance–voltage and current–voltage measurement. We also present the transistor results and address the impact of the epitaxial oxide films on future generation metal-oxide-semiconductor field effect transistors.

Enhanced Current Injection in Thermal Oxides Grown on Texturized Silicon

A new technique to achieve enhanced current injection in layers thermally grown on texturized monocrystalline Si surfaces is presented. Sites of local field enhancement are created at the interface by anisotropic chemical etching of the Si surface prior to oxidation. Current‐voltage characteristics measured on MOS capacitor structures having a 60 nm thick dry thermal oxide grown at 1000°C follow a Fowler‐Nordheim law over more than 5 decades of current and exhibit local field enhancement factors in the range 1–8 (exceptionally up to 13), depending on the etching conditions used. These high field enhancement factors lead to a reduction of the average field necessary to inject a current density of 10−8 A/cm2 to values in the range from 1.5 to 2.3 MV/cm for textured interface oxides as compared to values in excess of 7 MV/cm for smooth interface oxides grown under identical conditions. Characteristics of both texturized and smooth interface capacitors, measured after injecting a total charge of , exhibit a slight shift of ∼0.4 MV/cm to higher fields. The behavior of both types of oxides following field stress is similar, indicating that the trapping characteristics of the oxide are not degraded by the surface texturization. The method presented constitutes a promising alternative to other current enhancement techniques, based for example on the use of polysilicon oxides or off‐stoichiometric films, which are presently under investigation for EEPROM‐type memory cell applications.