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Abstract
On the basis of the quasi-three-dimensional scaling equation, equivalent number of gates, and minimum bottom-central potential, a novel threshold voltage model for the short-channel junctionless inverted T-shaped gate FETs (JLITFET) is presented. It is shown that the thin thickness of the inverted T-shaped silicon base (ITSB) is superior to the thick one in respect of suppressing SCEs and reducing the threshold voltage roll-off. With the same width of ITSB, the large height of fins is required to resist SCEs and reduce the threshold voltage degradation as the channel length is decreased. In comparison to both junctionless double-gate FET and junctionless FinFET, the JLITFET will suffer the least threshold voltage degradation among the three FETs due to its smallest scaling length. With its computational efficiency, the model can be easily used for the memory cell application for the JLITFET.
Published Version
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