Memory Blocks Research Articles

Quercetin, the new stress buster: Investigating the transcriptional and behavioral effects of this flavonoid on multiple stressors using Lymnaea stagnalis

Growing evidence suggests that a flavonoid-rich diet can prevent or reverse the effects of stressors, although the underlying mechanisms remain poorly understood. One common and abundant flavonoid found in numerous foods is quercetin. This study utilizes the pond snail Lymnaea stagnalis, a valid model organism for learning and memory, and a simple but robust learning paradigm—operant conditioning of aerial respiration—to explore the behavioral and transcriptional effects of different stressors on snails' cognitive functions and to investigate whether quercetin exposure can prevent stress effects on learning and memory formation. Our findings demonstrate that three different stressors—severe food deprivation, lipopolysaccharide injection (an inflammatory challenge), and fluoride exposure (a neurotoxic agent)—block memory formation for operant conditioning and affect the expression levels of key targets related to stress response, energy balance, and immune response in the snails' central ring ganglia. Remarkably, exposing snails to quercetin for 1 h before stress presentation prevents these effects at both the behavioral and transcriptional levels, demonstrating the potent stress-preventive properties of quercetin. Despite the evolutionary distance from humans, L. stagnalis has proven to be a valuable model for studying conserved mechanisms by which bioactive compounds like quercetin mitigate the adverse effects of various stressors on cognitive functions across species. Moreover, these findings offer insights into quercetin's potential for mitigating stress-induced physiological and cognitive impairments.

Accelerating the neural network controller embedded implementation on FPGA with novel dropout techniques for a solar inverter

Accelerating neural network (NN) controllers is important for improving the performance, efficiency, scalability, and reliability of real-time systems, particularly in resource-constrained embedded systems. This paper introduces a novel weight-dropout method for training neural network controllers in real-time closed-loop systems, aimed at accelerating the embedded implementation for solar inverters. The core idea is to eliminate small-magnitude weights during training, thereby reducing the number of necessary connections while ensuring the network’s convergence. To maintain convergence, only non-diagonal elements of the weight matrices were dropped. This dropout technique was integrated into the Levenberg–Marquardt and Forward Accumulation Through Time algorithms, resulting in more efficient training for trajectory tracking. We executed the proposed training algorithm with dropout on the AWS cloud, observing a performance increase of approximately four times compared to local execution. Furthermore, implementing the neural network controller on the Intel Cyclone V Field Programmable Gate Array (FPGA) demonstrates significant improvements in computational and resource efficiency due to the proposed dropout technique leading to sparse weight matrices. This optimization enhances the suitability of the neural network controller for embedded environments. In comparison to Sturtz et al. (2023), which dropped 11 weights, our approach eliminated 18 weights, significantly boosting resource efficiency. This resulted in a 16.40% reduction in Adaptive Logic Modules (ALMs), decreasing the count to 47,426.5. Combinational Look-Up Tables (LUTs) and dedicated logic registers saw reductions of 17.80% and 15.55%, respectively. However, the impact on block memory bits is minimal, showing only a 1% improvement, indicating that memory resources are less affected by weight dropout. In contrast, the usage of Memory 10 Kilobits (MK10s) dropped from 97 to 87, marking a 10% improvement. We also propose an adaptive dropout technique to further improve the previous results.

Double-Ended Bit-Stealing for Algebraic Data Types

Algebraic data types are central to the development and evaluation of most functional programs. It is therefore important for compilers to choose compact and efficient representations of such types, in particular to achieve good memory footprints for applications. Algebraic data types are most often represented using blocks of memory where the first word is used as a so-called tag, carrying information about the constructor, and the following words are used for carrying the constructor's arguments. As an optimisation, lists are usually represented more compactly, using a technique called bit-stealing, which, in its simplest form, uses the word-alignment property of pointers to byte-addressed allocated memory to discriminate between the nil constructor (often represented as 0x1) and the cons constructor (aligned pointer to allocated pair). Because the representation supports that all values can be held uniformly in one machine word, possibly pointing to blocks of memory, type erasure is upheld. However, on today's 64-bit architectures, memory addresses (pointers) are represented using only a subset of the 64 bits available in a machine word, which leave many bits unused. In this paper, we explore the use, not only of the least-significant bits of pointers, but also of the most-significant bits, for representing algebraic data types in a full ML compiler. It turns out that, with such a particular utilisation of otherwise unused bits, which we call double-ended bit-stealing, it is possible to choose unboxed representations for a large set of data types, while still not violating the principle of uniform data-representations. Examples include Patricia trees, union-find data structures, stream data types, internal language representations for types and expressions, and mutually recursive ASTs for full language definitions. The double-ended bit-stealing technique is implemented in the MLKit compiler and speedup ranges from 0 to 26 percent on benchmarks that are influenced by the technique. For MLKit, which uses abstract data types extensively, compilation speedups of around 9 percent are achieved for compiling MLton (another Standard ML compiler) and for compiling MLKit itself.

Using a Mathematical Model to Evaluate the Efficiency of Memory Allocation Algorithm

One of the key research areas in operating systems is memory allocation and process management by the operating system. Memory allocation is the process of allocating blocks of memory to different executing processes in order to improve overall system performance. This paper analyses the efficiency of memory allocation algorithms (first fit, best fit and worst fit) in the multiple partition and contiguous memory allocation scheme. A Mathematical model was used on process sizes in terms of percentage internal fragmentation (IF%), percentage external fragmentation (EF%), and percentage total utilization (TU%), this was done to compare the performance of the memory allocation algorithm. Results from the analysis show that the best fit made more efficient use of the available memory space than that of first-fit and worst fit.

High‐throughput in‐memory bitwise computing based on a coupled dual‐SRAM array with independent operands

AbstractThe successful implementation of artificial intelligence algorithms depends on the capacity to execute numerous repeated operations, which, in turn, requires systems with high data throughput. Although emerging computing‐in‐memory (CIM) eliminates the need for frequent data transfer between the memory and processing blocks and enables parallel activation of multiple rows, the traditional structure, where each row has only one identical input value, significantly limits its further application. To solve this problem, this study proposes a dual‐SRAM CIM architecture in which two SRAM arrays are coupled such that all operands are different, thus rendering the use of CIM considerably more flexible. The proposed dual‐SRAM array was implemented through a 55‐nm process, essentially delivering a frequency of 361 MHz for a 1.2‐V supply and energy efficiency of 161 TOPS/W at 0.9 V supply.

Chemical Memory in Primitive Organisms: Evolutionary Insights and Mechanistic Perspectives

Memory, the cornerstone of adaptive behavior, has been extensively studied within the confines of neural systems. A comprehensive literature review was conducted using key academic databases such as PubMed, Web of Science, and Google Scholar. The methodology prioritized peer-reviewed papers, reviews, and primary research, with a particular emphasis on articles relevant to chemical memory in primitive organisms. This review sheds light on the less-explored territory of chemical memory in primitive organisms. From the complex neural pathways in humans to the basic chemical interactions in bacteria and protozoa, this study underscores the evolutionary significance and ubiquity of information storage in biology. A notable highlight is the exploration of the ability of plants to adaptively respond to their environment despite lacking a central nervous system, emphasizing the role of epigenetic markers in stress memory. In organisms devoid of advanced neural systems, chemical reactions, and interactions pave the way for memory mechanisms, offering insight into the foundational building blocks of memory. The findings presented challenges in traditional neuro-centric views, broadening our understanding of memory and highlighting its pivotal role in the evolutionary tapestry of life.

Simulation and reconstruction for 3D elastic wave using multi-GPU and CUDA-aware MPI

3D finite-difference time-domain numerical simulation and reconstruction based on the domain decomposition technique are essential parts of high-performance computation for reverse-time migration and full-waveform inversion. However, the low GPU utilization in computing for small-sized models and the tremendous memory consumption for large-sized models may result in low computational efficiency and high memory costs. This paper proposes a contiguous memory management (CMM) method and a variable-order wavefield reconstruction (VWR) method. The CMM allocates the memory of many small-sized arrays used for MPI communications on a larger-sized contiguous memory block, which aims to reduce the number of MPI communications between subdomains and improve the communication bandwidth, thus reducing the MPI time overhead and improving the GPU utilization. Meanwhile, the VWR can flexibly set the number of layers of boundary wavefield used for source wavefield reconstruction according to the host memory capacity and accuracy requirements. Since one layer of boundary wavefield could be stored using the VWR, the memory consumption of host memory can be significantly alleviated. Numerical experiments show that GPU utilization in computing for the model with a size of 1213 can be improved from 25% to 90% using the CMM method, and the VWR method can reduce memory consumption by about 86% while maintaining good accuracy in wavefield reconstruction. In addition, the issue of how to obtain a domain decomposition scheme with optimal performance is discussed in this paper.

Modeling Retention Errors of 3D NAND Flash for Optimizing Data Placement

Considering 3D NAND flash has a new property of process variation (PV) , which causes different raw bit error rates (RBER) among different layers of the flash block. This paper builds a mathematical model for estimating the retention errors of flash cells, by considering the factor of layer-to-layer PV in 3D NAND flash memory, as well as the factors of program/erase (P/E) cycle and retention time of data. Then, it proposes classifying the layers of flash block in 3D NAND flash memory into profitable and unprofitable categories, according to the error correction overhead. After understanding the retention error variation of different layers in 3D NAND flash, we design a mechanism of data placement, which maps the write data onto a suitable layer of flash block, according to the data hotness and the error correction overhead of layers, to boost read performance of 3D NAND flash. The experimental results demonstrate that our proposed retention error estimation model can yield a R 2 value of 0.966 on average, verifying the accuracy of the model. Based on the estimated retention error rates of layers, the proposed data placement mechanism can noticeably reduce the read latency by 29.8 % on average, compared with state-of-the-art methods against retention errors for 3D NAND flash memory.

DLLBVS: Design of a High-Efficiency Deep Learning based Low-BER Video Streaming Model for High-Noise Wireless Networks

Design of video streaming models for high-noise networks is a multimodal process that requires efficient channel modelling, noise analysis, error-specific stream control, intelligent data augmentation, etc. This article proposes design of a high-efficiency deep learning based low-BER (Bit Error Rate) Video streaming model for high-noise wireless networks. The proposed model initially uses a Long-Short-Term Memory (LSTM) block for estimation of frame level features, and then uses Orthogonal Frequency Division Multiple Access (OFDMA) based modulation platform for transmission and reception of processed video frames. The OFDMA model is cascaded with a chaotic communication module, which assists in improving data fidelity under different noise conditions. The chaotic communication module is optimized using Grey Wolf Optimizer (GWO), which assists in setting up its hyperparameters for better efficiency under real-time communication scenarios. Video frames were pre-processed using Dual Neural Networks that assisted in estimation of differential frame information sets. Due to estimation of this differential frame information, streaming speed is improved, which assists in increasing number of frames transmitted per second, thereby improving streaming performance for different video types. This frame information is further processed by an iterative Gated Recurrent Unit (GRU) based VARMAx Model, which assists in predicting frame removal instances, thus assisting in faster & low error communications. The GRU VARMAx Model optimizes data flow, thus reducing congestion and improving throughput. The model was tested under AWGN (Additive While Gaussian Noise), Rayleigh, & Rician channel types, and its efficiency was compared with standard streaming techniques in terms of communication delay, Bit Error Rate, Peak to Average Power Ratio (PAPR), throughput, communication jitter and computational complexity levels. Based on this comparison it was observed that the proposed model showcased 3.5% lower communication delay, 8.3% lower BER, 5.9% lower PAPR, 10.5% higher throughput, 3.9% lower jitter and 6.4% lower computational complexity, which makes it highly useful for a wide variety of real-time streaming scenarios.

ARCHITEKTONICZNE, STRUKTURALNE I FUNKCJONALNE CECHY RÓWNOLEGŁO-HIERARCHICZNEJ ORGANIZACJI PAMIĘCI

Parallel hierarchical memory (PI memory) is a new type of memory that is designed to improve the performance of parallel computing systems. PI memory is composed of two blocks: a mask RAM and a tail element RAM. The mask RAM stores the masks that are used to encode the information, while the tail element RAM stores the actual information. The address block of the PI memory is responsible for generating the physical addresses of the cells where the tail elements and their masks are stored. The address block also stores the field of addresses where the array was written and associates this field of addresses with the corresponding external address used to write the array. The proposed address block structure is able to efficiently generate the physical addresses of the cells where the tail elements and their masks are stored. The address block is also able to store the field of addresses where the array was written and associate this field of addresses with the corresponding external address used to write the array. The proposed address block structure has been implemented in a prototype PI memory. The prototype PI memory has been shown to be able to achieve significant performance improvements over traditional memory architectures. The paper will present a detailed description of the PI transformation algorithm, a description of the different modes of addressing organization that can be used in PI memory, an analysis of the efficiency of parallel-hierarchical memory structures, and a discussion of the challenges and future research directions in the field of PI memory.

Basic Approaches for Reducing Power Consumption in Finite State Machine Circuits—A Review

Methods for reducing power consumption in circuits of finite state machines (FSMs) are discussed in this review. The review outlines the main approaches to solving this problem that have been developed over the last 40 years. The main sources of power dissipation in CMOS circuits are shown; the static and dynamic components of this phenomenon are analyzed. The power consumption saving can be achieved by using coarse-grained methods common to all digital systems. These methods are based on voltage or/and clock frequency scaling. The review shows the main structural diagrams generated by the use of these methods when optimizing the power characteristics of FSM circuits. Also, there are various known fine-grained methods taking into account the specifics of both FSMs and logic elements used. Three groups of the fine-grained methods targeting FPGA-based FSM circuits are analyzed. These groups include clock gating, state assignment, and replacing look-up table (LUT) elements by embedded memory blocks (EMBs). The clock gating involves a separate or joint use of such approaches as the (1) decomposition of FSM inputs and (2) disabling FSM inputs. The aim of the power-saving state assignment is to reduce the switching activity of a resulting FSM circuit. The replacement of LUTs by EMBs allows a reduction in the power consumption due to a decrease in the number of FSM circuit elements and their interconnections. We hope that the review will help experts to use known methods and develop new ones for reducing power consumption. We think that a good knowledge and understanding of existing methods of reducing power consumption is a prerequisite for the development of new, more effective methods to solve this very important problem. Although the methods considered are mainly aimed at FPGA-based FSMs, they can be modified, if necessary, and used for the power consumption optimization of FSM circuits implemented with other logic elements.

Exploiting RPMB authentication in a closed source TEE implementation

Embedded Multimedia Cards (eMMCs) provide a protected memory area called the Replay Protected Memory Block (RPMB). eMMCs are commonly used as storage media in modern smartphones. In order to protect these devices from unauthorized access, important data is stored in the RPMB area in an authenticated manner. Modification of the RPMB data requires a pre-shared authentication key. An unauthorized user cannot change the stored data.On modern devices, this pre-shared key is generated and used exclusively within a Trusted Execution Environment (TEE) preventing attackers from access. In this paper, we investigate how the authentication key for RPMB is programmed on the eMMC. We found that this key can be extracted directly from the target memory chip. Once obtained, the authentication key can be used to manipulate stored data. In addition, poor implementation of certain security features, aimed at preventing replay attacks using RPMB on the host system can be broken by an attacker. We show how the authentication key can be extracted and how it can be used to break the anti-rollback protection to enable data restoration even after a data wipe operation has been completed.Our findings show that non-secure RPMB implementations can enable forensic investigators to break security features implemented on modern smartphones.

Air quality index prediction using seasonal autoregressive integrated moving average transductive long short‐term memory

AbstractWe obtain the air quality index (AQI) for a descriptive system aimed to communicate pollution risks to the population. The AQI is calculated based on major air pollutants including O3, CO, SO2, NO, NO2, benzene, and particulate matter PM2.5 that should be continuously balanced in clean air. Air pollution is a major limitation for urbanization and population growth in developing countries. Hence, automated AQI prediction by a deep learning method applied to time series may be advantageous. We use a seasonal autoregressive integrated moving average (SARIMA) model for predicting values reflecting past trends considered as seasonal patterns. In addition, a transductive long short‐term memory (TLSTM) model learns dependencies through recurring memory blocks, thus learning long‐term dependencies for AQI prediction. Further, the TLSTM increases the accuracy close to test points, which constitute a validation group. AQI prediction results confirm that the proposed SARIMA–TLSTM model achieves a higher accuracy (93%) than an existing convolutional neural network (87.98%), least absolute shrinkage and selection operator model (78%), and generative adversarial network (89.4%).

PMAlloc: A Holistic Approach to Improving Persistent Memory Allocation

Persistent memory allocation is a fundamental building block for developing high-performance and in-memory applications. Existing persistent memory allocators suffer from many performance issues. First, they may introduce repeated cache line flushes and small random accesses in persistent memory for their poor heap metadata management. Second, they use static slab segregation resulting in a dramatic increase in memory consumption when allocation request size is changed. Third, they are not aware of NUMA effect, leading to remote persistent memory accesses in memory allocation and deallocation processes. In this paper, we design a novel allocator, named PMAlloc, to solve the above issues simultaneously. (1) PMAlloc eliminates cache line reflushes by mapping contiguous data blocks in slabs to interleaved metadata entries stored in different cache lines. (2) It writes small metadata units to a persistent bookkeeping log in a sequential pattern to remove random heap metadata accesses in persistent memory. (3) Instead of using static slab segregation, it supports slab morphing, which allows slabs to be transformed between size classes to significantly improve slab usage. (4) It uses a local-first allocation policy to avoid allocating remote memory blocks. And it supports a two-phase deallocation mechanism including recording and synchronization to minimize the number of remote memory access in the deallocation. PMAlloc is complementary to the existing consistency models. Results on 6 benchmarks demonstrate that PMAlloc improves the performance of state-of-the-art persistent memory allocators by up to 6.4x and 57x for small and large allocations, respectively. PMAlloc with NUMA optimizations brings a 2.9x speedup in multi-socket evaluation and is up to 36x faster than other persistent memory allocators. Using PMAlloc reduces memory usage by up to 57.8%. Besides, we integrate PMAlloc in a persistent FPTree. Compared to the state-of-the-art allocators, PMAlloc improves the performance of this application by up to 3.1x.

High-Speed Design of Post Quantum Cryptography With Optimized Hashing and Multiplication

In this brief, we realize different architectural techniques for improving the performance of post-quantum cryptography (PQC) algorithms when implemented as hardware accelerators on an application-specific integrated circuit (ASIC) platform. Having SABER as a case study, we designed a 256-bit wide architecture geared for high-speed cryptographic applications that incorporates smaller and distributed SRAM memory blocks. Moreover, we have adapted the building blocks of SABER to process 256-bit words. We have also used a buffering technique for efficient polynomial coefficient multiplications to reduce the clock cycle count. Finally, double-sponge functions are combined serially (one after another) in a high-speed KECCAK core to improve the hash operations of SHA/SHAKE. For key-generation, encapsulation, and decapsulation operations of SABER, our 256-bit wide accelerator with a single sponge function is 1.71x, 1.45x, and 1.78x faster than the raw clock cycle count of a serialized SABER design. Similarly, our 256-bit implementation with double-sponge functions takes 1.08x, 1.07x & 1.06x fewer clock cycles compared to its single-sponge counterpart. The studied optimization techniques are not specific to SABER – they can be utilized for improving the performance of other lattice-based PQC accelerators.

Multi-Stage Fusion Framework for Short-Term Passenger Flow Forecasting in Urban Rail Transit Systems Using Multi-Source Data

To improve real-time operation and management in urban rail transit (URT) systems, accurate and reliable short-term passenger flow forecasting at the network level is a crucial task. Although numerous endeavors have been devoted to this field, the insufficient topological representation for passenger flows in the URT network, the overlooking of intrinsic correlations among multi-source data, and the information loss in deep-learning frameworks are still critical issues that need to be addressed. This study proposes a multi-stage fusion passenger forecasting (MSFPF) model to accomplish short-term multi-step passenger forecasting leveraging multi-source data, and overcome the above-mentioned challenges. Based on the characteristics of passenger flows in the URT network, time-based origin–destination flow data is involved and utilized to enhance the representation of flows and provide spatial-temporal features. Then, the interaction and relationship among multi-source data are estimated to capture their intrinsic correlations. To effectively and comprehensively extract temporal and spatial features, a transformer long short-term memory block and a depth-wise attention block are constructed with attention mechanisms and employed. Furthermore, we construct the multi-stage fusion (MSF) structure to alleviate the information loss during the learning process, which is a significant component in improving the forecasting accuracy. In addition, the model is applied to two large-scale real-world datasets, in which it outperforms nine widely used baselines and four specific variants of itself. The quantitative experiments demonstrate the robustness and superiority of the proposed MSFPF model, and the significant contribution of the MSF structure in the model.

INCREASING THE EFFICIENCY OF THE DRILLING MACHINE WITH STRUCTURAL ORGANIZATION

The purpose of the article is to consider the method of structural organization of hydropneumatic units and its practical application. The synthesis of control devices of hydraulic and pneumatic units is an actual question, since at this stage the main technical characteristics affecting quality and functioning are formed. A significant element is the chosen structural organization, since the rationality of its structure affects not only speed, ease of operation and rationality of the scheme itself but also standardization and ease of device creation. Thanks to the definition of the structural organization of hydropneumatic units, namely its elements and the interaction between them in a discrete-analog system, an example of the construction of a hydropneumatic system of a drilling machine was considered. In the article, the main components of the structural organization are considered, a scheme is built, based on which, when designing a hydropneumatic unit, it is realistic to reduce the number of memory elements and logical elements. The sets and subsets of this structure are considered, the input and output signals of the hydropneumatic unit are determined. The memory block and its control unit are considered. Coincidence blocks and inclusion division blocks are considered. The scheme of the drilling machine is presented and its description is made with the indication of the element base. The beginning of the operation of this scheme is described and the operation graph for technological transitions within it is constructed. A table of inclusions for the scheme is built, which contains information about the current positions of executive devices and their operating mode, its current state, as well as about the interaction of input and output devices. The definition of the concept of the graph is provided. CPRs were constructed for transition states, taking into account the signals that move the system to the next state and the signals acting inside the transition. The respective systems of linear equations were minimized. The place of logical controllers in this structural organization is considered.

Exploring Long Short Term Memory Algorithms for Low Energy Data Aggregation

Long short-term memory methods are employed for data consolidation in intricate low-energy devices. It has enabled accurate and efficient aggregation of statistics in limited electricity settings, facilitating the review and retrieval of data while minimizing electricity wastage. The LSTM rules analyze, organize, and consolidate vast datasets inside weakly connected structures. It has employed a recurrent neural network to handle data processing, particularly nonlinear interactions. The machine's capabilities are subsequently examined and stored utilizing memory blocks. Memory blocks retain extended temporal connections within the data, facilitating adaptive and precise information aggregation. These blocks facilitate the system's ability to shop and utilize relevant capabilities for quick retrieval. The proposed algorithm offers realistic tuning capabilities such as learning rate scheduling and total regularization based on dropout like green information aggregation. These enable systems to reduce over fitting while permitting precise adjustment of the settings. It allows for optimizing the algorithm to provide highly dependable performance within weak structures, enhancing data aggregation techniques' energy efficiency. Standard algorithms provide an efficient, accurate solution for aggregating information in low-power systems. It facilitates evaluating, retrieving, and aggregating accurate and reliable information using memory blocks, adaptive tuning, and efficient learning rate scheduling.

Doświadczenie kryzysu jako składnik zbiorowej pamięci przedsiębiorców

Objective – To identify and explain the reasons leading the company to a micro‑scale crisis, which is independent of the market crisis. Research method – The use of in‑depth qualitative interviews with entrepreneurs. They covered entrepreneurs working in the profession for at least twenty years and representing the sector of micro, small and medium‑sized enterprises. Result – The experience of a company crisis on a microscale is an individual experience for each entrepreneur, independent of the market situation. It is the building block of the collective memory of entrepreneurs. Originality / value / implications / recommendations – Based on in‑depth qualitative research, using original statements of entrepreneurs, it has been proven that the company’s crisis, perceived as a sudden event, has its genesis in informal institutions, including ethical and cultural principles in interpersonal relations. A large role in mitigating the effects of the crisis is played by the word, the language of everyday communication of entrepreneurs with clients, contractors, as well as those in power with this professional group.

An evaluation of recent advancements in biological sensory organ-inspired neuromorphically tuned biomimetic devices.

In the field of neuroscience, significant progress has been made regarding how the brain processes information. Unlike computer processors, the brain comprises neurons and synapses instead of memory blocks and transistors. Despite advancements in artificial neural networks, a complete understanding concerning brain functions remains elusive. For example, to achieve more accurate neuron replication, we must better understand signal transmission during synaptic processes, neural network tunability, and the creation of nanodevices featuring neurons and synapses. This study discusses the latest algorithms utilized in neuromorphic systems, the production of synaptic devices, differences between single and multisensory gadgets, recent advances in multisensory devices, and the promising research opportunities available in this field. We also explored the ability of an artificial synaptic device to mimic biological neural systems across diverse applications. Despite existing challenges, neuroscience-based computing technology holds promise for attracting scientists seeking to enhance solutions and augment the capabilities of neuromorphic devices, thereby fostering future breakthroughs in algorithms and the widespread application of cutting-edge technologies.