Memory Bits Research Articles

Real-Time Distance Evaluation System for Wireless Localization

The paper describes the FPGA implementation of a novel position evaluation algorithm based on the time difference of arrival (TDOA) principle that combines the characteristics of an Orthogonal Frequency Division Modulation (OFDM) symbol with the properties of the Zadoff-Chu mathematical sequences. The resulting system is highly scalable and its characteristics are easily adaptable to different operating scenarios. The algorithm has been implemented using the Stratix IV-E EP4SGX70HF35C3 FPGA, requiring about 112k bit of memory and less than 44k logic elements of which about 16k are registers. The paper describes the algorithm and its FPGA implementation along with experimental results validating the system performance even in the presence of multipath interferences and showing precision in target position estimation that is better than 2 cm.

Primal-dual based distributed approximation algorithm for Prize-collecting Steiner tree

The Prize-collecting Steiner tree (PCST) problem is a generalization of the Steiner tree problem that finds applications in network design, content distribution networks, and many more. There are a few centralized approximation algorithms [D. Bienstock, M. X. Goemans, D. Simchi-Levi and D. Williamson, A note on the prize collecting traveling salesman problem. Math. Program. 59 (1993) 413–420; M. X. Goemans and D. E. Williamson, A general approximation technique for constrained forest problems, SIAM J. Appl. Math. 24(2) (1995) 296–317; D. S. Johnson, M. Minkoff and S. Phillips, The prize collecting Steiner tree problem: Theory and practice, in Proc. Eleventh Annual ACM-SIAM Symp. Discrete Algorithms, SODA ’00 (2000), pp. 760–769; A. Archer, M. Hossein Bateni and M. Taghi Hajiaghayi, Improved approximation algorithms for prize-collecting Steiner tree and TSP, SIAM J. Comput. 40(2) (2011) 309–332] for solving the PCST problem. However, the problem has seen very little progress in the distributed setting; to the best of our knowledge, the only distributed algorithms proposed so far are due to Rossetti [N. G. Rossetti, A first attempt on the distributed prize-collecting Steiner tree problem, M.Sc. thesis, University of Iceland, Reykjavik (2015)]: one of them fails to guarantee a constant approximation factor while the other one is essentially centralized. In this work, first, we present a deterministic [Formula: see text] factor distributed approximation algorithm (D-PCST algorithm) that constructs a PCST for a given connected undirected graph of [Formula: see text] nodes with non-negative edge weights and non-negative prize value for each node. The D-PCST algorithm is based on the primal-dual method and uses a technique of preserving dual constraints in a distributed manner, without relying on knowledge of the global structure of the network. For an input graph [Formula: see text], the round and message complexities of the D-PCST algorithm in the CONGEST model are [Formula: see text] and [Formula: see text] respectively, where [Formula: see text] and [Formula: see text]. Furthermore, we modify the D-PCST algorithm and show that a [Formula: see text]-approximate PCST can be deterministically computed using [Formula: see text] rounds and [Formula: see text] messages in the CONGEST model, where [Formula: see text] is the unweighted diameter of [Formula: see text]. For networks with [Formula: see text], the modified D-PCST algorithm performs better than the original one in terms of the round complexity. Both the algorithms require [Formula: see text] bits of memory in each node, where [Formula: see text] is the maximum degree of a node in the graph.

Estimating Ag-Cu Nanoalloy Applicability for PCM Data Recording

The paper studies applicability of individual particles of Ag-Cu nanoalloys as data bits in the next generation memory devices constructed on the phase change memory principle. To fulfill this task, the structure formation was simulated with the molecular dynamics method on cooling from the melt of Ag-Cu nanoparticles of the diameter of 2.0 – 8.0 nm of different chemical compositions (with copper content in the alloy from 10 to 50 percent), based on the modified tight-binding potential (TB-SMA). The authors investigated the influence of the size effects and the heat removal rate on the formation of the clusters structure. The investigation showed that different internal structures can be developed upon cooling from the liquid phase, so there were determined some criteria of their stability. Clusters with copper content of not more than 10% and diameters of more than 6.0 nm were isolated from the entire set of the considered particles.

Effect of Initial Synaptic State on Pattern Classification Accuracy of 3D Vertical Resistive Random Access Memory (VRRAM) Synapses

Amidst the considerable attention artificial intelligence (AI) has attracted in recent years, a neuromorphic chip that mimics the biological neuron has emerged as a promising technology. Memristor or Resistive random-access memory (RRAM) is widely used to implement a synaptic device. Recently, 3D vertical RRAM (VRRAM) has become a promising candidate to reducing resistive memory bit cost. This study investigates the operation principle of synapse in 3D VRRAM architecture. In these devices, the classification response current through a vertical pillar is set by applying a training algorithm to the memristors. The accuracy of neural networks with 3D VRRAM synapses was verified by using the HSPICE simulator to classify the alphabet in 7×7 character images. This simulation demonstrated that 3D VRRAMs are usable as synapses in a neural network system and that a 3D VRRAM synapse should be designed to consider the initial value of the memristor to prepare the training conditions for high classification accuracy. These results mean that a synaptic circuit using 3D VRRAM will become a key technology for implementing neural computing hardware.

Carbon resistive probe memory designed for ultra-high storage density

Probe-based storage memories are considered one of the most promising solutions to address the mass storage issues in the near future. However, data size arising from conventional probe memories is usually larger than probe size due to the thermal diffusion effect. To eliminate such thermal interference and make data dimension fully dominated by probe dimension, we proposed a concept of carbon-based resistive probe memory and developed a comprehensive computational model to predict its write, rewrite and readout performances governed by electro-thermal and mass concentration processes. The physical reality of such a theoretical model was demonstrated through the good agreement between the calculated and experimental measured threshold voltages for different layered thickness. The data bit of carbon-based resistive probe memory, considered as the sp2 filament inside sp3 background, is formed completely underneath the tip edge due to the localized electric field induced here. This makes the bit size fully determined by the probe tip dimension and allows for the achievement of ultra-high density using an ultra-small probe tip with low energy consumption. Such a conductive filament can be also rewritten back to its pristine sp3 state at relatively high temperature (~250 °C) and detected by sensing the device reading contrast (~1). The designed carbon-based resistive probe memory can retain its bit completeness even if we reduce the bit pitch to 28 nm for a probe size of 25 nm, exhibiting a superior immunity to thermal cross-talk effect. It, however, induces strong readout cross-talk, which is revealed from the resistance image of the multiple bit pattern. This adversely reduces the achievable recording density due to the required large bit pitch, which can be alleviated using either a very sharp tip apex or the optical readout scheme.

Sparse Harmonic Transforms: A New Class of Sublinear-Time Algorithms for Learning Functions of Many Variables

In this paper we develop fast and memory efficient numerical methods for learning functions of many variables that admit sparse representations in terms of general bounded orthonormal tensor product bases. Such functions appear in many applications including, e.g., various Uncertainty Quantification (UQ) problems involving the solution of parametric PDE that are approximately sparse in Chebyshev or Legendre product bases (Chkifa et al. in Polynomial approximation via compressed sensing of high-dimensional functions on lower sets. arXiv:1602.05823 , 2016; Rauhut and Schwab in Math Comput 86(304):661–700, 2017). We expect that our results provide a starting point for a new line of research on sublinear-time solution techniques for UQ applications of the type above which will eventually be able to scale to significantly higher-dimensional problems than what are currently computationally feasible. More concretely, let $${\mathcal {B}}$$ be a finite Bounded Orthonormal Product Basis (BOPB) of cardinality $$|{\mathcal {B}}| = N$$ . Herein we will develop methods that rapidly approximate any function f that is sparse in the BOPB, that is, $$f: {\mathcal {D}} \subset {\mathbb {R}}^D \rightarrow {\mathbb {C}}$$ of the form $$\begin{aligned} f(\varvec{x}) = \sum _{b \in {\mathcal {S}}} c_b \cdot b(\varvec{x}) \end{aligned}$$ with $${\mathcal {S}} \subset {\mathcal {B}}$$ of cardinality $$|{\mathcal {S}}| = s \ll N$$ . Our method adapts the CoSaMP algorithm (Needell and Tropp in Appl Comput Harmon Anal 26(3):301–321, 2009) to use additional function samples from f along a randomly constructed grid $${\mathcal {G}} \subset {\mathbb {R}}^D$$ with universal approximation properties in order to rapidly identify the multi-indices of the most dominant basis functions in $${\mathcal {S}}$$ component by component during each CoSaMP iteration. It has a runtime of just $$(s \log N)^{{\mathcal {O}}(1)}$$ , uses only $$(s \log N)^{{\mathcal {O}}(1)}$$ function evaluations on the fixed and nonadaptive grid $${\mathcal {G}}$$ , and requires not more than $$(s \log N)^{{\mathcal {O}}(1)}$$ bits of memory. We emphasize that nothing about $${\mathcal {S}}$$ or any of the coefficients $$c_b \in {\mathbb {C}}$$ is assumed in advance other than that $${\mathcal {S}} \subset {\mathcal {B}}$$ has $$|{\mathcal {S}}| \le s$$ . Both $${\mathcal {S}}$$ and its related coefficients $$c_b$$ will be learned from the given function evaluations by the developed method. For $$s\ll N$$ , the runtime $$(s \log N)^{{\mathcal {O}}(1)}$$ will be less than what is required to simply enumerate the elements of the basis $${\mathcal {B}}$$ ; thus our method is the first approach applicable in a general BOPB framework that falls into the class referred to as sublinear-time. This and the similarly reduced sample and memory requirements set our algorithm apart from previous works based on standard compressive sensing algorithms such as basis pursuit which typically store and utilize full intermediate basis representations of size $$\varOmega (N)$$ during the solution process.

Multi Fluxon Storage and its Implications for Microprocessor Design

One of the main challenges for single flux quantum (SFQ) technology to successfully implement a microprocessor is to have a compact and robust on-chip memory that can be used for register files and cache memory. In this context, we designed high capacity destructive readout (HC-DRO) cells. The design is based on our insight that each cell can store more than one SFQ pulse with the same area footprint of a regular DRO cell. In our current design, we demonstrate a single HC-DRO cell that can store up to three SFQ pulses thereby enabling us to store the equivalent of two bits of memory in a single cell. We have designed a register file (RF) architecture for a microprocessor and used the HC-DRO cells to reduce the Josephson junction count required for its implementation. The RF architecture presented in this work can also be used for implementing cache memories. We also demonstrate the benefits of doubling the storage density with HC-DRO cells by designing a 2-bit branch predictor circuit block for a 5-stage pipeline microprocessor that dramatically improves the cycles per instruction metric of an SFQ based microprocessor. All the design details are presented in the paper by verifying the design concepts through JSIM simulations and Verilog simulations.

Buckled beam mechanical memory using an asymmetric piezoresistor for readout

This paper presents a non-volatile mechanical memory bit that uses a bistable beam that buckles into one of two stable positions. The beam buckles because of compressive stress that is applied by oxidizing the silicon beam. In order to process a wafer with a released, buckled beam, it was necessary to use a stencil mask for the last steps to minimize damage to the device. The stencil mask is used to the etch contact openings in the thermal oxide and to deposit metal for electrical connection. Parallel electrodes located close to the bistable beam are used to electrostatically write the bit value, and asymmetric piezoresistors located at each anchor point of the bistable beam are used to read the bit value. The design was optimized using simulations, and the relationship between the readout signal, beam length, and piezoresistor length were found. The measurements demonstrate that the memory bit is promising for non-volatile memory applications where its inherent radiation hardness is required.

Soft Error Tolerant Count Min Sketches

The estimation of the frequency of the elements on a set is needed in a wide range of computing applications. For example, to estimate the number of hits that a video gets or the number of packets in a network flow. In some cases, the number of elements in the set is very large and it is not practical to maintain a table with the exact count for each of them. Instead, simpler and more efficient data structures, commonly referred to as sketches, that provide an estimate are used. Among those structures the Count Min Sketch (CMS) is one of the most popular sketches. The CMS provides estimates that have one sided errors. In more detail, the CMS returns an estimate that is equal to or larger than the actual value. An update or check requires a small and constant number of memory accesses and the memory footprint is fixed and does not depend on the number of elements. The CMS relies on several arrays of counters that are stored in memory. Memories are prone to suffer soft errors that flip the contents of memory cells due for example to ionizing radiation. Therefore, it is of interest to study the impact that soft errors can have on the CMS estimates and to propose protection techniques that minimize their effect while requiring low overhead in terms of additional memory and circuitry. To the best of our knowledge this has not been done before. In this article, first the effect of soft errors on the CMS is evaluated by injecting errors. Then, in the second part a protection technique that does not require additional memory bits is presented and compared with the protection using a parity bit. In the last part of the article, the technique is extended to protect also against double adjacent bit errors.

A lower bound on the queueing delay in resource constrained load balancing

We consider the following distributed service model: jobs with unit mean, general distribution, and independent processing times arrive as a renewal process of rate $\lambda n$, with $0<\lambda <1$, and are immediately dispatched to one of several queues associated with $n$ identical servers with unit processing rate. We assume that the dispatching decisions are made by a central dispatcher endowed with a finite memory, and with the ability to exchange messages with the servers. We study the fundamental resource requirements (memory bits and message exchange rate), in order to drive the expected queueing delay in steady-state of a typical job to zero, as $n$ increases. We develop a novel approach to show that, within a certain broad class of “symmetric” policies, every dispatching policy with a message rate of the order of $n$, and with a memory of the order of $\log n$ bits, results in an expected queueing delay which is bounded away from zero, uniformly as $n\to \infty $. This complements existing results which show that, in the absence of such limitations on the memory or the message rate, there exist policies with vanishing queueing delay (at least with Poisson arrivals and exponential service times).

Short-Term Long-Term Compute-in-Memory Architecture: A Hybrid Spin/CMOS Approach Supporting Intrinsic Consolidation

Biological memory structures impart enormous retention capacity while automatically providing vital functions for chronological information management and update the resolution of the domain and episodic knowledge. A crucial requirement for hardware realization of such cortical operations found in biology is to first design both short-term memory (STM) and long-term memory (LTM). Herein, these memory features are realized via a beyond-CMOS-based learning approach derived from the repeated input information and retrieval of the encoded data. We first propose a new binary STM-LTM architecture with composite synapse of the spin Hall effect-driven magnetic tunnel junction (SHE-MTJ) and capacitive memory bit cell to mimic the behavior of biological synapses. This STM-LTM platform realizes the memory potentiation through a continual update process using STM-to-LTM transfer, which is applied to neural networks based on the established capacitive crossbar. We then propose a hardware-enabled and customized STM-LTM transition algorithm for the platform considering the real hardware parameters. We validate the functionality of the design using SPICE simulations that show the proposed synapse has the potential of reaching ~30.2-pJ energy consumption for STM-to-LTM transfer and 65 pJ during STM programming. We further analyze the correlation between energy, array size, and STM-to-LTM threshold utilizing the MNIST data set.

An Efficient Software Stack Sphere Decoder for Polar Codes

Proved to achieve the symmetric capacity of the binary-input discrete memoryless channels, polar codes have been chosen for the eMBB control channels in the 5th generation mobile communication systems. Besides the main decoding algorithms like successive cancellation (SC) decoding and CRC-aid SC list (CA-SCL) decoding, sphere decoder (SD) and list SD (LSD) are the alternatives for short codes with less required memory bits. Existing SD and LSD attain high calculation complexity, for SD requires a back-tracking process and LSD needs a large list size $L$ to achieve satisfying performance. To reduce complexity, an efficient software stack sphere decoder (ESSD) based on the synchronous determination is firstly proposed in this article. With the dynamic set-by-set decoding in the stack structure, it achieves the lowest complexity in SD-based decoders (SD/LSD/ESSD) while sharing the same performance on low-rate codes and high-rate codes. Compared with the CA-SCL decoder, the complexity and latency of the proposed ESSD are also competitive at high signal-to-noise-ratio on the displayed codes. Implemented on C++ , the proposed ESSD reduces $\text{44.77}\%$ latency compared with CA-SCL-32 for $\mathcal {P}(128,120)$ at the BER of $10^{-5}$ with $E_b/N_0 = \text{7}$ dB.

RETRACTED: Efficient soft error resiliency by multi-match packet classification using scalable TCAM implementation in FPGA

Ternary content addressable memories (TCAMs) are generally utilized for system gadgets to actualize parcel characterization. They are utilized, for instance, for bundle sending, for security, and to actualize programming characterized systems (SDNs). TCAMs are normally executed as independent gadgets or as a protected innovation obstruct that is coordinated on systems administration application-explicit incorporated circuits. Then again, field-programmable entryway exhibits (FPGAs) excluding TCAM squares. Be that as it may, the adaptability of FPGAs impacts in alluring for SDN usage, and majority of field programmable gate array merchants give improvement packs to SDN. By considering implementation of TCAM in FPGA and, hence, there is an importance to imitate TCAMs utilizing the rationale squares possible to be reached in the FPGA. Lately, various plans to imitate TCAMs on FPGAs have been devised. Least among them exploit the major of memory squares accessible into the inner part of present day FPGAs to utilize them to execute TCAMs. An issue when utilizing recollections is that those squares will be influenced by delicate blunders that degenerate the put away bits. The recollections can be secured with an equality test to distinguish blunders or with a mistake redress code to address them, yet it needs extra bits of memory for each word. Regarding the above concise, the insurance of the recollections used to imitate new TCAM has been implemented. Specifically, it is appeared by abusing the way that just a subset of the conceivable memory substance are legitimate, most single-piece blunders can be redressed when the recollections are ensured with an equality bit.

Optimization of n-MOS 6T Nanowire SRAM Bit Cell Based on Nanowires Ratio of SiNWTs

In nowadays technology, the primary memory structure widely used in many digital circuit applications is a six transistor (6T) Static Random Access Memory (SRAM) bit cell. The main reason for minimizing memory bit cell to nanodimensions is to provide the SRAM integrated circuits (ICs) with the possible largest memory size per one chip, and the main unit in 6T SRAM bit cell is the MOSFET. One of the new MOSFET structures that overcome conventional MOSFET structure problems under minimization towards nanodimension is the silicon nanowire transistor (SiNWT). This study is the first to explore and optimize the nanowire ratio of driver to load (KD/KL) for a six n-channel SiNWT-based SRAM bit cell. The MuGFET simulation tool has been used to calculate the output characteristics of each transistor individually, and then these characteristics are implemented in the MATLAB software to produce the final static butterfly and current characteristics of nanowire 6T-SRAM bit cell. The demonstration of the driver to load transistors’ nanowires ratio optimizations of nanoscale n-type SiNWT-based SRAM bit cell has been discussed. In this research, the optimization of KD/KL will strongly depend on inflection voltage and high and low noise margins (NMs) of butterfly characteristics. The improvement of NMs of butterfly characteristics has been done by increasing the drain current (Ids) of the driver transistor. Also, the optimization in principle will depend on whether NMs are equal and high, and the inflection voltage (Vinf) is near to Vdd/2 values as possible. These principles have been used as limiting factors for optimization. The results show that the optimization strongly depends on the nanowire ratio, and the best ratio was KD/KL 4. The increase in KD/KL leads to a continuous increase in NMH, acceptable NML and low percentage increment of static power consumption (ΔP %) at KD/KL 4.

Strain-mediated electric manipulation of magnetic skyrmion and other topological states in geometric confined nanodiscs

Magnetic skyrmions in multilayer stack structures are promising magnetic memory bits for applications in race-track storage devices or random-access memories. For practical implementation in energy efficient memory devices, it is essential to achieve a deterministic switch of skyrmion states, e.g. nucleation and elimination, triggered by electric fields. In this work, by means of micromagnetic simulation, we demonstrate the strain-mediated electric field driven switching of magnetic skyrmion and other topological states without the presence of a magnetic field in a proposed device consisting of nanodiscs of trilayer Pt/Co/Ta stacks on a piezoelectric substrate. It is revealed that the multiple magnetic state switching behaviors, including the nucleation and elimination of skyrmion or labyrinth stripe domain states, as well as topological transitions between skyrmion, vortex, skyrmionium and vertical single domain states, can be triggered by applying an external electric field mediated by strains. The corresponding critical strains and their dependence on the geometric parameters of the nanodiscs (e.g. size and number of stacks) for triggering such magnetic switching are also explored. The stability of these topological domain states and possible switching behaviors (e.g. volatile and non-volatile) between the different states are discussed as well. The capability for controlled switching of these topological states provides a new pathway to energy efficient high-density magnetoelectric memory and logic devices.

Tight Bounds for Undirected Graph Exploration with Pebbles and Multiple Agents

We study the problem of deterministically exploring an undirected and initially unknown graph with n vertices either by a single agent equipped with a set of pebbles or by a set of collaborating agents. The vertices of the graph are unlabeled and cannot be distinguished by the agents, but the edges incident to a vertex have locally distinct labels. The graph is explored when all vertices have been visited by at least one agent. In this setting, it is known that for a single agent without pebbles Θ(log n ) bits of memory are necessary and sufficient to explore any graph with at most n vertices. We are interested in how the memory requirement decreases as the agent may mark vertices by dropping and retrieving distinguishable pebbles or when multiple agents jointly explore the graph. We give tight results for both questions showing that for a single agent with constant memory Θ(log log n ) pebbles are necessary and sufficient for exploration. We further prove that using collaborating agents instead of pebbles does not help as Θ(log log n ) agents with constant memory each are necessary and sufficient for exploration. For the upper bounds, we devise an algorithm for a single agent with constant memory that explores any n -vertex graph using O (log log n ) pebbles, even when n is not known a priori . The algorithm terminates after polynomial time and returns to the starting vertex. We further show that the algorithm can be realized with additional constant-memory agents rather than pebbles, implying that O (log log n ) agents with constant memory can explore any n -vertex graph. For the lower bound, we show that the number of agents needed for exploring any graph with at most n vertices is already Ω(log log n ) when we allow each agent to have at most O ((log n ) 1 -ε) bits of memory for any ε &gt; 0. Our argument also implies that a single agent with sublogarithmic memory needs Θ(log log n ) pebbles to explore any n -vertex graph.

Memway: in-memorywaylaying acceleration for practical rowhammer attacks against binaries

The Rowhammer bug is a novel micro-architectural security threat, enabling powerful privilege-escalation attacks on various mainstream platforms. It works by actively flipping bits in Dynamic Random Access Memory (DRAM) cells with unprivileged instructions. In order to set up Rowhammer against binaries in the Linux page cache, the Waylaying algorithm has previously been proposed. The Waylaying method stealthily relocates binaries onto exploitable physical addresses without exhausting system memory. However, the proof-of-concept Waylaying algorithm can be easily detected during page cache eviction because of its high disk I/O overhead and long running time. This paper proposes the more advanced Memway algorithm, which improves on Waylaying in terms of both I/O overhead and speed. Running time and disk I/O overhead are reduced by 90% by utilizing Linux tmpfs and inmemory swapping to manage eviction files. Furthermore, by combining Memway with the unprivileged posix fadvise API, the binary relocation step is made 100 times faster. Equipped with our Memway+fadvise relocation scheme, we demonstrate practical Rowhammer attacks that take only 15-200 minutes to covertly relocate a victim binary, and less than 3 seconds to flip the target instruction bit.

Electric field-controlled crossover effect in oxygen-deficient titanium-oxide memory bits

In this letter, we report an unusual crossover in the current-voltage characteristics of forming-free titanium oxide-based memory bits. The voltage at which crossover between high and low resistance states take place, Vcr gradually shifts to lower bias values with either decreasing sweeping rates, increasing maximum scan voltage or increasing current compliance. Interestingly, the crossover effect is not pronounced for reduced-oxide based memory bits. The mechanism behind these changes in the I-V curves is discussed.

Non Volatile Low Power Wake up Radio Transceiver for Wireless Sensor Network

Wireless sensor nodes consume lots of energy during communication but huge power consumption has been observed during active listening in idle mode as source nodes can start data transmission at any time. Power saving can be achieved by establishing synchronization among end nodes. Many rendezvous solutions are available and out of which wake up receiver found extremely adroit. A non volatile wake up transceiver has been proposed in the present paper that works on the basis of ID matching. State of art using 4GB of memory to remember states of sensor nodes while proposed technique used only 60 bits of memory with very less false alarm probability. Power consumption for proposed model is only 59.47 nW. Hence this model is quite effective in terms of power consumption and memory usage as compared to trailing models.

Adaptive 2-D Scheduling-Based Nonbinary Majority-Logic Decoding for NAND Flash Memory

This brief presents a nonbinary adaptive 2D scheduling-based majority logic decoding (NB-ATS-MLGD) algorithm for NAND flash memory. The proposed algorithms provide considerable tradeoff between error-correcting capability and decoding complexity, and make the NB-MLGD decoding more attractive for practical purposes in the multi-level cells (MLC) NAND flash memory. The most significant feature of the proposed NB-ATS-MLGD algorithm is the 2D layered scheduling strategy, where the decoding orders of check nodes (CNs) and variable nodes (VNs) are both adaptive. By leveraging on the MLC flash memory bit error patterns, an early-correcting (EC) criterion is incorporated into the NB-ATS-MLGD algorithm. Furthermore, the simplification and parallelization of proposed algorithms make them more practical in NAND flash memory. Simulation results show that the proposed algorithms increase the lifetime of MLC flash memory up to 3000 program-and-erase (PE) cycles and have desirable convergence speed compared with the conventional non-binary MLGD algorithm. When at low PE cycles, the NB-EC-ATS-MLGD algorithm improves frame error rate (FER) performance by more than 3 order of magnitudes compared with the conventional non-binary MLGD algorithm.