Memory-based Computing Research Articles

A Parallel Multiobjective PSO Weighted Average Clustering Algorithm Based on Apache Spark

Multiobjective clustering algorithm using particle swarm optimization has been applied successfully in some applications. However, existing algorithms are implemented on a single machine and cannot be directly parallelized on a cluster, which makes it difficult for existing algorithms to handle large-scale data. With the development of distributed parallel computing framework, data parallelism was proposed. However, the increase in parallelism will lead to the problem of unbalanced data distribution affecting the clustering effect. In this paper, we propose a parallel multiobjective PSO weighted average clustering algorithm based on apache Spark (Spark-MOPSO-Avg). First, the entire data set is divided into multiple partitions and cached in memory using the distributed parallel and memory-based computing of Apache Spark. The local fitness value of the particle is calculated in parallel according to the data in the partition. After the calculation is completed, only particle information is transmitted, and there is no need to transmit a large number of data objects between each node, reducing the communication of data in the network and thus effectively reducing the algorithm's running time. Second, a weighted average calculation of the local fitness values is performed to improve the problem of unbalanced data distribution affecting the results. Experimental results show that the Spark-MOPSO-Avg algorithm achieves lower information loss under data parallelism, losing about 1% to 9% accuracy, but can effectively reduce the algorithm time overhead. It shows good execution efficiency and parallel computing capability under the Spark distributed cluster.

LocationSpark: In-memory Distributed Spatial Query Processing and Optimization.

Due to the ubiquity of spatial data applications and the large amounts of spatial data that these applications generate and process, there is a pressing need for scalable spatial query processing. In this paper, we present new techniques for spatial query processing and optimization in an in-memory and distributed setup to address scalability. More specifically, we introduce new techniques for handling query skew that commonly happens in practice, and minimizes communication costs accordingly. We propose a distributed query scheduler that uses a new cost model to minimize the cost of spatial query processing. The scheduler generates query execution plans that minimize the effect of query skew. The query scheduler utilizes new spatial indexing techniques based on bitmap filters to forward queries to the appropriate local nodes. Each local computation node is responsible for optimizing and selecting its best local query execution plan based on the indexes and the nature of the spatial queries in that node. All the proposed spatial query processing and optimization techniques are prototyped inside Spark, a distributed memory-based computation system. Our prototype system is termed LocationSpark. The experimental study is based on real datasets and demonstrates that LocationSpark can enhance distributed spatial query processing by up to an order of magnitude over existing in-memory and distributed spatial systems.

Analog Memristive CAMs for Area- and Energy-Efficient Reconfigurable Computing

Memory-based reconfigurable computing rose to outperform conventional FPGAs in logic function density, as well as being less impacted by the programmable interconnection. However, the major drawback is that the area and power overheads are significant, and this gets worse in high-density, high-performance Memory-based Computing (MBC) devices. In this brief, we investigate the usage of analog memristive CAMs to improve the area density of MBCs, thus enabling denser memories and smaller power consumption. Simulation results indicate significant area and energy savings, up to $2.2\times $ and $2.6\times $ , respectively, compared to the non-volatile counterparts, at the cost of increasing latency by up to 20%.

Resistive CAM Acceleration for Tunable Approximate Computing

The Internet of Things significantly increases the amount of data generated, straining the processing capability of current computing systems. Approximate computing is a promising solution to accelerate computation by trading off energy and accuracy. In this paper, we propose a resistive content addressable memory (CAM) accelerator, called RCA, which exploits data locality to have an approximate memory-based computation. RCA stores high frequency patterns and performs computation inside CAM without using processing cores. During execution time, RCA searches an input operand among all prestored values on a CAM and returns the row with the nearest distance. To manage accuracy, we use a distance metric which considers the impact of each bit indices on computation accuracy. We evaluate an application of proposed RCA on CPU approximation, where RCA can be used as a stand-alone or as a hybrid computing unit besides CPU cores for tunable CPU approximation. We evaluate the architecture of the proposed RCA using HSPICE and multi2sim by testing our results on x86 CPU processor. Our evaluation shows that RCA can accelerate CPU computation by 12.6× and improve the energy efficiency by 6.6× as compared to a traditional CPU architecture, while providing acceptable quality of service.

Networked Power-Gated MRAMs for Memory-Based Computing

Emerging nonvolatile memory technologies open new perspectives for original computing architectures. In this paper, we propose a new type of flexible and energy-efficient architecture that relies on power-gated distributed magnetoresistive random access memory (MRAM). The proposed architecture uses a network-on-chip (NoC) to interconnect MRAM-based clusters, processing elements, and managers. The NoC distributes application-specific commands to MRAM devices by means of packets. Configurable network interfaces allow to transform MRAM devices into smart units able to respond to incoming commands. In this context, three types of MRAM designs are proposed with different power-gating policies and granularities. A relevant database search engine case study is considered to illustrate the benefits of this proposed architecture. It is implemented with a sparse-neural-network approach and simulated in SystemC with different scenarios including hundreds of database queries. Hardware designs and accurate power estimations have been conducted. The obtained results demonstrate important power reduction with database hit rates of about 94%. Targeting 65-nm technology, energy savings reach 87% when compared with an static random access memory-based implementation. Moreover, a new asymmetric read/write MRAM type provides from 39% to 50% energy reduction with respect to the other fixed-granularity models. This results in a low-power, highly scalable, and configurable implementation of memory-based computing.

Machine Learning with PySpark - Review

<p>A reasonable distributed memory-based Computing system for machine learning is Apache Spark. Spark is being superior in computing when compared with Hadoop. Apache Spark is a quick, simple to use for handling big data that has worked in modules of Machine Learning, streaming SQL, and graph processing. We can apply machine learning algorithms to big data easily, which makes it simple by using Spark and its machine learning library MLlib, even this can be made simpler by using the Python API PySpark. This paper presents the study on how to develop machine learning algorithms in PySpark. </p>

Guest Editorial for the Special Section on Emerging Computational Paradigms

The seven papers in this special section focus on memory-based computing and 3D stacked hybrid memory architectures, on many-core neuromorphic platforms and clustered many-core accelerators, on emerging technologies for on-chip interconnects and signal reconstruction algorithms running on a heterogeneous mobile SoC and on the efficient parallelization of GPU primitives.

Emerging Trends in Design and Applications of Memory-Based Computing and Content-Addressable Memories

Content-addressable memory (CAM) and associative memory (AM) are types of storage structures that allow searching by content as opposed to searching by address. Such memory structures are used in diverse applications ranging from branch prediction in a processor to complex pattern recognition. In this paper, we review the emerging challenges and opportunities in implementing different varieties of CAM/AM structures. Beyond-CMOS silicon and nonsilicon memory technologies hold significant promise in implementing dense, fast, and energy-efficient CAM/AM structures. We describe circuit/architecture level implementations of CAM/AM using these technologies, as well as novel applications in different domains, including informatics, text analytics, data mining, and reconfigurable computing platforms.

Exploring Spin Transfer Torque Devices for Unconventional Computing

This paper reviews the potential of spin-transfer torque devices as an alternative to complementary metal–oxide–semiconductor for non-von Neumann and non-Boolean computing. Recent experiments on spin-transfer torque devices have demonstrated high-speed magnetization switching of nanoscale magnets with small current densities. Coupled with other properties, such as nonvolatility, zero leakage current, high integration density, we discuss that the spin-transfer torque devices can be inherently suitable for some unconventional computing models for information processing. We review several spintronic devices in which magnetization can be manipulated by current induced spin transfer torque and explore their applications in neuromorphic computing and reconfigurable memory-based computing.

Utility Mining Algorithm for High Utility Item sets from Transactional Databases

The discovery of item sets with high utility like profits is referred by mining high utility item sets from a transactional database. Although in recent years a number of relevant algorithms have been proposed, for high utility item sets the problem of producing a large number of candidate item sets is incurred. The mining performance is degraded by such a large number of candidate item sets in terms of execution time and space requirement. When the database contains lots of long transactions or long high utility item sets the situation may become worse. Internet purchasing and transactions is increased in recent years, mining of high utility item sets especially from the big transactional databases is required task to process many day to day operations in quick time. There are many methods presented for mining the high utility item sets from large transactional datasets are subjected to some serious limitations such as performance of this methods needs to be investigated in low memory based systems for mining high utility itemsets from large transactional datasets and hence needs to address further as well. Another limitation is these proposed methods cannot overcome the screenings as well as overhead of null transactions; hence, performance degrades drastically. During this paper, we are presenting the new approach to overcome these limitations. We presented distributed programming model for mining business-oriented transactional datasets by using an improved Map Reduce framework on Hadoop, which overcomes not only the single processor and main memory-based computing, but also highly scalable in terms of increasing database size. We have used this approach with existing UP-Growth and UP-Growth+ with aim of improving their performances further. In experimental studies we will compare the performances of existing algorithms UP-Growth and UP-Growth+ against the improve UP-Growth and UP-Growth+ with Hadoop.

An Efficient Distributed Programming Model for Mining Useful Patterns in Big Datasets

Mining combined association rules with correlation and market basket analysis can discover customer’s buying purchase rules along with frequently correlated, associated-correlated, and independent patterns synchronously which are extraordinarily useful for making everyday’s business decisions. However, due to the main memory bottleneck in single computing system, existing approaches fail to handle big datasets. Moreover, most of them cannot overcome the screenings and overhead of null transactions; hence, performance degrades drastically. In this paper, considering these limitations, we propose a distributed programming model for mining business-oriented transactional datasets by using an improved MapReduce framework on Hadoop, which overcomes not only the single processor and main memory-based computing, but also highly scalable in terms of increasing database size. Experimental results show that the technique proposed and developed in this paper are feasible for mining big transactional datasets in terms of time and scalability.

Analysis and Modeling of Internal State Variables for Dynamic Effects of Nonvolatile Memory Devices

Hybrid integration of CMOS and nonvolatile memory (NVM) devices has become the foundation for emerging nonvolatile memory-based computing. The primary challenge to validate hybrid memory system with both CMOS and NVM devices is to develop a SPICE-like simulator that can simulate the dynamic behavior accurately and efficiently. Since memristor, spin-transfer-toque magnetic-tunneling-junction (STT-MTJ) and phase-change-memory (PCM) devices are the most promising candidates of next generation of NVM devices, it is under great interest in including these new devices in the standard CMOS design flow. The previous approaches either ignore dynamic effect without consideration of internal states for dynamic behavior, or need complex equivalent circuits to represent those devices. This paper proposes a new modified nodal analysis for NVM devices with identified internal state variables for dynamic behavior. As such, compact SPICE-like implementation can be derived for all three new NVM devices in the design of large-scale memory circuits. As demonstrated by a number of examples on hybrid memory circuits with both CMOS and NVM devices, our newly developed SPICE-like simulator can capture dynamic behaviors of memristor, STT-MTJ and PCM devices, and can also reduce CPU runtime by 20-69 times when compared to the previous equivalent circuit based approaches.

A Scalable Memory-Based Reconfigurable Computing Framework for Nanoscale Crossbar

Nanoscale molecular electronic devices amenable to bottom-up self-assembly into a crossbar structure have emerged as a promising candidate for future electronic systems. To address some of the design challenges in molecular crossbar, we propose “memory-based architecture for reconfigurable computing” (MBARC), where memory, instead of switch-based logic functions, is used as the computing element. MBARC leverages on the fact that regular and periodic structures of molecular crossbar are attractive for a dense memory design. The main idea in MBARC is to partition a logic circuit, store the partitions as multi-input-multi-output lookup tables in a memory array, and then, use a simple CMOS-based scheduler to evaluate the partitions in a topological time-multiplexed manner. Compared to existing reconfigurable nanocomputing models, the proposed memory-based computing has three major advantages: 1) it minimizes the requirement of programmable interconnects (PIs); 2) it minimizes the number of CMOS interfacing elements that are required for level restoration and cascading logic blocks; and 3) it can achieve higher defect tolerance through efficient use of redundancy. Simulation results for a set of ISCAS benchmarks show average improvement of 32% in area, 21% in delay, and 34% in energy per vector compared to the implementation of a nanoscale field-programmable gate array. Effectiveness of the framework is also studied for two large sequential circuits, namely, 2-D discrete cosine transform and eight-tap finite-impulse-response filter.

LUT Optimization for Memory-Based Computation

Recently, we have proposed the antisymmetric product coding (APC) and odd-multiple-storage (OMS) techniques for lookup-table (LUT) design for memory-based multipliers to be used in digital signal processing applications. Each of these techniques results in the reduction of the LUT size by a factor of two. In this brief, we present a different form of APC and a modified OMS scheme, in order to combine them for efficient memory-based multiplication. The proposed combined approach provides a reduction in LUT size to one-fourth of the conventional LUT. We have also suggested a simple technique for selective sign reversal to be used in the proposed design. It is shown that the proposed LUT design for small input sizes can be used for efficient implementation of high-precision multiplication by input operand decomposition. It is found that the proposed LUT-based multiplier involves comparable area and time complexity for a word size of 8 bits, but for higher word sizes, it involves significantly less area and less multiplication time than the canonical-signed-digit (CSD)-based multipliers. For 16- and 32-bit word sizes, respectively, it offers more than 30% and 50% of saving in area-delay product over the corresponding CSD multipliers.

APL descriptions of functional building blocks for connectionist computer models

APL functions provide concise, array-oriented expressions for describing connection-based computing. These give insights into a variety of neural network-like computer models. Functional decomposition into inherently parallel operation of collective or memory-based computing is effected with the identification of several command-like APL simulation functions.These functions serve to: (a) generate and configure initial values and structures for network layers, connection weights and thresholds, (b) strategically sample training sets to provide acyclic sequences of patterns, (c) update weights for memorizing or learning from the training set, (d) locate units effective for storing and retrieving memories, and (e) use a cue or noise-corrupted pattern for recalling or reconstructing memory associations established during training. Also, APL functions are used to accomodate for data values missing from the training patterns. Other simply described functions generate random fixed reference addresses and initialize modifiable weight values. Test patterns with specified levels of noise contamination are generated by simple APL expressions.