Memory Allocation Research Articles

An efficient method for simulating fluctuating wind speed fields in two-spatial dimensions based on a frequency-dependent acceptance-rejection scheme

The simulation of fluctuating wind speed fields holds paramount importance in the wind-resistant design of significant structures such as high-rise buildings, long-span bridges, and wind turbines. To address the computational challenges posed by the original spectral representation method (SRM), a novel approach has emerged. This approach, rooted in the frequency-wavenumber spectrum (FWS), offers a solution to the complexities associated with the original SRM. An enhanced non-uniform discrete technique based on the acceptance-rejection (A-R) criterion was introduced to improve the efficiency of the FWS-based SRM. Nonetheless, this technique currently faces certain constrains, including its demand for a substantial allocation of random access memory (RAM) and its inability to be seamlessly integrated with the fast Fourier transform (FFT) algorithm. Given this scenario, a notably more effective strategy for selecting representative points emerges -the frequency-dependent acceptance-rejection (A-R) scheme. This innovative scheme holds the advantage of diminishing RAM utilization, transforming wind field modeling from a supercomputers-exclusive task to one feasible on personal computers. Moreover, its seamless integration with FFT technology bolsters simulation efficiency. The provided numerical simulation instances of two-spatial dimensional fluctuating wind speed fields underscore the proficiency of this proposed frequency-dependent A-R scheme. The outcomes demonstrated the combined A-R and FFT technique’s efficiency and precision, in simulating two-spatial dimensions fluctuating wind speed fields.

Memory Allocation Strategy in Edge Programmable Logic Controllers Based on Dynamic Programming and Fixed-Size Allocation

With the explosive growth of data at the edge in the Industrial Internet of Things (IIoT), edge devices are increasingly performing more data processing tasks to alleviate the load on cloud servers. To achieve this goal, Programmable Logic Controllers (PLCs) are gradually transitioning into edge PLCs. However, efficiently executing a large number of computational tasks in memory-limited edge PLCs is a significant challenge. Therefore, there is a need to design an efficient memory allocation strategy for edge PLCs. This paper proposes a dynamic memory allocation strategy for edge PLCs. It adopts an approach of organizing memory into small blocks to handle memory requests from real-time tasks and utilizes a well-performing dynamic programming method for resource allocation problems to handle memory requests from non-real-time tasks. This approach ensures real-time performance while improving the efficiency of non-real-time task processing. In the simulation experiments, the algorithm implemented based on this allocation strategy is compared with the default method and several open-source memory allocators. The experimental results demonstrate that the proposed algorithm, on average, improves the speed of real-time task processing by 13.7% and achieves a maximum speed improvement of 17.0% for non-real-time task processing. The experimental results show that the allocation strategy effectively improves memory allocation efficiency in memory-limited environments.

Memory aware optimized Hadoop MapReduce model in cloud computing environment

<p>In the last decade, data analysis has become one of the popular tasks due to enormous growth in data every minute through different applications and instruments. MapReduce is the most popular programming model for data processing. Hadoop constitutes two basic models i.e., Hadoop file system (HDFS) and MapReduce, Hadoop is used for processing a huge amount of data whereas MapReduce is used for data processing. Hadoop MapReduce is one of the best platforms for processing huge data in an efficient manner such as processing web logs data. However, existing model This research work proposes memory aware optimized Hadoop MapReduce (MA-OHMR). MA-OHMR is developed considering memory as the constraint and prioritizes memory allocation and revocation in mapping, shuffling, and reducing, this further enhances the job of mapping and reducing. Optimal memory management and I/O operation are carried out to use the resource inefficiently manner. The model utilizes the global memory management to avoid garbage collection and MA-OHMR is optimized on the makespan front to reduce the same. MA-OHMR is evaluated considering two datasets i.e., simple workload of Wikipedia dataset and complex workload of sensor dataset considering makespan and cost as an evaluation parameter.</p>

AutoMap: Automatic Mapping of Neural Networks to Deep Learning Accelerators for Edge Devices

Emerging deep neural networks (DNNs) have been emerging in applications (object detection, automatic speech recognition, etc.) deployed on edge devices. To improve the energy efficiency of edge devices, domain specific deep learning accelerators (DLAs) are designed with limited on-chip resources. The manifold DLA designs and evolving DNN topologies bring challenges for applications mapping and scheduling on hardware resources. In this paper, we propose an automatic DNN mapping framework named AutoMap given the hardware backend information. Firstly, a computational graph representation called Extended Directed Weighted Graph (EDWG) is proposed, which realizes unified expression for both spatial and temporal network inter-layer connections. Secondly, an associated partitioner is implemented for splitting an EDWG into subEDWGs, which incorporates the on-chip memory constraint and facilitates weight data reuse on chip. Lastly, a dynamic memory allocation strategy is utilized to alleviate the feature storing burden introduced by the multivarious network sizes and connections. Compared to the baseline mapping methods, experimental results show that our proposed automatic mapping framework can help to speedup the execution of several DNNs on state-of-the-art DLAs, ranging from 1.27x to 3.45x. The utilization of the PE array can increase from 20% to 64%.

Optimal FPGA memory allocation for image processing

In the field of computer vision, Field Programmable Gate Array (FGPA) limited de on-chip memory is difficult to meet the power, size and other requirements. To address this phenomenon, the study constructs a partitioning algorithm to achieve a balance between energy consumption and resource utilisation based on the analysis of memory resource allocation, overall power consumption and resource utilisation from the perspective of image processing technology. The power consumption of the balancing algorithm is lower compared to the optimised utilisation algorithm HLS tool, with both Block Ramdom Access Memory (BRAM) power consumption taking the value of 0.005; the dynamic power consumption takes the value range of 0.014–0.082. Compared to the High Level Synthesis (HLS) tool, the overall power consumption of the balancing algorithm and the optimised utilisation algorithm is significantly lower, with the values of 0.251 and 0.252 respectively, both with a reduction rate of approximately 30%. The accuracy rate of the proposed memory optimisation allocation algorithm is the highest among the four memory optimisation allocation algorithms and strategies on all three types of target scales. FPGA memory optimisation allocation strategy can guarantee to have lower power consumption while satisfying the same resource occupancy, and the model has in-depth application value in visual image vision technology.

Wear-leveling-aware buddy-like memory allocator for persistent memory file systems

Existing persistent memory file systems usually ignore the problem that persistent memories (PMs) have limited write endurance. Then the underlying PMs can be damaged easily by the unbalanced writes of file systems. However, existing wear-leveling-aware space management techniques mainly focus on providing higher-balanced writes to PMs rather than reducing the overhead, which can lead to serious performance degradation of persistent memory file systems. In this paper, we propose an efficient wear-leveling-aware buddy-like memory allocator, called WBAlloc, to achieve a higher-accuracy wear-leveling of PM while improving the performance of persistent memory file systems. Like the buddy memory allocator, WBAlloc adopts a multi-level allocator to manage the unused space of PM, and each allocator represents a range of allocation granularity, which can achieve O(1) time complexity in both allocation and deallocation. We implement the proposed WBAlloc in the Linux kernel based on NOVA, a typical persistent memory file system. Compared with original NOVA, DWARM, and WMAlloc (DWARM and WMAlloc are the state-of-the-art wear-leveling-aware allocators of persistent memory file systems), the experimental results show that the proposed WBAlloc can achieve 26.23%, 80.46%, 15.61% performance improvement while reducing the maximum writes by up to 338.88%, 159.28%, and 29.45% on average, respectively.

Smart Approaches for Evaluating Photosynthetically Active Radiation at Various Stations Based on MSG Prime Satellite Imagery

Photosynthetically active radiation (PAR) is the 400–700 nm portion of the solar radiation spectrum that photoautotrophic organisms including plants, algae, and cyanobacteria use for photosynthesis. PAR is a key variable in global ecosystem and Earth system modeling, playing a prominent role in carbon and water cycling. Alongside air temperature, water availability, and atmospheric CO2 concentration, PAR controls photosynthesis and consequently biomass productivity in general. The management of agricultural and horticultural crops, forests, grasslands, and even grasses at sports venues is a non-exhaustive list of applications for which an accurate knowledge of the PAR resource is desirable. Modern agrivoltaic systems also require a good knowledge of PAR in conjunction with the variables needed to monitor the co-located photovoltaic system. In situ quality-controlled PAR sensors provide high-quality information for specific locations. However, due to associated installation and maintenance costs, such high-quality data are relatively scarce and generally extend over a restricted and sometimes non-continuous period. Numerous studies have already demonstrated the potential offered by surface radiation estimates based on satellite information as reliable alternatives to in situ measurements. The accuracy of these estimations is site-dependent and is related, for example, to the local climate, landscape, and viewing angle of the satellite. To assess the accuracy of PAR satellite models, we inter-compared 11 methods for estimating 30 min surface PAR based on satellite-derived estimations at 33 ground-based station locations over several climate regions in Europe, Africa, and South America. Averaged across stations, the results showed average relative biases (relative to the measurement mean) across methods of 1 to 20%, an average relative standard deviation of 25 to 30%, an average relative root mean square error of 25% to 35% and a correlation coefficient always above 0.95 for all methods. Improved performance was seen for all methods at relatively cloud-free sites, and quality degraded towards the edge of the Meteosat Second Generation viewing area. A good compromise between computational time, memory allocation, and performance was achieved for most locations using the Jacovides coefficient applied to the global horizontal irradiance from HelioClim-3 or the CAMS Radiation Service. In conclusion, satellite estimations can provide a reliable alternative estimation of ground-based PAR for most applications.

Deep Learning Enhanced Volumetric Photoacoustic Imaging of Vasculature in Human.

The development of high-performance imaging processing algorithms is a core area of photoacoustic tomography. While various deep learning based image processing techniques have been developed in the area, their applications in 3D imaging are still limited due to challenges in computational cost and memory allocation. To address those limitations, this work implements a 3D fully-dense (3DFD) U-net to linear array based photoacoustic tomography and utilizes volumetric simulation and mixed precision training to increase efficiency and training size. Through numerical simulation, phantom imaging, and in vivo experiments, this work demonstrates that the trained network restores the true object size, reduces the noise level and artifacts, improves the contrast at deep regions, and reveals vessels subject to limited view distortion. With these enhancements, 3DFD U-net successfully produces clear 3D vascular images of the palm, arms, breasts, and feet of human subjects. These enhanced vascular images offer improved capabilities for biometric identification, foot ulcer evaluation, and breast cancer imaging. These results indicate that the new algorithm will have a significant impact on preclinical and clinical photoacoustic tomography.

Operand-Oriented Virtual Memory Support for Near-Memory Processing

Virtual memory support is one of the major challenges of near-memory processing (NMP). Many previous works focused on this issue, but there are practical limitations that conventional CPU hardware or memory allocation schemes should be modified. Another technique uses a specialized page table for NMP to avoid such limitations. However, the previous work proposed NMP-specific page table that has static page table walk latency regardless of data size. This causes unnecessarily long address translation time for relatively small data. In this paper, we propose an operand-oriented technique for virtual memory support. Our scheme does not pre-determine the size of shared space; rather, it allocates shared space depending on the size of operands data for NMP. Then, we significantly reduce page table walk latency by using our flexible page table, which adapts the page table hierarchy to the size of shared spaces. To prove our concept, we implement our scheme in a full-system simulator and an FPGA-based verification platform. We then compared it with CPU's page table and the previous NMP-specific page table. The experimental results show that our technique outperforms page table walk latency by 69.3 percent and 43.8 percent compared to the CPU's page table and the comparison, respectively.

Operating System Support-Based Prevention Mechanism for Use-After-Free Attacks on the Glibc Memory Allocator

Operating System Support-Based Prevention Mechanism for Use-After-Free Attacks on the Glibc Memory Allocator

Analysis of Public Opinion on the Impact of the Implementation of Community Activity Restrictions (PPKM) During the Covid-19 Pandemic Using Long Short Term Memory and Latent Dirichlet Allocation

Technology social is the fastest and most up-to-date source of information. A model that can provide mapping will help in sorting out information more precisely and quickly. Public opinion in the mass media always develops quickly to talk about an issue in just a few days or even hours, so we do not know what the opinions of the people in the mass media are on the issue. In this study, the author applied topic modeling to the results of sentiment analysis on PPKM. The source of data in this study was obtained from twitter using SNScrape. The collected data was analyzed sentiment using the Long Short-term Memory (LSTM) method, so that public opinion was obtained with positive, negative, and neutral sentiments. The classification obtained from the results of the sentiment analysis process is continued with the topic modeling process using the Latent Dirichlet Allocation (LDA) method and visualized in the form of a wordcloud to find out the relationship between one topic and another. The sentiment analysis process produces a model with an accuracy rate of 90.8% and the topic modeling process successfully presents topics that are easy to interpret so that conclusions can be known about an issue.

A dimensionality reduction approach for convolutional neural networks

The focus of this work is on the application of classical Model Order Reduction techniques, such as Active Subspaces and Proper Orthogonal Decomposition, to Deep Neural Networks. We propose a generic methodology to reduce the number of layers in a pre-trained network by combining the aforementioned techniques for dimensionality reduction with input-output mappings, such as Polynomial Chaos Expansion and Feedforward Neural Networks. The motivation behind compressing the architecture of an existing Convolutional Neural Network arises from its usage in embedded systems with specific storage constraints. The conducted numerical tests demonstrate that the resulting reduced networks can achieve a level of accuracy comparable to the original Convolutional Neural Network being examined, while also saving memory allocation. Our primary emphasis lies in the field of image recognition, where we tested our methodology using VGG-16 and ResNet-110 architectures against three different datasets: CIFAR-10, CIFAR-100, and a custom dataset.

What you can read is what you can't execute

Due to the address space layout randomization (ASLR), code reuse attacks (CRAs) require memory probes to get available gadgets. Code reading is the basic way to obtain code information. In theory, setting the code to be unreadable can prevent code reading. However, the pages are loaded dynamically, and the existing methods cannot set all code as unreadable at one time. They can only control code permissions page-by-page via time-consuming page tracking. Moreover, since some special users need to read code, turning off the read permission will affect their execution. To solve these problems, this paper proposes a method AntiRead. It rebuilds the buddy system for memory allocation. The new buddy system places code pages in a specific memory pool to manage their read permissions. In the presence of AntiRead, what is obtained by adversaries through code reading is either randomized code or non-executable code. Experiments and analysis show that AntiRead can prevent the code that has been read from being used as gadgets without affecting the normal code reading. In addition, the CPU overhead introduced by AntiRead is 1.8%.

Video saliency-detection using custom spatiotemporal fusion method

There have been several researches done in the field of image saliency but not as much as in video saliency. In order to increase precision and accuracy during compression, reduce coding complexity and time consumption along with memory allocation problems with our proposed solution. It is a modified high-definition video compression (HEVC) pixel based consistent spatiotemporal diffusion with temporal uniformity. It involves taking apart the video into groups of frames, computing colour saliency, integrate temporal fusion, pixel saliency fusion is conducted and then colour information guides the diffusion process for the spatiotemporal mapping with the help of permutation matrix. The proposed solution is tested on a publicly available extensive dataset with five global saliency valuation metrics and is compared with several other state-of-the-art saliency detection methods. The results display and overall best performance amongst all other candidates.

Parallelism in a Region Inference Context

Region inference is a type-based program analysis that takes a non-annotated program as input and constructs a program that explicitly manages memory allocation and deallocation by dividing the heap into a stack of regions, each of which can grow and shrink independently from other regions, using constant-time operations. Whereas region-based memory management has shown useful in the contexts of explicit region-based memory management, and in particular, in combination with parallel execution of code, combining region inference with techniques for higher-order parallel programming has not been investigated. In this paper, we present an implementation of a fork-join parallel construct suitable for a compiler based on region inference. We present a minimal higher-order language incorporating the parallel construct, including typing rules and a dynamic semantics for the language, and demonstrate type soundness. We present a novel effect-based region-protection inference algorithm and discuss benefits and shortcomings of the approach. We also describe an efficient implementation embedded in the MLKit Standard ML compiler. Finally, we evaluate the approach and the implementation based on a number of parallel benchmarks, and thereby demonstrate that the technique effectively utilises multi-core architectures in a higher-order functional setting.

UArch: A Super-Resolution Processor With Heterogeneous Triple-Core Architecture for Workloads of U-Net Networks.

High-resolution medical images are of critical significance to improve disease diagnosis. Limited by the camera and power of medical devices, medical images often have very low resolution. For example, wireless capsule endoscopes, often used to diagnose diseases of the small bowel, can only capture low-resolution endoscopic images. The existing super-resolution (SR) networks perform exceptionally well in recovering high-resolution images, but they are computationally expensive and require high bandwidth, which can result in unacceptable latency and bandwidth requirements for embedded medical devices. In this paper, we propose a U-Net-based SR (USR) network structure and an SR processor named UArch. The USR-s, which is the lightweight version of USR, has an SR performance of 42.68dB for ×2 scale SR. The USR-s has 0.3dB higher PSNR (peak signal-to-noise ratio) than the SR algorithm, which is often used in recent SR hardware. Based on well-designed strategies, including heterogeneous triple-core architecture, fine-grained on-chip memory allocation, out-of-order execution, and sub- tensor-based processing flow, the UArch, designed for U-Net networks, can fulfill ×2, ×3, and ×4 scale SR by deploying USR-s, achieving high throughput of 60 fps and low latency of 25ms for ×2 scale 1920 × 1080 output image SR at 156MHz. The UArch achieves high energy efficiency which is 2264.5 GOPS/W when synthesized and evaluated under the TSMC 28nm process and which is 199.3 GOPS/W when implemented on Xilinx ZCU111. Our SR processor is capable of reconstructing high-quality endoscopic images and is more efficient than the previous state-of-the-art SR processors.

A novel GPU based Geo-Location Inference Attack on WebGL framework

In the past few years, graphics processing units (GPUs) have become an indispensable part of modern computer systems, not only for graphics rendering but also for intensive parallel computing. Given that many tasks running on GPUs contain sensitive information, security concerns have been raised, especially about potential GPU information leakage. Previous works have shown such concerns by showing that attackers can use GPU memory allocations or performance counters to measure victim side effects. However, such an attack has a critical drawback that it requires a victim to install desktop applications or mobile apps yielding it uneasy to be deployed in the real world. In this paper, we solve this drawback by proposing a novel GPU-based side-channel Geo-Privacy inference attack on the WebGL framework, namely, GLINT (stands for Geo-Location Inference Attack). GLINT merely utilizes a lightweight browser extension to measure the time elapsed to render a sequence of frames on well-known map websites, e.g., Google Maps, or Baidu Maps. The measured stream of time series is then employed to infer geologically privacy-sensitive information, such as a search on a specific location. Upon retrieving the stream, we propose a novel online segmentation algorithm for streaming data to determine the start and end points of privacy-sensitive time series. We then combine the DTW algorithm and KNN algorithm on these series to conclude the final inference on a user’s geo-location privacy.We conducted real-world experiments to testify our attack. The experiments show that GeoInfer can correctly infer more than 83% of user searches regardless of the locations and map websites, meaning that our Geo-Privacy inference attack is accurate, practical, and robust. To counter this attack, we implemented a defense strategy based on Differential Privacy to hinder obtaining accurate rendering data. We found that this defense mechanism managed to reduce the average accuracy of the attack model by more than 70%, indicating that the attack was no longer effective. We have fully implemented GLINT and open-sourced it for future follow-up research.

Overcoming the IOTLB wall for multi-100-Gbps Linux-based networking.

This article explores opportunities to mitigate the performance impact of IOMMU on high-speed network traffic, as used in the Linux kernel. We first characterize IOTLB behavior and its effects on recent Intel Xeon Scalable & AMD EPYC processors at 200 Gbps, by analyzing the impact of different factors contributing to IOTLB misses and causing throughput drop (up to 20% compared to the no-IOMMU case in our experiments). Secondly, we discuss and analyze possible mitigations, including proposals and evaluation of a practical hugepage-aware memory allocator for the network device drivers to employ hugepage IOTLB entries in the Linux kernel. Our evaluation shows that using hugepage-backed buffers can completely recover the throughput drop introduced by IOMMU. Moreover, we formulate a set of guidelines that enable network developers to tune their systems to avoid the "IOTLB wall", i.e., the point where excessive IOTLB misses cause throughput drop. Our takeaways signify the importance of having a call to arms to rethink Linux-based I/O management at higher data rates.

Co-Optimizing CPU Voltage, Memory Placement, and Task Offloading for Energy-Efficient Mobile Systems

Energy-saving is one of the most important missions in the design of battery-based mobile systems. Many ideas have been suggested for saving energy in different system layers. Specifically, (1) lowering the supply voltage for idle CPU time slots, (2) using hybrid memory to save DRAM refresh power, and (3) task offloading to edge/cloud servers are well-acknowledged techniques used in CPU, memory, and network subsystems. In this paper, we show that co-optimizing these three techniques is necessary for further reducing the energy consumption of mobile real-time systems. To this end, we present an extended task model and formulate the effect of dynamic voltage/frequency scaling (DVFS), hybrid memory allocation, and task offloading problems as a unified measure. We then present a new real-time task scheduling scheme, called Co-TOMS, to co-optimize the energy-saving techniques in CPU, memory, and network subsystems by considering the given task set and resource conditions. The main contributions of our study can be summarized as follows. First, we optimize three energy-saving techniques across different system layers and find that they have significant influence on each other. For example, the effect of DVFS alone is limited in mobile systems, but combining it with offloading greatly amplifies its efficiency. Second, previous studies on offloading usually define a deadline as the maximum allowable latency at the application-level, but we focus on hard real-time systems that must meet task-level deadlines. Third, we design a steady-state genetic algorithm that allows fast convergence with reasonable computation overhead under various resource and workload conditions.

Adaptive density-based robust topology optimization under uncertain loads using parallel computing

This work presents an efficient parallel implementation of density-based robust topology optimization (RTO) using adaptive mesh refinement (AMR) schemes permitting us to address the problem with modest computational resources. We use sparse grid stochastic collocation methods (SCMs) for transforming the RTO problem into a weighted multiple-loading deterministic problem at the collocation points. The calculation of these deterministic problems and the functional sensitivity is computationally expensive. We combine distributed-memory parallel computing and AMR techniques to address the problem efficiently. The former allows us to exploit the computational resources available, whereas the latter permits us to increase performance significantly. We propose the parallel incremental calculation of the deterministic problems and the contribution to the functional sensitivity maintaining a similar memory allocation to the one used in the deterministic counterpart. The cumulative computing uses buffers to adapt the evaluation at the collocation points to the parallel computing resources permitting the exploitation of the embarrassing parallelism of SCMs. We evaluate the deterministic problems in a coarse mesh generated for each topology optimization iteration to increase the performance. We perform the regularization and design variable update in a fine mesh to obtain an equivalent design to the one generated in such a mesh. We evaluate the proposal in two- and three-dimensional problems to test its feasibility and scalability. We also check the performance improvement using computational buffers in parallel computing nodes. Finally, we compare the proposal to the same approach using different preconditioners without AMR schemes showing significant performance improvements.