Memory Allocation Research Articles

RL-ANN-Based Minimum-Current-Stress Scheme for the Dual-Active-Bridge Converter With Triple-Phase-Shift Control

Aiming to reduce the current stress and improve the power efficiency of the dual-active-bridge (DAB) converter, this article proposes a reinforcement learning (RL) + artificial neural network (ANN)-based minimum-current-stress scheme. In the first stage, Q-learning as a typical algorithm of the RL method is adopted for offline training. The aim of the first stage is to solve the optimized control strategy based on the triple-phase-shift (TPS) control. More specifically, the zero-voltage-switching (ZVS) constraints and each effective operation mode are taken into consideration during the training process of the Q-learning algorithm. Therefore, the minimum-current-stress scheme while maintaining the soft switching can be obtained after the first stage. In the second stage, the training results of the Q-learning algorithm are used to train an ANN, in order to reduce the computational time and memory allocation. After that, the trained agent of the ANN, which likes an implicit function, can provide optimal phase-shift-angle online in real time under the entire continuous operation range. Finally, the detailed simulation and experimental results are given to demonstrate the effectiveness of the proposed optimized scheme.

Memory-Efficient CNN Accelerator Based on Interlayer Feature Map Compression

Existing deep convolutional neural networks (CNNs) generate massive interlayer feature data during network inference. To maintain real-time processing in embedded systems, large on-chip memory is required to buffer the interlayer feature maps. In this paper, we propose an efficient hardware accelerator with an interlayer feature compression technique to significantly reduce the required on-chip memory size and off-chip memory access bandwidth. The accelerator compresses interlayer feature maps through transforming the stored data into frequency domain using hardware-implemented <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$8\times 8$ </tex-math></inline-formula> discrete cosine transform (DCT). The high-frequency components are removed after the DCT through quantization. Sparse matrix compression is utilized to further compress the interlayer feature maps. The on-chip memory allocation scheme is designed to support dynamic configuration of the feature map buffer size and scratch pad size according to different network-layer requirements. The hardware accelerator combines compression, decompression, and CNN acceleration into one computing stream, achieving minimal compressing and processing delay. A prototype accelerator is implemented on an FPGA platform and also synthesized in TSMC 28-nm COMS technology. It achieves 403GOPS peak throughput and <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$1.4\times \sim 3.3\times $ </tex-math></inline-formula> interlayer feature map reduction by adding light hardware area overhead, making it a promising hardware accelerator for intelligent IoT devices.

Engineering In-place (Shared-memory) Sorting Algorithms

We present new sequential and parallel sorting algorithms that now represent the fastest known techniques for a wide range of input sizes, input distributions, data types, and machines. Somewhat surprisingly, part of the speed advantage is due to the additional feature of the algorithms to work in-place, i.e., they do not need a significant amount of space beyond the input array. Previously, the in-place feature often implied performance penalties. Our main algorithmic contribution is a blockwise approach to in-place data distribution that is provably cache-efficient. We also parallelize this approach taking dynamic load balancing and memory locality into account. Our new comparison-based algorithm In-place Parallel Super Scalar Samplesort ( IPS 4 o ) , combines this technique with branchless decision trees. By taking cases with many equal elements into account and by adapting the distribution degree dynamically, we obtain a highly robust algorithm that outperforms the best previous in-place parallel comparison-based sorting algorithms by almost a factor of three. That algorithm also outperforms the best comparison-based competitors regardless of whether we consider in-place or not in-place, parallel or sequential settings. Another surprising result is that IPS 4 o even outperforms the best (in-place or not in-place) integer sorting algorithms in a wide range of situations. In many of the remaining cases (often involving near-uniform input distributions, small keys, or a sequential setting), our new In-place Parallel Super Scalar Radix Sort ( IPS 2 Ra ) turns out to be the best algorithm. Claims to have the – in some sense – “best” sorting algorithm can be found in many papers which cannot all be true. Therefore, we base our conclusions on an extensive experimental study involving a large part of the cross product of 21 state-of-the-art sorting codes, 6 data types, 10 input distributions, 4 machines, 4 memory allocation strategies, and input sizes varying over 7 orders of magnitude. This confirms the claims made about the robust performance of our algorithms while revealing major performance problems in many competitors outside the concrete set of measurements reported in the associated publications. This is particularly true for integer sorting algorithms giving one reason to prefer comparison-based algorithms for robust general-purpose sorting.

Neural Network Modeling of Arbitrary Hysteresis Processes: Application to GO Ferromagnetic Steel

A computationally efficient hysteresis model, based on a standalone deep neural network, with the capability of reproducing the evolution of the magnetization under arbitrary excitations, is here presented and applied in the simulation of a commercial grain-oriented electrical steel sheet. The main novelty of the proposed approach is to embed the past history dependence, typical of hysteretic materials, in the neural net, and to illustrate an optimized training procedure. Firstly, an experimental investigation was carried out on a sample of commercial GO steel by means of an Epstein equipment, in agreement with the international standard. Then, the traditional Preisach model, identified only using three measured symmetric hysteresis loops, was exploited to generate the training set. Once the network was trained, it was validated with the reproduction of the other measured hysteresis loops and further hysteresis processes obtained by the Preisach simulations. The model implementation at a low level of abstraction shows a very high computational speed and minimal memory allocation, allowing a possible coupling with finite-element analysis (FEA).

A separation logic for heap space under garbage collection

We present SL♢, a Separation Logic that allows controlling the heap space consumption of a program in the presence of dynamic memory allocation and garbage collection. A user of the logic works with space credits, a resource that is consumed when an object is allocated and produced when a group of objects is logically deallocated, that is, when the user is able to prove that it has become unreachable and therefore can be collected. To prove such a fact, the user maintains pointed-by assertions that record the immediate predecessors of every object. Our calculus, SpaceLang, has mutable state, shared-memory concurrency, and code pointers. We prove that SL♢ is sound and present several simple examples of its use.

Особенности разработки программных продуктов с использованием массивов в объектно-ориентированной среде

The features of software development using static and dynamic arrays in the C ++ Builder object-oriented environment are considered. The syntax of various options for creating static and dynamic arrays in the C ++ Builder language is considered in detail. Examples of working with static and dynamic arrays in C ++ Builder developed by the authors and the corresponding algorithms are presented in the form of block diagrams, program codes and program interfaces. Examples of program development are given using one-dimensional and multidimensional arrays. Examples of memory allocation are given for dynamic arrays. The choice of the required method for solving the problem is substantiated, taking into account the available input data and taking into account the expected results, as well as the peculiarities of their obtaining and processing. The external specification and the main features of the solution of the assigned tasks are considered. The development of algorithms and programs for solving problems using arrays in the C ++ Builder environment is the basis for solving engineering and technical problems using software on a computer. The proposed approaches can be used in practice, since the algorithms outlined in the work will serve as a complex example in solving the set engineering and technical problems.

Improving Performance with SIMD Intrinsics

Computer application development has a long history. With the continuous development of hardware, both the software and the programming languages and frameworks that make application development possible have also changed. As we move forward in time, as more and more powerful computers become available, the level of programming languages has also risen to a higher level. Increasingly high-level APIs and languages have become available, pointers, memory allocations and releases have slowly disappeared from the area of the programming. However, with the transition to high-level languages, the optimization of programs or the possibility of it has been relegated to the background, because some efficiency-enhancing options are not available in high-level languages. This paper therefore delves deeper into the benefits of SSE/AVX based SIMD concurrency capabilities that are “forgotten” in everyday programming. The presented tests will show that there are reserves in the CPU that can be used to push certain performance limits further away.

A Novel Workload-Aware and Optimized Write Cycles in NVRAM

With the emergence of the Internet of things (IoT), embedded systems have now changed its dimensionality and it is applied in various domains such as healthcare, home automation and mainly Industry 4.0. These Embedded IoT devices are mostly battery-driven. It has been analyzed that usage of Dynamic Random-Access Memory (DRAM) centered core memory is considered the most significant source of high energy utility in Embedded IoT devices. For achieving the low power consumption in these devices, Non-volatile memory (NVM) devices such as Parameter Random Access Memory (PRAM) and Spin-Transfer Torque Magnetic Random-Access Memory (STT-RAM) are becoming popular among main memory alternatives in embedded IoT devices because of their features such as high thickness, byte addressability, high scalability and low power intake. Additionally, Non-volatile Random-Access Memory (NVRAM) is widely adopted to save the data in the embedded IoT devices. NVM, flash memories have a limited lifetime, so it is mandatory to adopt intelligent optimization in managing the NVRAM-based embedded devices using an intelligent controller while considering the endurance issue. To address this challenge, the paper proposes a powerful, lightweight machine learning-based workload-adaptive write schemes of the NVRAM, which can increase the lifetime and reduce the energy consumption of the processors. The proposed system consists of three phases like Workload Characterization, Intelligent Compression and Memory Allocators. These phases are used for distributing the write-cycles to NVRAM, following the energy-time consumption and number of data bytes. The extensive experimentations are carried out using the IoMT (Internet of Medical things) benchmark in which the different endurance factors such as application delay, energy and write-time factors were evaluated and compared with the different existing algorithms.

On the Applicability of Numerical Quadrature for Double Surface Integrals at 5G Frequencies

The human exposure assessment to wireless communications systems including the fifth generation (5G) mobile systems is related to determining the specific absorption rate (SAR) or the absorbed power density (APD). The assessment of both quantities requires the use of various numerical techniques, including moments method (MoM). As the use of MoM results in a fully populated system matrix, a tremendous computational cost is incurred, both in terms of matrix fill time and memory allocation, as the matrix size is directly related to frequency of the problem. This paper investigates the applicability of numerical integration at frequencies related to 5G. The novelty of this work is related to the comprehensive set of tests of various combination of source and observation triangles using the developed unit cube test. A number of convergence tests were performed to investigate the effects of the increasing frequency and the discretization scheme on the numerical solution, as well as to determine how to curb the computational requirements by the proficient use of numerical integration. The results show that in the lower GHz range, lower integration orders could be used, resulting in the decrease of matrix fill time without loss of solution accuracy.

Computer generation of detailed reaction networks in hydrocracking of Fischer-Tropsch wax

Fischer-Tropsch synthesis (FTS) wax is a mixture of linear hydrocarbons with carbon number from C7 to C70+. Converting FTS wax into high-quality diesel (no sulfur and nitrogen contents) by hydrocracking technology is attractive in economy and practicability. Kinetic study of the hydrocracking of FTS wax in elementary step level is very challenging because of the huge amounts of reactions and species involved. Generation of reaction networks for hydrocracking of FTS wax in which the chain length goes up to C70 is described on the basis of Boolean adjacency matrixes. Each of the species (including paraffins, olefins and carbenium ions) involved in the elementary steps is represented digitally by using a ( N + 3) × N matrix, in which a group of standardized numbering rules are designed to guarantee the unique identity of the species. Subsequently, the elementary steps are expressed by computer-aided matrix transformations in terms of proposed reaction rules. Dynamic memory allocation is used in species storage and a characteristic vector with nine elements is designed to store the key information of a ( N + 3) × N matrix, which obviously reduces computer memory consumption and improves computing efficiency. The detailed reaction networks of FTS wax hydrocracking can be generated smoothly and accurately by the current method. The work is the basis of advanced elementary-step-level kinetic modeling.

Operating Systems and Hypervisors for Network Functions: A Survey of Enabling Technologies and Research Studies

Scalable and flexible communication networks increasingly conduct the packet processing for Network Functions (NFs) in General Purpose Computing (GPC) platforms. The input/output (I/O)-intensive and latency-sensitive packet processing is challenging for the operating systems and hypervisors running on GPC platforms. This article surveys the existing enabling technologies and research studies on operating system and hypervisor aspects that directly influence the packet processing for NFs on GPC platforms. We organize this survey according to the main categories abstraction approach, memory access, and I/O strategy. We further categorize abstraction approach technologies and research studies into the categories operation systems, hypervisors, and containers. We partition the memory access category into the two sub-categories of memory allocation and memory access, while we partition the I/O strategy category into the sub-categories I/O device virtualization and I/O device access. Our survey gives a comprehensive summary of the capabilities and limitations of the existing enabling technologies and researched approaches for abstraction, memory access, and I/O for NF packet processing. We outline critical future research directions for advancing NF packet processing on GPC platforms.

OpSparse: A Highly Optimized Framework for Sparse General Matrix Multiplication on GPUs

Sparse general matrix multiplication (SpGEMM) is an important and expensive computation primitive in many real-world applications. Due to SpGEMM&#x2019;s inherent irregularity and the vast diversity of its input matrices, developing high-performance SpGEMM implementation on modern processors such as GPUs is challenging. The state-of-the-art SpGEMM libraries (i.e., <i>nsparse</i> and <i>spECK</i>) adopt several algorithms to tackle the challenges of global load balance, local load balance, and allocation of the result matrix. While these libraries focus on the high-level algorithm design for SpGEMM, they neglect several low-level architecture-specific optimizations, which causes inefficient implementations in their libraries. In this paper, we classify their inefficient implementations into several categories. Based on our observations, we propose a highly optimized SpGEMM library called <i>OpSparse</i>. The optimizations in <i>OpSparse</i> include 1) optimizing the binning method by improving the utilization of the shared memory, 2) optimizing the hashing method by reducing the access to the hash table, 3) improving the trade-off between hash collision rate and hardware utilization in the hashing method by setting appropriate binning ranges, 4) reducing the overheads of global memory utilization by minimizing the global memory usage of the metadata, and 5) improving the execution parallelism by overlapping global memory allocation with kernel execution. Performance evaluations with 26 commonly used matrices on an Nvidia Tesla V100 GPU show that <i>OpSparse</i> achieves on average 7.35&#x00D7; (up to 27.8&#x00D7;), 1.43&#x00D7; (up to 1.81&#x00D7;), and 1.52&#x00D7; (up to 2.04&#x00D7;) speedups over three state-of-the-art SpGEMM libraries: <i>cuSPARSE</i>, <i>nsparse</i>, and <i>spECK</i>, respectively.

Practical Near-Data-Processing Architecture for Large-Scale Distributed Graph Neural Network

Graph Neural Networks have drawn tremendous attention in the past few years due to their convincing performance and high interpretability in various graph-based tasks like link prediction and node classification. With the ever-growing graph size in the real world, especially for industrial graphs at a billion-level, the storage of graphs can easily consume Terabytes so that the process of GNNs has to be processed in a distributed manner. As a result, the execution could be inefficient due to the expensive cross-node communication and irregular memory access. Various GNN accelerators have been proposed for efficient GNN processing. They, however, mainly focused on small and medium-size graphs, which is not applicable to large-scale distributed graphs. In this paper, we present a practical Near-Data-Processing architecture based on a memory-pool system for large-scale distributed GNNs. We propose a customized memory fabric interface to construct the memory pool for low-latency and high throughput cross-node communication, which can provide flexible memory allocation and strong scalability. A practical Near-Data-Processing design is proposed for efficient work offloading and bandwidth utilization improvement. Moreover, we also introduce a partition and scheduling scheme to further improve performance and achieve workload balance. Comprehensive evaluations demonstrate that the proposed architecture can achieve up to <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$27\times $ </tex-math></inline-formula> and <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$8\times $ </tex-math></inline-formula> higher training speed compared to two state-of-the-art distributed GNN frameworks: Deep Graph Library and <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$P^{3}$ </tex-math></inline-formula> , respectively.

Local Memory Allocation Recruits Memory Ensembles Across Brain Regions

Local Memory Allocation Recruits Memory Ensembles Across Brain Regions

GShare: A centralized GPU memory management framework to enable GPU memory sharing for containers

Owing to low overhead and rapid deployment, containers are increasingly becoming an attractive system software platform for deep learning and high performance computing (HPC) applications that leverage GPUs. Unfortunately, existing container software does not concern how each container allocates GPU memory. Therefore, if a certain container consumes the majority of GPU memory, other containers may not run their workloads because of insufficient memory. This paper presents gShare, a centralized GPU memory management framework to enable GPU memory sharing for containers. As with a modern operating system, gShare allocates the entire GPU memory inside the framework and manages the memory with sophisticated memory allocators. gShare is then able to enforce the GPU memory limit of each container by mediating the memory allocation calls. To achieve its objective, gShare introduces the API remoting components, the mediator, and the three-level memory allocator, which enable lightweight and efficient GPU memory management. Our prototype implementation achieves near-native performance with secure isolation and little memory waste in popular deep learning and HPC workloads.

Variable-sized bin packing problem with conflicts and item fragmentation

In this paper, we study the Variable-Sized Bin Packing Problem with Conflicts and Item Fragmentation (VSBPPC-IF) that has applications such as (i) the delivery planning of incompatible items using a fleet of heterogenous vehicles where split delivery is allowed, and (ii) load balancing and memory allocation in parallel processing. In VSBPPC-IF, a set of items has to be packed into the bins with different capacities and costs. Items can be fragmented, and each fragment can be packed into a separate bin. However, the fragments of conflicting items cannot be packed into the same bin. The goal in VSBPPC-IF is to find a packing of the items into the bins with minimum total cost. We propose a lower bounding mechanism for the problem and compare it against the trivial continuous lower bound. We develop a novel heuristic algorithm based on the idea of generating subsets of compatible items and determining the types of the bins used by solving a mathematical model. We compare the performance of the proposed solution approach both against a lower bound and a set of benchmark algorithms from the literature. The proposed heuristic not only outperforms the benchmark algorithms but also provides solutions with quite low (0.25% on average) optimality gaps.

Performance characterization of containerization for HPC workloads on InfiniBand clusters: an empirical study

Containerization technology offers an appealing alternative for encapsulating and operating applications (and all their dependencies) without being constrained by the performance penalties of using Virtual Machines and, as a result, has got the interest of the High-Performance Computing (HPC) community to obtain fast, customized, portable, flexible, and reproducible deployments of their workloads. Previous work on this area has demonstrated that containerized HPC applications can exploit InfiniBand networks, but has ignored the potential of multi-container deployments which partition the processes that belong to each application into multiple containers in each host. Partitioning HPC applications has demonstrated to be useful when using virtual machines by constraining them to a single NUMA (Non-Uniform Memory Access) domain. This paper conducts a systematical study on the performance of multi-container deployments with different network fabrics and protocols, focusing especially on Infiniband networks. We analyze the impact of container granularity and its potential to exploit processor and memory affinity to improve applications’ performance. Our results show that default Singularity can achieve near bare-metal performance but does not support fine-grain multi-container deployments. Docker and Singularity-instance have similar behavior in terms of the performance of deployment schemes with different container granularity and affinity. This behavior differs for the several network fabrics and protocols, and depends as well on the application communication patterns and the message size. Moreover, deployments on Infiniband are also more impacted by the computation and memory allocation, and because of that, they can exploit the affinity better.

RustHorn: CHC-based Verification for Rust Programs

Reduction to satisfiability of constrained Horn clauses (CHCs) is a widely studied approach to automated program verification. Current CHC-based methods, however, do not work very well for pointer-manipulating programs, especially those with dynamic memory allocation. This article presents a novel reduction of pointer-manipulating Rust programs into CHCs, which clears away pointers and memory states by leveraging Rust’s guarantees on permission. We formalize our reduction for a simplified core of Rust and prove its soundness and completeness. We have implemented a prototype verifier for a subset of Rust and confirmed the effectiveness of our method.

Application of Radial Basis Neural Network in MPPT Technique for Stand-Alone PV System Under Partial Shading Conditions

This paper proposes a highly sophisticated controller to track the maximum power point (MPP) of Photovoltaic (PV) systems. This method is based on the Artificial Neural Network (ANN) algorithm, which uses Radial Basis Neural Network (RBNN) to estimate the optimum voltage for the considered PV system, which helps to extract Global MPP. The critical methodology lies in the RBNN block generation, which considers one-year real-time data of the Panaji, Goa (India) region for the training process to drive this extensive PV system with resistive load. Nearly 1500 samples of one-year real-time Irradiation (G) and Temperature (T) are given as input to RBNN. The proposed intelligent technique only consists of single-stage ANN, thereby reducing the processing time and memory allocations for generating the corresponding Vmpp value for each G and T. A comparative study has been done using conventional techniques like Perturb and Observe (P & O) and Incremental Conductance (InC) methodologies. It was found that RBNN MPPT is best to use with PV modules affected by partial shading; on average, the tracking accuracy ranging from 94.6% to 97.4%. The response time of the RBNN method to reach MPP is 0.007 s which is much faster than the P & O method (0.15 s) and InC method (0.268 s). Also, very few oscillations are observed with the RBNN method than the other two in the transient tracking period. Obtained results indicate that the proposed inherent learning-based controller, with its enhanced efficiency conversion and faster tracking speeds, ensures better reliability for the complete PV system.

Tnvmalloc: A Thread-Level-Based Wear-Aware Allocator for Nonvolatile Main Memory

The nonvolatile main memory (NVMM) has the advantages of near-DRAM speed, byte-addressability, and persistence, and presents limitations in write durability. The memory allocator, a fundamental data structure of memory management, can effectively mitigate the wear speed, thereby prolonging the NVMM lifetime. Nevertheless, balancing the performance and writing reliability in single and multi-thread scenarios is still an open problem for NVMM allocators. In this paper, we propose a thread-level wear-aware allocator (Tnvmalloc) that divides the NVMM space into multiple management granularities and then dynamically selects the optimal blocks using a wear-leveling strategy based on allocation requests and wear records. Experiments show that the proposed Tnvmalloc provides more than 10 times improvement in wear-leveling than typical allocators Glibc malloc, NVMalloc, and nvm_malloc, which becomes obvious especially in multi-threaded scenarios. Moreover, when allocating large memory blocks, Tnvmalloc achieves three times faster than that of NVMalloc.