Memory Access Research Articles

Cognitive causes of ‘like me’ race and gender biases in human language production

Natural language contains and communicates social biases, often reflecting attitudes, prejudices and stereotypes. Here we provide evidence for a novel psychological pathway for the expression of such biases, in which they arise as a consequence of the automatized mechanisms by which humans retrieve words to produce sentences. Four experiments show that, when describing events, speakers tend to mention people who are more like them first and, thus, tend to highlight the perspectives of their own social groups. This ‘like me’ effect was seen in speakers from multiple demographic groups, in both English and Chinese speakers and in both first- and second-language English speakers. Psycholinguistic manipulations pinpoint that the bias is caused by greater accessibility in memory of words that refer to in-group than out-group members. These data provide a new cognitive explanation for why people produce biased language and highlight how detailed cognitive theories can have social implications.

QRNet: Query-based reparameterization net for real-time detection of power adapter surface defects

In industrial production, automated surface defect detection holds paramount importance. While current techniques can handle complex background power adapter surface defect detection with high precision, they have many parameters, low speed, slow convergence, and complex post-processing (such as non-maximum suppression). To this end, this study aims to develop a more efficient and effective method for surface defect detection. The primary objective of this research is to enhance the speed of detection without sacrificing accuracy. This paper designs the Separable-reparam Feature Module (SFM), which is based on depth-wise convolution, to fuse multi-branch features through reparameterization techniques. SFM has low parameters and excels in feature extraction without increasing the model’s Memory Access Cost (MAC). SFM combines cross-stage fusion to construct the backbone, enabling the extraction of multi-scale features. Following the standard query decoder architecture, a QRNet was built to learn the query set of objects, and predict the surface defect set for power adapter. Additionally, a novel two-stage mixed-supervised transfer-learning approach is proposed to expedite the convergence process. Experimental results on the power adapter defect dataset demonstrate QRNet’s remarkable performance. It achieved a mean average precision (mAP) of 98.94 % with just 0.841 M parameters and a latency of 5.72 ms. In conclusion, QRNet represents an advancement in surface defect detection, offering a balance between accuracy and efficiency.

Adapting arepo-rt for exascale computing: GPU acceleration and efficient communication

ABSTRACT Radiative transfer (RT) is a crucial ingredient for self-consistent modelling of numerous astrophysical phenomena across cosmic history. However, on-the-fly integration into radiation hydrodynamics (RHD) simulations is computationally demanding, particularly due to the stringent time-stepping conditions and increased dimensionality inherent in multifrequency collisionless Boltzmann physics. The emergence of exascale supercomputers, equipped with extensive CPU cores and GPU accelerators, offers new opportunities for enhancing RHD simulations. We present the first steps towards optimizing arepo-rt for such high-performance computing environments. We implement a novel node-to-node (n-to-n) communication strategy that utilizes shared memory to substitute intranode communication with direct memory access. Furthermore, combining multiple internode messages into a single message substantially enhances network bandwidth utilization and performance for large-scale simulations on modern supercomputers. The single-message n-to-n approach also improves performance on smaller scale machines with less optimized networks. Furthermore, by transitioning all RT-related calculations to GPUs, we achieve a significant computational speedup of around 15 for standard benchmarks compared to the original CPU implementation. As a case study, we perform cosmological RHD simulations of the Epoch of Reionization, employing a similar setup as the THESAN project. In this context, RT becomes sub-dominant such that even without modifying the core arepo codebase, there is an overall threefold improvement in efficiency. The advancements presented here have broad implications, potentially transforming the complexity and scalability of future simulations for a wide variety of astrophysical studies. Our work serves as a blueprint for porting similar simulation codes based on unstructured resolution elements to GPU-centric architectures.

MultiSplit: An Efficient Algorithm for Packet Classification with Equivalent Priority

Packet classification is a core function of network devices for providing advanced services, with the key challenge being to optimize classification speed while maintaining low memory usage. So far, many have proposed software-based packet classification solutions, with most of them adopting a multi-classifier architectures to accommodate the distribution of rule sets. Unfortunately, the need to perform lookups on each classifier during the packet classification stage significantly increases overhead, severely limiting classification speed. To address this shortfall, an efficient packet classification framework based on decision tree algorithms named MultiSplit is proposed. By leveraging the relationships of coverage and priority within the rule set, a new attribute can be abstracted for each rule, termed equivalent priority. Through this preprocessing, MultiSplit significantly reduces redundant lookup overhead while supporting the multi-classifier framework. Additionally, MultiSplit introduces a novel decision tree algorithm that combines multiple splits and intra-level binary search, significantly improving rule separation efficiency. The experimental results show that MultiSplit reduces memory consumption by 49% and decreases memory access by 63%, on average, compared with state-of-the-art packet classification algorithms.

Spiking neural networks for nonlinear regression of complex transient signals on sustainable neuromorphic processors

In recent years, spiking neural networks were introduced in science as the third generation of artificial neural networks leading to a tremendous energy saving on neuromorphic processors. This sustainable effect is due to the sparse nature of signal processing in-between spiking neurons leading to much less scalar multiplications as in second-generation networks. The spiking neuron’s efficiency is even more pronounced by their inherently recurrent nature being useful for recursive function approximations. We believe that there is a need for a general regression framework for SNNs to explore the high potential of neuromorphic computations. However, besides many classification studies with SNNs in the literature, nonlinear neuromorphic regression analysis represents a gap in research. Hence, we propose a general SNN approach for function approximation applicable for complex transient signal processing taking surrogate gradients due to the discontinuous spike representation into account. However, to pay attention to the need for high memory access during deep SNN network communications, additional spiking Legrendre Memory Units are introduced in the neuromorphic architecture. Path-dependencies and evolutions of signals can be tackled in this way. Furthermore, interfaces between real physical and binary spiking values are necessary. Following this intention, a hybrid approach is introduced, exhibiting an autoencoding strategy between dense and spiking layers. However, to verify the presented framework of nonlinear regression for a wide spectrum of scientific purposes, we see the need for obtaining realistic complex transient short-time signals by an extensive experimental set-up. Hence, a measurement technique for benchmark experiments is proposed with high-frequency oscillations measured by capacitive and piezoelectric sensors resulting in wave propagations and inelastic solid deformations to be predicted by the developed SNN regression analysis. Hence, the proposed nonlinear regression framework can be deployed to a wide range of scientific and technical applications.

PIM GPT a hybrid process in memory accelerator for autoregressive transformers

Decoder-only Transformer models such as Generative Pre-trained Transformers (GPT) have demonstrated exceptional performance in text generation by autoregressively predicting the next token. However, the efficiency of running GPT on current hardware systems is bounded by low compute-to-memory-ratio and high memory access. In this work, we propose a Process-in-memory (PIM) GPT accelerator, PIM-GPT, which achieves end-to-end acceleration of GPT inference with high performance and high energy efficiency. PIM-GPT leverages DRAM-based PIM designs for executing multiply-accumulate (MAC) operations directly in the DRAM chips, eliminating the need to move matrix data off-chip. Non-linear functions and data communication are supported by an application specific integrated chip (ASIC). At the software level, mapping schemes are designed to maximize data locality and computation parallelism. Overall, PIM-GPT achieves 41 − 137 × , 631 − 1074 × speedup and 123 − 383 × , 320 − 602 × energy efficiency over GPU and CPU baseline on 8 GPT models with up to 1.4 billion parameters.

Quantized CNN-based efficient hardware architecture for real-time hand gesture recognition

Nowadays, Convolutional Neural Networks (CNN) have been widely adopted for vision-based hand gesture recognition. Several existing CNN architectures designed for gesture classification perform well with high accuracy but require a high memory footprint and processing when deployed on low-power embedded devices. To address this issue, we present a quantized CNN-based efficient framework for meeting real-life hand gesture recognition challenges. The proposed quantized CNN is designed and implemented using the FINN-based pipelined streaming architecture on an FPGA. Moreover, hardware-based optimizations are used to minimize the resources needed and to achieve fast memory access. Experimental results demonstrate that the developed recognition system achieves an average accuracy of 92% on the numeral database of Indian Sign Language (ISL). Additionally, our optimized design attains an inference latency of 0.85ms for real-time single gesture prediction on the PYNQ Zynq Ultrascale (ZU) FPGA, consuming only 3.63 W of power. The proposed design achieves a better trade-off between hardware resource utilization and speed performance, over previous designs.

CFE-YOLOv8s: Improved YOLOv8s for Steel Surface Defect Detection

Due to the low detection accuracy in steel surface defect detection and the constraints of limited hardware resources, we propose an improved model for steel surface defect detection, named CBiF-FC-EFC-YOLOv8s (CFE-YOLOv8s), including CBS-BiFormer (CBiF) modules, Faster-C2f (FC) modules, and EMA-Faster-C2f (EFC) modules. Firstly, because of the potential information loss that convolutional neural networks (CNN) may encounter when dealing with miniature targets, the CBiF combines CNN with Transformer to optimize local and global features. Secondly, to address the increased computational complexity caused by the extensive use of convolutional layers, the FC uses the FasterNet block to reduce redundant computations and memory access. Lastly, the EMA is incorporated into the FC to design the EFC module and enhance feature fusion capability while ensuring the light weight of the model. CFE-YOLOv8s achieves mAP@0.5 values of 77.8% and 69.5% on the NEU-DET and GC10-DET datasets, respectively, representing enhancements of 3.1% and 2.8% over YOLOv8s, with reductions of 22% and 18% in model parameters and FLOPS. The CFE-YOLOv8s demonstrates superior overall performance and balance compared to other advanced models.

Two-stage re-parameterization and sample disentanglement network for surveillance vehicle detection

Abstract Detecting vehicles from a surveillance viewpoint is essential, as it has wide applications in community security and traffic control. However, existing methods completely overlook the high memory access costs (MAC) and low degree of parallelism inherent in multi-branch topologies, resulting in significant latency during inference. Additionally, existing methods share the same positive/negative sample set between the classification and localization branches, leading to sample misalignment, and rely solely on intersection-over-union (IoU) for sample assignment, thereby causing a decrease in detection performance. To tackle these issues, this paper introduces a two-stage re-parameterization and sample disentanglement network (TRSD-Net). It is based on two-stage depthwise to pointwise re-parameterization (RepTDP) and task-aligned sample disentanglement (TSD). RepTDP employs structural re-parameterization to decouple the multi-branch topology during training and the plain architecture during inference, thus achieving low latency. By employing different sample assignment strategies, TSD can adaptively select the most suitable positive/negative sample sets for classification and localization tasks, thereby enhancing detection performance. Additionally, TSD considers three important factors influencing sample assignment. TRSD-Net is evaluated on both the UA-DETRAC and COCO datasets. On the UA-DETRAC dataset, compared to state-of-the-art (SOTA) methods, TRSD-Net improves the detection accuracy from 58.8% to 59.7%. Additionally, it reduces the parameter count by 87%, the computational complexity by 85%, and the latency by 39%, while increasing the detection speed by 65%. Similar performance improvement trends are observed on the COCO dataset.

Split_ Composite: A Radar Target Recognition Method on FFT Convolution Acceleration.

Synthetic Aperture Radar (SAR) is renowned for its all-weather and all-time imaging capabilities, making it invaluable for ship target recognition. Despite the advancements in deep learning models, the efficiency of Convolutional Neural Networks (CNNs) in the frequency domain is often constrained by memory limitations and the stringent real-time requirements of embedded systems. To surmount these obstacles, we introduce the Split_ Composite method, an innovative convolution acceleration technique grounded in Fast Fourier Transform (FFT). This method employs input block decomposition and a composite zero-padding approach to streamline memory bandwidth and computational complexity via optimized frequency-domain convolution and image reconstruction. By capitalizing on FFT's inherent periodicity to augment frequency resolution, Split_ Composite facilitates weight sharing, curtailing both memory access and computational demands. Our experiments, conducted using the OpenSARShip-4 dataset, confirm that the Split_ Composite method upholds high recognition precision while markedly enhancing inference velocity, especially in the realm of large-scale data processing, thereby exhibiting exceptional scalability and efficiency. When juxtaposed with state-of-the-art convolution optimization technologies such as Winograd and TensorRT, Split_ Composite has demonstrated a significant lead in inference speed without compromising the precision of recognition.

Mitigating measures of memory access bottlenecks in high performance computing

Mitigating measures of memory access bottlenecks in high performance computing

Autobiographical memory of blind and sighted early teenagers: Memory accessibility, episodicity and phenomenology

AbstractVisual system is crucial to autobiographical memory. Research tended to show that blind adults may compensate for the loss of visual information in retrieval of their autobiographical memories. Much less is known about how blind children's autobiographical memory develops in the absence of visual information. Using cue‐word methodology, 36 sighted and 33 blind early teenagers were asked to recall memories and subsequently rated phenomenological qualities of their memories. Retrieval latency, the number of prompts provided, episodic and non‐episodic details reported for each memory were coded. In terms of memory accessibility, the blind group recalled comparable number of memories with comparable latency to retrieve memories, but they needed more prompting. Blind participants recalled similar number of episodic details; however, they reported more extraneous details, decreasing specificity. Blind early teenagers reported higher auditory imagery, a propensity to remember events from the first‐person perspective, and a tendency to remember events as coherent stories.

FPGA-based tiling scheme and on-chip memory scheduling scheme for multi-branch semantic segmentation neural network accelerator

Abstract According to the characteristics of a multi-branch semantic segmentation neural network with a large amount of intermediate data during the inference process, we reduce the requirement of off-chip memory access and the redundant calculation due to tiling through better blocking scheme, better on-chip memory partitioning scheme, and on-chip memory scheduling scheme, improving the energy efficiency to 77.4 GOPS/W.

Hyperion: A Highly Effective Page and PC Based Delta Prefetcher

Hardware prefetching plays an important role in modern processors for hiding memory access latency. Delta prefetchers show great potential at the L1D cache level, as they can impose small storage overhead by recording deltas. Furthermore, local delta prefetchers, such as Berti, have been shown to achieve high L1D accuracy. However, there is still room for improving the L1D coverage of existing delta prefetchers. Our goal is to develop a delta prefetcher capable of achieving both high L1D coverage and accuracy. We explore delta prefetchers trained on various types of contextual information, ranging from coarse-grained to fine-grained, and analyze their L1D coverage and accuracy. Our findings indicate that training deltas based on the access histories of both PCs and memory pages for individual PCs and memory pages can lead to increased L1D coverage alongside high accuracy. Therefore, we introduce Hyperion, a highly efficient Page and PC-based delta prefetcher. In terms of the vital component of recording access histories, we implement three different structures and engage in a detailed discussion about them. Furthermore, Hyperion utilizes micro-architecture information (e.g., L1D hits or misses, PQ occupancy) and real-time L1D accuracy to dynamically adjust its issuing mechanism, further enhancing performance and L1D accuracy. Our results show that Hyperion achieves an L1D accuracy of 92.4% and an L1D coverage of 51.9%, along with an L2C coverage of 63.0% and an LLC coverage of 67.5% across a diverse range of applications, including SPEC CPU2006, SPEC CPU2017, GAP, and PARSEC, with a baseline of no prefetching. Regarding performance, Hyperion achieves a 50.1% performance gain, outperforming the state-of-the-art delta prefetcher Berti by 5.0% over baseline across all memory-intensive traces from the four benchmark suites.

MCU-based Safer Coagulation Mode by Nonfixed Duty Cycle for an Electrosurgery Inverter.

The arcing-involved pulsating coagulation mode with both active and blank periods is essential for modern electrosurgery. This paper begins with a comprehensive introduction to such a pulsating mode, followed by its implementation challenges. Then, an industrial-scale low-speed microcontroller unit (MCU), TMS320F28379D, is utilized to exemplify the proposed output sampling and data-transferring strategy on a gallium nitride (GaN)-based high-frequency inverter that enables coagulation mode with interweaved active periods and blank periods. The inverter prototype fills the active period with 390 kHz sinusoids of amplitude ranging from hundreds to thousands of Volts, while maintaining null outputs during blank periods. The strategy of sampling the above-mentioned sinusoidal outputs, coupled with their data transfer facilitated by direct memory access (DMA), is also articulated for subsequential power computation. Besides that, a novel nonfixed duty cycle approach, featuring an alterable number of sinusoids as the active period, is proposed and integrated into the GaN-based inverter to enhance mode safety. Finally, the power tracking performance of the mode is evaluated initially on resistive load, secondarily on resistive plus capacitive load (R-C), and thirdly on fresh biotissue with the appearance of electrical arcing. The existing necessity of the null blank periods is examined at the end of the paper.

BPN-YOLO: A Novel Method for Wood Defect Detection Based on YOLOv7

The detection of wood defect is a crucial step in wood processing and manufacturing, determining the quality and reliability of wood products. To achieve accurate wood defect detection, a novel method named BPN-YOLO is proposed. The ordinary convolution in the ELAN module of the YOLOv7 backbone network is replaced with Pconv partial convolution, resulting in the P-ELAN module. Wood defect detection performance is improved by this modification while unnecessary redundant computations and memory accesses are reduced. Additionally, the Biformer attention mechanism is introduced to achieve more flexible computation allocation and content awareness. The IOU loss function is replaced with the NWD loss function, addressing the sensitivity of the IOU loss function to small defect location fluctuations. The BPN-YOLO model has been rigorously evaluated using an optimized wood defect dataset, and ablation and comparison experiments have been performed. The experimental results show that the mean average precision (mAP) of BPN-YOLO is improved by 7.4% relative to the original algorithm, which can better meet the need to accurately detecting surface defects on wood.

Social episodic memory in severe alcohol use disorder: Positive encoding bias and negative bias in accessibility of interpersonal information.

Alterations in higher-order social cognition are well documented in individuals with severe alcohol use disorder (SAUD). However, the basic mechanisms underpinning them are not well understood. This knowledge gap hampers the development of targeted therapeutic interventions. Here, we investigated whether individuals with SAUD show abnormalities in social episodic memory processes, which may represent relevant candidate mechanisms for alterations in social cognition. Recently detoxified patients with SAUD and matched healthy controls (HCs) completed two experimental tasks. We first used a Social Recognition Task in 40 SAUD patients and 40 HCs to measure the participants' ability to implicitly memorize the facial identity and emotion of novel interpersonal cues (i.e., dynamic facial expressions of anger and happiness). We then used a Social Memory Accessibility Task in 29 SAUD patients and 30 HCs) to measure participants' access to and fluency for already existing social memories by asking them to retrieve as many specific positive and negative interpersonal events as possible within equal time limits. In the Social Recognition Task, we found that, compared to HCs, patients with SAUD had a globally lower recognition performance for the facial identities of novel social stimuli, but a preserved bias toward positive information. Conversely, in the social memory accessibility task, patients showed greater access to and fluency for negative interpersonal memories than controls (no group differences were observed for positive ones), resulting in a negative accessibility bias. This exploration of episodic social memory in individuals with SAUD showed (1) a preserved bias for the encoding of positive versus negative novel social information, and (2) greater access to negative than positive interpersonal memories. These results enhance our understanding of socio-affective processing in individuals with SAUD and identify social memory alterations that may contribute to social cognition and interpersonal difficulties.

A novel Laplacian vector directional filter designed for real-time removal of impulsive noise from color images

Eliminating noise from a color image represents an essential task in image processing, given that noise can markedly diminish visual quality and impact the precision of subsequent analyses or applications (such as visual quality inspection, medical image analysis, etc.). In this study, we introduce an innovative approach designed to remove noise while preserving the edges and fine details of a color image. This method is based on Laplacian operators, threshold values for identifying potentially corrupted pixels due to noise, and the Vector Directional Filter (VDF) for substituting noisy pixels. Consequently, this technique is termed Laplacian VDF (LVDF). Additionally, a Hardware/Software (HW/SW) design is formulated for the real-time implementation of the LVDF filter. The hardware architecture is designed through the High-Level Synthesis (HLS) flow, while the software component is executed using the ARM Cortex-A53 hardcore processor. Furthermore, five Direct Memory Access (DMAs) are employed to enhance data throughput between the hardware coprocessor and Double Data Rate (DDR) memory. Performance evaluations conducted on the ZCU102 kit reveal that the LVDF HW/SW design facilitates the restoration of 74 images per second, resulting in a 94 % reduction in execution time compared to the software implementation, all while maintaining consistent objective and subjective image quality.

Accelerating Graph Analytics Using Attention-Based Data Prefetcher

Graph analytics shows promise for solving challenging problems on relational data. However, memory constraints arise from the large size of graphs and the high complexity of algorithms. Data prefetching is a crucial technique to hide memory access latency by predicting and fetching data into the memory cache beforehand. Traditional prefetchers struggle with fixed rules in adapting to complex memory access patterns in graph analytics. Machine learning (ML) algorithms, particularly long short-term memory (LSTM) models, excel in memory access prediction. However, they encounter challenges such as difficulty in learning interleaved access patterns and high storage costs when predicting in large memory address space. In addition, there remains a gap between designing a high-performance ML-based memory access predictor and developing an effective ML-based prefetcher for an existing memory system. In this work, we propose a novel Attention-based prefetching framework to accelerate graph analytics applications. To achieve high-performance memory access prediction, we propose A2P, a novel Attention-based memory Access Predictor for graph analytics. We use the multi-head self-attention mechanism to extract features from memory traces. We design a novel bitmap labeling method to collect future deltas within a spatial range, making interleaved patterns easier to learn. We introduce a novel super page concept, allowing the model to surpass physical page constraints. To integrate A2P into a memory system, we design a three-module prefetching framework composed of an existing memory hierarchy, a prefetch controller, and the predictor A2P. In addition, we propose a hybrid design to combine A2P and existing hardware prefetchers for higher prefetching performance. We evaluate A2P and the prefetching framework using the widely used GAP benchmark. Prediction experiments show that for the top three predictions, A2P outperforms the widely used state-of-the-art LSTM-based model by 23.1% w.r.t. Precision, 21.2% w.r.t. Recall, and 10.4% w.r.t. Coverage. Prefetching experiments show that A2P provides 18.4% IPC Improvement on average, outperforming state-of-the-art prefetchers BO by 17.2%, ISB by 15.0%, and Delta-LSTM by 10.9%. The hybrid prefetcher combining A2P and ISB achieves 21.7% IPC Improvement, outperforming the hybrid of BO and ISB by 16.3%.

Tackling addictive behaviors through memory suppression: A scoping review and perspective.

Forgetting is often viewed as a human frailty. However, over the years, it has been considered an adaptive process that allows people to avoid retrieval of undesirable memories, preventing them from suffering and discomfort. Evidence shows that the ability to suppress memories is affected by several psychopathological conditions characterized by persistent unwanted thoughts, including anxiety and posttraumatic stress disorders. Nevertheless, memory suppression (MS) mechanisms in addiction-a clinical condition characterized by recurrent drug-related thoughts that contribute to repeated drug use-have received little attention so far. Addiction theories reveal that drugs change behavior by working on memory systems, particularly on declarative memory, which is related to the retrieval and encoding of drug-related memories. In this review, the main behavioral and neurofunctional findings concerning the Think/No-Think task-an adaptation of the classical Go/No-Go tasks typically used to evaluate the suppression of motor response-are presented. We then show how the memory system can be involved in the craving or anticipation/preoccupation stage of the addiction cycle. Subsequently, the study of MS in the context of addictive behaviors is highlighted as a promising approach for gaining knowledge about the mechanisms contributing to the continuation of addiction. Finally, we discuss how interventions aiming to strengthen this ability could impact the anticipation/preoccupation stage by (i) reducing the accessibility of drug-related memories, (ii) decreasing craving and attention toward drug-related stimuli, and (iii) improving overall inhibition abilities. In conclusion, this review aims to illustrate how the study of MS may be a valuable approach to enhance our understanding of substance use disorders by unveiling the underlying cognitive and neural mechanisms involved, which could have important implications for addiction treatment.