Memory Access Requirements Research Articles

An efficient sequential consistency implementation with dynamic race detection for GPUs

As GPUs are being used for general purpose computations, applications with different memory access requirements have emerged. In spite of the growing demand, only few GPU coherence protocols and memory models have been explored in research, and even fewer models have been implemented in products. However, in the CPU domain a diverse range of memory models for parallel programming have been proposed, which explore the interplay between performance and programmability.Sequential consistency (SC) is one of the strict memory models. It provides the most programmer intuitive execution of memory operation but it imposes strict ordering restrictions on memory operations that cause performance overhead. Hence, implementing and supporting SC is one of the most challenging tasks in any computing platform, and GPUs are no exception. As such in this paper, we propose a GPU architecture that implements SC memory model with minimal performance and power overhead. We achieve this goal by designing a mechanism to detect races between different streaming multiprocessors (SMs) dynamically at runtime. The race is detected using a signature-based mechanism to keep track of sets of unseen updates for each SM which significantly reduces the hardware implementation cost, with a small increase in invalidation traffic. Our experiments show that dynamic race detection can be used to implement sequential consistency with 5% performance overhead.

Hardware acceleration of number theoretic transform for zk‐SNARK

AbstractZk‐SNARK unleashes the great potential of ZKP (zero‐knowledge proof) in the blockchain, distributed storage, and so forth. However, the proof‐generation of zk‐SNARK is excessively time intensive, making it a challenge to deploy a high‐performance zk‐SNARK in most real applications. As a result, NTT (Number Theoretic Transform), one of the most time‐consuming parts in proof‐generation, needs to be accelerated significantly. To address this issue, we propose a novel and efficient “data reordering" technique to enable a highly pipelined architecture, on which an FPGA‐based hardware accelerator is designed to support the large‐bitwidth and large‐scale NTT tasks in zk‐SNARK. This two‐level pipelined architecture can effectively reduce the data dependency and memory access requirements, meanwhile, can be flexibly scaled to different scales of FPGAs. To balance computing efficiency and flexibility, the OpenCL equipped with HLS is used to implement the heterogeneous acceleration system. We prototype the accelerator on the AMD‐Xilinx Alveo U50 card (UltraScale+ XCU50 FPGA). The evaluation results show that (1) our accelerator shows high scalability for different scales of FPGAs with a stable performance improvement; (2) it performs 1.95 faster than the one in PipeZK; (3) and it achieves 27.98 , 1.74 speedup and 6.9 , 6 energy efficiency improvement than AMD Ryzen 9 5900X single core and 12 cores respectively when integrated into the well‐known ZKP open‐source project, Bellman.

A Heterogeneity-Aware Replacement Policy for the Partitioned Cache on Asymmetric Multi-Core Architectures.

In an asymmetric multi-core architecture, multiple heterogeneous cores share the last-level cache (LLC). Due to the different memory access requirements among heterogeneous cores, the LLC competition is more intense. In the current work, we propose a heterogeneity-aware replacement policy for the partitioned cache (HAPC), which reduces the mutual interference between cores through cache partitioning, and tracks the shared reuse state of each cache block within the partition at runtime to guide the replacement policy to keep cache blocks shared by multiple cores in multithreaded programs. In the process of updating the reuse state, considering the difference of memory accesses to LLC by heterogeneous cores, the cache replacement policy tends to keep cache blocks required by big cores, to better improve the LLC access efficiency of big cores. Compared with LRU and the SRCP, which are the state-of-the-art cache replacement algorithms, the performance of big cores can be significantly improved by HAPC when running multithreaded programs, while the impact on little cores is almost negligible, thus improving the overall performance of the system.

A 10pJ/bit 256b AES-SoC Exploiting Memory Access Acceleration

Low-cost high-volume internet of things sensors require an end-to-end secure private-content exchange. Restricted energy and computing of system-on-a-chip for low-cost sensor applications drive lightweight hardware acceleration of security primitives. A trade-off between power and time needs to be achieved to develop such primitives. The main challenge is to handle memory transportation in the crypto-accelerator. Here we propose different approaches for AES-128/256 Sbox acceleration schemes. We designed a Sbox unit to be connected as a logic unit. The unit was tested as a RISC-V ISA instruction in the RISC-V processor to reduce software execution times. This unit was also included in an AES hardware core with direct memory access (DMA), which avoids using the main processor to access the data. We fabricated a RISC-V based 32-bit SoC in a standard 180nm CMOS technology that includes the Sbox calculation using pipeline and a pure-combinational approach. Measurement results indicate lower memory access and lower energy requirements than pure software approaches up to 100 times with a custom Sbox instruction. The AES core also provides a minimum energy consumption of 3.58 pJ/cycle. At its best, the combined SoC performs the encryption in active-mode with energy consumption of 9.7 pJ/bit. This solution offers up to three times energy savings compared to previously reported work.

Uneven memory regulation for scheduling IMA applications on multi-core platforms

The adoption of multi-cores for mixed-criticality systems has fueled research on techniques for providing scheduling isolation guarantees to applications of different criticalities. These are especially hard to provide in the presence of contention in shared resources of the system, such as buses and DRAMs. The state-of-the-art Single-Core Equivalence (SCE) framework improves timing isolation by enforcing periodic memory access budgets per core, which allows computing safe stall delays for the cores as input to the schedulability analysis. In this work, we extend the theoretical toolkit for this state-of-the-art framework by considering EDF and server-based scheduling, instead of partitioned fixed-priority scheduling which SCE has assumed so far. A second extension to the theory of SCE consists in additionally allowing memory access budgets to be uneven and defined on a per-server basis, rather than just on a per-core basis, which is what was supported until now. This added flexibility allows better memory bandwidth efficiency, especially when servers with dissimilar memory access requirements co-exist on a given core, and this in turn improves schedulability. Finally, we also formulate an Integer-Linear Programming Model (ILP) guaranteed to find a feasible mapping of a given set of servers to processors, including their execution time and memory access budgets, if such a mapping exists. Our experiments with synthetic task sets confirm that considerable improvement in schedulability can result from the use of per-server memory access budgets under the SCE framework.

Real-time machine vision FPGA implementation for microfluidic monitoring on Lab-on-Chips.

A machine vision implementation on a field-programmable gate array (FPGA) device for real-time microfluidic monitoring on Lab-On-Chips is presented in this paper. The machine vision system is designed to follow continuous or plug flows, for which the menisci of the fluids are always visible. The system discriminates between the front or "head" of the flow and the back or "tail" and is able to follow flows with a maximum speed of 20 mm/sec in circular channels of a diameter of 200 μm (corresponding to approx. 60 μl/sec ). It is designed to be part of a complete Point-of-Care system, which will be portable and operate in non-ideal laboratory conditions. Thus, it is able to cope with noise due to lighting conditions and small LoC displacements during the experiment execution. The machine vision system can be used for a variety of LoC devices, without the need for fiducial markers (such as redundancy patterns) for its operation. The underlying application requirements called for a complete hardware implementation. The architecture uses a variety of techniques to improve performance and minimize memory access requirements. The system input is 8 bit grayscale uncompressed video of up to 1 Mpixel resolution. The system uses an operating frequency of 170 Mhz and achieves a computational time of 13.97 ms (worst case), which leads to a throughput of 71.6 fps for 1 Mpixel video resolution.

An Efficient Architecture of Forward Transforms and Quantization for H.264/AVC Codecs

Thanks to many novel coding tools, H.264/AVC has become the most efficient video compression standard providing much better performance than previous standards. However, this standard comes with an extraordinary computational complexity and a huge memory access requirement, which make the hardware architecture design much more difficult and costly, especially for realtime applications. In the framework of H.264 codec hardware architecture project, this paper presents an efficient architecture of Forward Transform and Quantization (FTQ) for H.264/AVC codecs in mobile applications. To reduce the hardware implementation overhead, the proposed design uses only one unified architecture of 1-D transform engine to perform all required transform processes, including discrete cosine transform and Walsh Hadamard transform. This design also enables to share the common parts among multipliers that have the same multiplicands. The performance of the design is taken into consideration and improved by using a fast architecture of the multiplier in the quantizer, the most critical component in the design. Experimental results show that our architecture can completely finish transform and quantization processes for a 4:2:0 macroblock in 228 clock cycles and the achieved throughput is 445Msamples/s at 250MHz operating frequency while the area overhead is very small, 147755μm2 (approximate 15KGates), with the 130nm TSMC CMOS technology.

FAST ALGORITHM ANALYSIS AND BIT-SERIAL ARCHITECTURE DESIGN FOR SUB-PIXEL MOTION ESTIMATION IN H.264

The sub-pixel motion estimation (SME), together with the interpolation of reference frames, is a computationally extensive part of the H.264 encoder that increases the memory requirement 16-times for each reference frame. Due to the huge computational complexity and memory requirement of the H.264 SME, its hardware architecture design is an important issue especially in high resolution or low power applications. To solve the above difficulties, we propose several optimization techniques in both algorithm and architecture levels. In the algorithm level, we propose a parabolic based algorithm for SME with quarter-pixel accuracy which reduces the computational budget by 94.35% and the memory access requirement by 98.5% in comparison to the standard interpolate and search method. In addition, a fast version of the proposed algorithm is presented that reduces the computational budget 46.28% further while maintaining the video quality. In the architecture level, we propose a novel bit-serial architecture for our algorithm. Due to advantages of the bit-serial architecture, it has a low gate count, high speed operation frequency, low density interconnection, and a reduced number of I/O pins. Also, several optimization techniques including the sum of absolute differences truncation, source sharing exploiting and power saving techniques are applied to the proposed architecture which reduce power consumption and area. Our design can save between 57.71–90.01% of area cost and improves the macroblock (MB) processing speed between 1.7–8.44 times when compared to previous designs. Implementation results show that our design can support real time HD1080 format with 20.3 k gate counts at the operation frequency of 144.9 MHz.

A lightweight adaptive compression scheme for energy-efficient mobile-to-mobile file sharing applications

We propose an energy efficient adaptive scheme for mobile-to-mobile file sharing applications. The proposed scheme monitors the signal strength level during the file transfer process and compresses data blocks on-the-fly only whenever energy reduction gain is expected. The proposed scheme exploits the trade-off between spending energy to compress a file and transmit less data versus spending energy sending the file uncompressed and, thus, without additional computations before transmission. By applying data compression, the intended information is sent with lower number of bits and, thus, less transmission energy. However, the computational as well as memory access requirements of compression algorithms could consume more energy than simply transmitting data uncompressed. Moreover, if the transmission rate over the wireless medium is high then the need for compression might be reduced or even eliminated as data is transferred efficiently within a limited amount of time. We evaluate and optimize the performance of the proposed adaptive compression scheme using experimental measurements in different scenarios and as a function of various parameters. Energy consumption results demonstrate that the proposed scheme achieves notable energy reduction gains when compared to other traditional approaches. Moreover, we derive an empirical energy model that analytically quantifies the energy consumed during data transmission as a function of the signal strength level and during data compression as a function of the data size. The derived empirical model is then used to obtain energy consumption results for file sharing over multihop scenarios.

Performance Comparison of Graphics Processors to Reconfigurable Logic: A Case Study

A systematic approach to the comparison of the graphics processor (GPU) and reconfigurable logic is defined in terms of three throughput drivers. The approach is applied to five case study algorithms, characterized by their arithmetic complexity, memory access requirements, and data dependence, and two target devices: the nVidia GeForce 7900 GTX GPU and a Xilinx Virtex-4 field programmable gate array (FPGA). Two orders of magnitude speedup, over a general-purpose processor, is observed for each device for arithmetic intensive algorithms. An FPGA is superior, over a GPU, for algorithms requiring large numbers of regular memory accesses, while the GPU is superior for algorithms with variable data reuse. In the presence of data dependence, the implementation of a customized data path in an FPGA exceeds GPU performance by up to eight times. The trends of the analysis to newer and future technologies are analyzed.

Implementation and Optimization of cGA+LS to solve Capacitated VRP over Cell/B.E.

This paper presents a case study to illustrate the design and implementation of cellular Genetic Algorithm (cGA) with Local Search (LS) to solve Capacitated Vehicle Routing Problem (CVRP) over Cell Broadband Engine (Cell BE). Cell BE is a heterogeneous, distributed memory multicore processor architecture for multimedia applications with regular memory access requirements. It has one 64-bit Power Processing Element (PPE) that acts as the main processor and 8 Synergistic Processing Elements (SPEs) with only 256 KB of local memory, each for instructions and data. GAs on the other hand use population based search techniques. Such techniques usually have large memory requirements and show non-uniform memory access patterns. These properties of GAs make their implementation over Cell BE even more challenging. In order to take maximum advantage of the hardware, we propose an asynchronous approach to implement cGA+LS over Cell BE. In this paper, we discuss the implementation and optimization of the proposed method in detail. We compare the proposed method with other state-of-theart CVRP solvers and synchronous implementation of cGA+LS over Cell BE. We solve existing benchmark problems and achieve considerable speedups. We extend the work further to solve extremely large instances of CVRP compared to ones present in the CVRP literature, and get acceptable results in a reasonable amount of time.

Analysis and Hardware Architecture Design of Global Motion Estimation

Global motion estimation and compensation (GME/GMC) is an important video processing technique and has been applied to many applications including video segmentation, sprite/mosaic generation, and video coding. In MPEG-4 Advanced Simple Profile (ASP), GME/GMC is adopted to compensate camera motions. Since GME is important, many GME algorithms have been proposed. These algorithms have two common characteristics, huge computation complexity and ultra large memory bandwidth. Hence for realtime applications, a hardware accelerator of GME is required. However, there are many hardware design challenges of GME like irregular memory access and huge memory bandwidth, and only few hardware architectures have been proposed. In this paper, we first analyzed three typical algorithms of GME, and a fast GME algorithm is proposed. By using temporal prediction and skipping the redundant computation, 91% memory bandwidth and 80% iterations are saved, while the performance is kept, compared to Gradient Descent in MPEG-4 Verification Model. Based on our proposed algorithm, a hardware architecture of GME is also presented. A new scheduling, Reference-Based Scheduling, is developed to solve the irregular memory access problem. An interleaved memory arrangement is applied to satisfy the memory access requirement of interpolation. The total gate count of hardware implementation is 131 K with Artisan 0.18 um cell library, and the internal memory size is about 7.9 Kb. Its processing ability is MPEG-4 ASP@L3, which is 352×288 with 30 fps, at 30 MHz.

Multiple-input turbo code for secure data aggregation and source-channel coding in wireless sensor networks

In wireless sensor networks, the data of neighbouring sensor nodes are often highly correlated due to that they have overlapping sensing areas. To exploit the data correlation for reducing the amount of data while transmitting data from sensor nodes to their base station, this paper introduces Multiple-Input Turbo (MIT) code to implement jointly source coding channel coding and data aggregation for wireless systems, in particular, wireless sensor networks. MIT code has multiple input sequences and employs partial interleaving to reduce the memory size and access requirements. This paper also addresses how MIT code can be used to implement security together with data aggregation and source-channel coding. The simulation results show that the Bit Error Rate (BER) performance of MIT code is slightly better than turbo codes, even if MIT code implements partial interleaving and has multiple inputs.

Algorithmic and architectural co-design for integer motion estimation of AVS

The video part of A VS has been finalized, in order to enhance coding performance. AVS video standard adopts some new features for motion estimation, such as variable block size search, multiple reference frames, and motion vector prediction. However, the better performance comes at the price of high computational complexity, data dependence and memory access requirement. These new features also make the hardware implementation more difficult, especially for real-time applications. In this paper, we firstly propose an integer motion estimation algorithm from hardware-oriented viewpoint. Experimental results show that the proposed algorithm has almost the same performance as the reference software of AVS in SDTV applications. Then the corresponding VLSI architecture is presented. The VLSI architecture has been described in Verilog HDL and synthesized using 0.18 mum Artisan CMOS cells library. The circuit totally costs about 400 K equivalent logic gates. At 108 MHz working frequency, the circuit can meet the real-time requirement for SDTV (720times576, 25 fps) applications, with the search area of 192times192. The co-design obtains better tradeoff between performance and gate-count

Analysis and architecture design of an HDTV720p 30 frames/s H.264/AVC encoder

H.264/AVC significantly outperforms previous video coding standards with many new coding tools. However, the better performance comes at the price of the extraordinarily huge computational complexity and memory access requirement, which makes it difficult to design a hardwired encoder for real-time applications. In addition, due to the complex, sequential, and highly data-dependent characteristics of the essential algorithms in H.264/AVC, both the pipelining and the parallel processing techniques are constrained to be employed. The hardware utilization and throughput are also decreased because of the block/MB/frame-level reconstruction loops. In this paper, we describe our techniques to design the H.264/AVC video encoder for HDTV applications. On the system design level, in consideration of the characteristics of the key components and the reconstruction loops, the four-stage macroblock pipelined system architecture is first proposed with an efficient scheduling and memory hierarchy. On the module design level, the design considerations of the significant modules are addressed followed by the hardware architectures, including low-bandwidth integer motion estimation, parallel fractional motion estimation, reconfigurable intrapredictor generator, dual-buffer block-pipelined entropy coder, and deblocking filter. With these techniques, the prototype chip of the efficient H.264/AVC encoder is implemented with 922.8 K logic gates and 34.72-KB SRAM at 108-MHz operation frequency.

A power-efficient TCAM architecture for network forwarding tables

Stringent memory access and search speed requirements are two of the main bottlenecks in wire speed processing. Most viable search engines are implemented in content addressable memories (CAMs). CAMs have high operational speed advantage over other memory search algorithms. However, this performance advantage comes with a price of higher silicon area, and higher power consumption. Ternary CAMs (TCAM) are widely used for route lookup operations in networking applications. IP address prefix length distribution in the core routers shows a similar characteristic such that the prefixes with 24 or longer bits attract more than 50% of the traffic. Based on this statistical observation, we propose a TCAM architecture that can be used on top of the previously reported power saving techniques and it offers additional 30% reduction in power consumption. Furthermore, we model the dynamic power consumption in TCAM circuits due match, mismatch and don’t care activities.

An efficient quality-aware memory controller for multimedia platform SoC

The ongoing advancements in VLSI technology allow system-on-a-chip (SoC) design to integrate heterogeneous control and computing functions into a single chip. On the other hand, the pressures of area and cost lead to the requirement for a single, shared off-chip DRAM memory subsystem. To satisfy different memory access requirements for latency and bandwidth of these heterogeneous functions to this kind of DRAM memory subsystem, a quality-aware memory controller is important. This paper presents an efficient multilayer, quality-aware memory controller that contains well-partitioned functionality layers to achieve high DRAM utilization while still meet different requirements for bandwidth and latency. Layer 0, also called memory interface socket, is a configurable, programmable, and high-efficient SDRAM controller for designers to rapidly integrate SDRAM subsystem into their designs. Together with Layer 1 quality-aware scheduler, the memory controller also has the capability to provide quality-of-service guarantees including minimum access latencies and fine-grained bandwidth allocation for heterogeneous control and computing functional units in SoC designs. Moreover, Layer 2 built-in address generator designed for multimedia processing units can effectively reduce the address bus traffic and therefore further increase the efficiency of on-chip communication. Experimental results of a digital set-top-box emulation system show that the access latency of the latency-sensitive data flows can be effectively reduced by 37%-65% and the memory bandwidths can be precisely allocated to bandwidth-sensitive data flows with a high degree of control.

A fast digital radon transform—an efficient means for evaluating the hough transform

A fast digital Radon transform based on recursively defined digital straight lines is described, which has the sequential complexity of 0(N' log N) additions for an N x N image. This transform can be used to evaluate the Hough transform to detect straight lines in a digital image. Whilst a parallel implementation of the Hough transform algorithm is difficult because of global memory access requirements, the fast digital Radon transform is vectorizable and therefore well suited for parallel computation. The structure of the fast algorithm is shown to be quite similar to the FFT algorithm for decimation in frequency. It is demonstrated that even for sequential computation the fast Radon transform is an attractive alternative to the classical Hough transform algorithm.

A fast digital Radon transform—An efficient means for evaluating the Hough transform

A fast digital Radon transform based on recursively defined digital straight lines is described, which has the sequential complexity of N 2 log N additions for an N × N image. This transform can be used to evaluate the Hough transform to detect straight lines in a digital image. Whilst a parallel implementation of the Hough transform algorithm is difficult because of global memory access requirements, the fast digital Radon transform is vectorizable and therefore well suited for parallel computation. The structure of the fast algorithm is shown to be quite similar to the FFT algorithm for decimation in frequency. It is demonstrated that even for sequential computation the fast Radon transform is an attractive alternative to the classical Hough transform algorithm.

Access and Alignment of Data in an Array Processor

This paper discusses the design of a primary memory system for an array processor which allows parallel, conflict-free access to various slices of data (e.g., rows, columns, diagonals, etc.), and subsequent alignment of these data for processing. Memory access requirements for an array processor are discussed in general terms and a set of common requirements are defined. The ability to meet these requirements is shown to depend on the number of independent memory units and on the mapping of the data in these memories. Next, the need to align these data for processing is demonstrated and various alignment requirements are defined. Hardware which can perform this alignment function is discussed, e.g., permutation, indexing, switching or sorting networks, and a network (the omega network) based on Stone's shuffle-exchange operation [1] is presented. Construction of this network is described and many of its useful properties are proven. Finally, as an example of these ideas, an array processor is shown which allows conflict-free access and alignment of rows, columns, diagonals, backward diagonals, and square blocks in row or column major order, as well as certain other special operations.