Memory Access Operations Research Articles

Magnetic Skyrmion as a Spintronic Deep Learning Spiking Neuron Processor

Deep spiking neural networks (SNNs) have emerged as one of the popular architectures in complex pattern recognition and classification tasks that can be enabled by low-power neuromorphic hardware. However, hardware implementation of such algorithms using conventional CMOS devices is area expensive and energy inefficient. This is owing to the fundamental mismatch between the underlying neuromophic computations and the CMOS transistors along with energy consumption involved in synaptic memory-access operations. Hence, there is a need for novel “neuro-mimetic” devices offering a direct mapping to synaptic and neuronal functionalities together with the possibility of providing in situ synaptic storage. Magnetic skyrmions have recently been proposed as a promising alternative for next-generation information carrier due to remarkably high stability, ultra-low depinning current density, and extremely compact size. In this paper, the design of skyrmion-based devices to emulate biological synapses and neurons is explored, and skyrmionic synapse-based crossbar architectures driving skyrmionic neurons are proposed. We perform a systematic device-circuit-architecture co-design for digit recognition with the MNIST handwritten digits dataset to evaluate the feasibility of our proposal. The device-to-system simulations indicate that the proposed skyrmion-based devices in deep SNNs can potentially achieve two orders of magnitude improvement in energy consumption over an optimized CMOS implementation at a 45 nm technology node.

Type Information Elimination from Objects on Architectures with Tagged Pointers Support

Implementations of object-oriented programming languages associate type information with each object to perform various runtime tasks such as dynamic dispatch, type introspection, and reflection. A common means of storing such relation is by inserting a pointer to the associated type information into every object. Such an approach, however, introduces memory and performance overheads when compared with non-object-oriented languages. Recent 64-bit computer architectures have added support for tagged pointers by ignoring a number of bits - tag - of memory addresses during memory access operations and utilize them for other purposes; mainly security. This paper presents the first investigation into how this hardware support can be exploited by a Java Virtual Machine to remove type information from objects. Moreover, we propose novel hardware extensions to the address generation and load-store units to achieve low-overhead type information retrieval and tagged object pointers compression-decompression. The evaluation has been conducted after integrating the Maxine VM and the ZSim microarchitectural simulator. The results, across all the DaCapo benchmark suite, pseudo-SPECjbb2005, SLAMBench and GraphChi-PR executed to completion, show up to 26 and 10 percent geometric mean heap space savings, up to 50 and 12 percent geometric mean dynamic DRAM energy reduction, and up to 49 and 3 percent geometric mean execution time reduction with no significant performance regressions.

Application Productivity and Performance Evaluation of Transparent Locality-aware One-sided Communication Primitives

Nowadays, the individual nodes of a distributed parallel computer consist of multi- or many-core processors allowing to execute more than one process per node. The large difference in communication speed within a node through shared memory, versus across nodes through the network interconnect, requires to use locality-aware communication schemes for any efficient distributed application. However, writing an efficient locality-aware MPI code is complex and error-prone, because the developer has to use very different APIs for communication operations within and across nodes, respectively, and manage inter-process synchronization. In this paper, we analyze and enhance a recent one-sided communication model, namely DART-MPI, which is implemented on top of MPI-3. In this runtime system, the complexities of handling locality-awareness of MPI memory access operations, either remote or local, and the related synchronization calls are hidden inside the related DART-MPI interfaces resulting in concise code and improved application and developer productivity. We have carried out in-depth evaluation of our DART-MPI system. Foremost, a micro benchmark is conducted to help understanding the prime performance overhead of implementing APIs in DART-MPI system, which is small and becomes negligible with the growing message sizes. We then compare the performance of DART-MPI and flat MPI without locality awareness, in particular blocking and non-blocking memory operations, using a realistic scientific application on a large-scale supercomputer. The comparison demonstrates that in most cases the DART-MPI version of this application shows better performance than the flat MPI version. Further, we compare the DART-MPI version to a functionally equivalent MPI version, which thus includes code to deal with data-locality, and show that DART-MPI realizes almost the full potential of highly optimized MPI while maintaining high productivity for non-expert programmers.

고해상도 영상의 효과적인 처리를 위한 블록 버퍼 기반의 저 복잡도 무손실 프레임 메모리 압축 방법

본 논문에서는 고해상도 영상의 효과적인 처리를 위한 블록 버퍼 기반의 저 복잡도 무손실 프레임 메모리 (frame memory) 압축 방법을 제안한다. 제안하는 압축 방법은 공간적 상관도를 제거하기 위하여 블록단위 MHT (modified Hadamard transform)를 사용하고, 엔트로피 부호화를 위하여 AGR (adaptive Golomb-Rice) 부호화 기법을 적용하여 저 복잡도 무손실 압축 및 효과적인 하드웨어 구현을 달성한다. MHT는 가산기와 1비트 오른쪽 시프트(1-bit right shift) 연산만으로 구성되어 있고, AGR은 별도의 메모리 공간 및 메모리 접근 동작(memory access operation)을 포함하지 않아 저 복잡도 구현이 용이하다. 기존의 저 복잡도 무손실 압축 방법과 비교하여 제안한 알고리즘은 압축률 측면에서 우수한 성능을 나타내고, 기존 코덱(codec)의 구조를 크게 수정하지 않으면서 화질의 열화없이 하드웨어 장치에 적용될 수 있음을 다양한 영상에 대한 실험 및 복잡도 분석을 통해 보인다. 또한 제안한 방법은 메모리 접근 동작을 필요로 하지 않아 하드웨어 구현을 위한 비용을 최소화 할 수 있어, Fill HD급 이상의 고해상도 영상을 효과적으로 처리하는데 유용하다. This study addresses a low complexity and lossless frame memory compression algorithm based on block-buffer structure for efficient high resolution video processing. Our study utilizes the block-based MHT (modified Hadamard transform) for spatial decorrelation and AGR (adaptive Golomb-Rice) coding as an entropy encoding stage to achieve lossless image compression with low complexity and efficient hardware implementation. The MHT contains only adders and 1-bit shift operators. As a result of AGR not requiring additional memory space and memory access operations, AGR is effective for low complexity development. Comprehensive experiments and computational complexity analysis demonstrate that the proposed algorithm accomplishes superior compression performance relative to existing methods, and can be applied to hardware devices without image quality degradation as well as negligible modification of the existing codec structure. Moreover, the proposed method does not require the memory access operation, and thus it can reduce costs for hardware implementation and can be useful for processing high resolution video over Full HD.

A Compiler Approach for Exploiting Partial SIMD Parallelism

Existing vectorization techniques are ineffective for loops that exhibit little loop-level parallelism but some limited superword-level parallelism (SLP). We show that effectively vectorizing such loops requires partial vector operations to be executed correctly and efficiently, where the degree of partial SIMD parallelism is smaller than the SIMD datapath width. We present a simple yet effective SLP compiler technique called P aver (PArtial VEctorizeR), formulated and implemented in LLVM as a generalization of the traditional SLP algorithm, to optimize such partially vectorizable loops. The key idea is to maximize SIMD utilization by widening vector instructions used while minimizing the overheads caused by memory access, packing/unpacking, and/or masking operations, without introducing new memory errors or new numeric exceptions. For a set of 9 C/C++/Fortran applications with partial SIMD parallelism, P aver achieves significantly better kernel and whole-program speedups than LLVM on both Intel’s AVX and ARM’s NEON.

A Rapid Prototyping Matlab Based Design Tool of Wireless Sensor Nodes for Healthcare Applications

Remote patient monitoring enables medical facilities and personnel to monitor patients outside of conventional clinical settings. This technology is greatly affected by the available energy sources. The limited energy supply is the bottleneck for measurement, data transmission, network connection and lifetime. Thus, efficient power consumption estimation in the early stage of the design would give the user an insight on its feasibility within medical constraints. In this paper, a power-oriented Matlab based design tool is proposed. It will help the user to make an energy aware design. In fact, it will enable him to determine the power consumption of each node based on a set of selected components, the daily routine of the patient and many other factors. It will also allow him to test multiple configurations prior to the physical implementation. This will minimize the time and financial impact of any modification. Furthermore, it will provide guidance to properly adapt the design within the requirements of the application: Choosing components, energy sources, etc. A validation is proposed via a physical implementation in order to compare the results obtained through simulation with practical measurements. Future works aim to take into account memory access operations, include several sensors operating within a network, and adapt the tool to other applications (smart buildings, environmental monitoring, etc.).

Modular vector processor architecture targeting at data-level parallelism

Taking advantage of DLP (Data-Level Parallelism) is indispensable in most data streaming and multimedia applications. Several architectures have been proposed to improve both the performance and energy consumption for such applications. Superscalar and VLIW (Very Long Instruction Word) processors along with SIMD (Single-Instruction Multiple-Data) and vector processor (VP) accelerators, are among the available options for designers to accomplish their desired requirements. We present an innovative architecture for a VP which separates the path for performing data shuffle and memory-indexed accesses from the data path for executing other vector instructions that access the memory. This separation speeds up the most common memory access operations by avoiding extra delays and unnecessary stalls. In our lane-based VP design, each vector lane uses its own private memory to avoid any stalls during memory access instructions. The proposed VP, which is developed in VHDL and prototyped on an FPGA, serves as a coprocessor for one or more scalar cores. Benchmarking shows that our VP can achieve very high performance. For example, it achieves a larger than 1500-fold speedup in the color space converting benchmark compared to running the code on a scalar core. The inclusion of distributed data shuffle engines across vector lanes has a spectacular impact on the execution time, primarily for applications like FFT (Fast-Fourier Transform) that require large amounts of data shuffling. Compared to running the benchmark on a VP without the shuffle engines, the speedup is 5.92 and 7.33 for the 64-point FFT without and with compiler optimization, respectively. Compared to runs on the scalar core, the achieved speedups for this benchmark are 52.07 and 110.45 without and with compiler optimization, respectively.

CRANarch: A feasible processor micro-architecture for Cloud Radio Access Network

Cloud Radio Access Network (C-RAN) becomes a promising infrastructure, which can improve hardware resource utilization of traditional Radio Access Network (RAN). For C-RAN, data centers are essential hardware platform, and these data centers are universally equipped with general commercial multi-core processors which are not designed for wireless communication protocols dedicatedly. In this paper, firstly, we evaluate performance bottlenecks of general multi-core processors with current dominant micro-architecture via typical wireless communication protocol. The results show that the dominant micro-architecture mismatches to demands of wireless communication protocols, which makes dominant general multi-core processor is inefficient when used in this application field. Secondly, we analyze the essential micro-architectural level reasons for the inefficiency in detail. A typical characteristic of wireless communication protocols is there are lots of random memory accesses in a large memory address space, which results in high miss ratio of on-chip cache hierarchies. The frequent on-chip cache misses result in amounts of off-chip memory access operations, which incurs longer memory access latency as a dominant factor to degrade overall performance. Based on the results, we identify key micro-architectural characteristics that meet demands of wireless communication protocols. Finally, we propose a feasible micro-architecture of multi-core processor for C-RAN, called as CRANarch, the performance results show its improved hardware utilization efficiency and power efficiency when used in C-RAN data centers.

Data reuse-based fast subpixel motion estimation for high efficiency video coding

A data reuse-based fast subpixel motion estimation (SME) method for high efficiency video coding (HEVC) is proposed. Since SME is one of the most computation-intensive tools in the encoder process, conventional research on SME focused on the reduction of the computational complexity. The applied data-reuse architecture for the design of fast SME substantially reduces computational complexity at the cost of a reasonable increase in memory bandwidth. The core of the proposed data-reuse method is the replacement of redundant computations in SME with the memory access operations of previously computed values. The proposed method was tested in the latest video coding standard, HEVC, with experimental results showing a reduction in operational complexity of ∼64.14%, and a reduction in encoding time of ∼56.13%, compared to the SME in the HEVC reference encoder.

A simple wear leveling algorithm for NOR type solid storage device

The role and importance of solid storage devices (SSD) is rapidly increasing for the purpose of data storage. The SSDs are rapidly replacing the old fashioned and traditional magnetic storage medium. Few factors responsible for this metamorphic turnaround are due to the better performance and low power requirement of SSDs. But, as with every pros there are some associated cons. One limiting factor of SSDs in replacing traditional magnetic storage media is its low endurance. These solid state devices can be re-programmed for a limited number of times. Unlike, magnetic storage media, the SSDs can be re-programmed for a limited number of times. Internally, SSDs are organized either in bytes or blocks. Generally, for memory access operations, either the byte or blocks are used. With each write operation, the byte gets worn out and its lifetime decreases. To guard this limiting factor of SSD, wear leveling mechanism is used. Wear leveling mechanism is provided as a feature in flash type SSDs, which evenly distributes the write operation throughout the flash memory and prevents the early wear out of memory. The existing wear leveling mechanism is limited only to flash type SSDs. In this paper, we propose a wear leveling algorithm for SSD and precisely NOR type SSD. NAND types SSDs are well equipped with algorithms to enhance their life and reliability. The algorithm proposed will provide a mechanism that will enhance the life, endurance and reliability of SSD of NOR type.

Reinstating higher order properties of a study list by retrieving a list item

In two experiments, we looked at the role of higher order list properties in episodic recall. A probabilistic paired-associate paradigm was used in which each cue was repeatedly paired with two different targets. This paradigm permitted us to cue for a target that had been studied with that cue in the last list, or to cue for either of the two targets that had been repeatedly paired with that cue, although neither the cue nor either of its two targets had been studied in the last list. In Experiment 1, the higher order property was whether all of the targets in a given list were animal names or vegetable names. In Experiment 2, the higher order property was whether all of the pairs in a list were associatively related or unrelated. The assumption was that if participants were using these higher order properties when they retrieved a target that had been studied in the last list, they would also use these properties when recalling in response to a cue that had been studied in other lists but not in the most recent list. The results supported the use of both kinds of higher order properties in episodic access. They also showed that these higher order properties were reinstated by retrieving a target, and were then used in the next memory access operation. The questions of why the retrieval of a target would reinstate a higher order list property and how these very different higher order list properties aid in episodic access were also discussed.

Compact modeling of CRS devices based on ECM cells for memory, logic and neuromorphic applications

Dynamic physics-based models of resistive switching devices are of great interest for the realization of complex circuits required for memory, logic and neuromorphic applications. Here, we apply such a model of an electrochemical metallization (ECM) cell to complementary resistive switches (CRSs), which are favorable devices to realize ultra-dense passive crossbar arrays. Since a CRS consists of two resistive switching devices, it is straightforward to apply the dynamic ECM model for CRS simulation with MATLAB and SPICE, enabling study of the device behavior in terms of sweep rate and series resistance variations. Furthermore, typical memory access operations as well as basic implication logic operations can be analyzed, revealing requirements for proper spike and level read operations. This basic understanding facilitates applications of massively parallel computing paradigms required for neuromorphic applications.

Memory Reliability Improvement Based on Maximized Error-Correcting Codes

Error-correcting codes (ECC) offer an efficient way to improve the reliability and yield of memory subsystems. ECC-based protection is usually provided on a memory word basis such that the number of data-bits in a codeword corresponds to the amount of information that can be transferred during a single memory access operation. Consequently, the codeword length is not the maximum allowed by a certain check-bit number since the number of data-bits is constrained by the width of the memory data interface. This work investigates the additional error correction opportunities offered by the absence of a perfect match between the numbers of data-bits and check-bits in some widespread ECCs. A method is proposed for the selection of multi-bit errors that can be additionally corrected with a minimal impact on ECC decoder latency. These methods were applied to single-bit error correction (SEC) codes and double-bit error correction (DEC) codes. Reliability improvements are evaluated for memories in which all errors affecting the same number of bits in a codeword are independent and identically distributed. It is shown that the application of the proposed methods to conventional DEC codes can improve the mean-time-to-failure (MTTF) of memories with up to 30 %. Maximized versions of the DEC codes are also proposed in which all adjacent triple-bit errors become correctable without affecting the maximum number of triple-bit errors that can be made correctable.

Loop scheduling with memory access reduction subject to register constraints for DSP applications

SUMMARYMemory accesses introduce big‐time overhead and power consumption because of the performance gap between processors and main memory. This paper describes and evaluates a technique, loop scheduling with memory access reduction (LSMAR), that replaces hidden redundant load operations with register operations in loop kernels and performs partial scheduling for newly generated register operations subject to register constraints. By exploiting data dependence of memory access operations, the LSMAR technique can effectively reduce the number of memory accesses of loop kernels, thereby improving timing performance. The technique has been implemented into the Trimaran compiler and evaluated using a set of benchmarks from DSPstone and MiBench on the cycle‐accurate simulator of the Trimaran infrastructure. The experimental results show that when the LSMAR technique is applied, the number of memory accesses can be reduced by 18.47% on average over the benchmarks when it is not applied. The measurements also indicate that the optimizations only lead to an average 1.41% increase in code size. With such small code size expansion, the technique is more suitable for embedded systems compared with prior work.Copyright © 2013 John Wiley & Sons, Ltd.

실사기반 디지털 홀로그래픽 비디오의 실시간 생성을 위한 하드웨어의 설계

본 논문에서는 고속으로 홀로그램을 생성할 수 있는 하드웨어의 구조를 제안하고 이를 구현하였다. 제안한 하드웨어는 홀로그램 평면의 행 단위로 병렬 연산을 수행할 수 있는 구조를 가지고 있고, 한 행의 각 홀로그램 화소들이 독립적으로 연산될 수 있는 알고리즘을 이용하였다. 이러한 연산 방법을 통해서 홀로그램 생성 하드웨어서 가장 문제가 되는 메모리 접근량을 대폭 감소시킴으로써 하드웨어 처리능력의 실시간성을 대폭 향상시켰다. 제안한 하드웨어는 입력 인터페이스, 초기 파라미터 연산기, 홀로그램 화소 연산기, 라인 버퍼, 그리고 메모리 제어기로 구성된다. 제안한 하드웨어는 기존의 하드웨어와 동일한 처리능력을 가지면서도 메모리 접근횟수는 약 20,000배 감소시킬 수 있었다. 구현한 하드웨어는 198MHz에서 안정적으로 동작할 수 있었고, 168,960개의 LUT, 153,944개의 레지스터, 그리고 19,212개의 DSP 블록을 사용하였다.

Hardware architecture of high-performance digital hologram generator on the basis of a pixel-by-pixel calculation scheme

In this paper we propose a hardware architecture for high-speed computer-generated hologram generation that significantly reduces the number of memory access times to avoid the bottleneck in the memory access operation. For this, we use three main schemes. The first is pixel-by-pixel calculation, rather than light source-by-source calculation. The second is a parallel calculation scheme extracted by modifying the previous recursive calculation scheme. The last scheme is a fully pipelined calculation scheme and exactly structured timing scheduling, achieved by adjusting the hardware. The proposed hardware is structured to calculate a row of a computer-generated hologram in parallel and each hologram pixel in a row is calculated independently. It consists of and input interface, an initial parameter calculator, hologram pixel calculators, a line buffer, and a memory controller. The implemented hardware to calculate a row of a 1920×1080 computer-generated hologram in parallel uses 168,960 lookup tables, 153,944 registers, and 19,212 digital signal processing blocks in an Altera field programmable gate array environment. It can stably operate at 198 MHz. Because of three schemes, external memory bandwidth is reduced to approximately 1/20,000 of the previous ones at the same calculation speed.

Automatic analysis of DMA races using model checking and k-induction

Modern multicore processors, such as the Cell Broadband Engine, achieve high performance by equipping accelerator cores with small “scratch-pad” memories. The price for increased performance is higher programming complexity – the programmer must manually orchestrate data movement using direct memory access (DMA) operations. Programming using asynchronous DMA operations is error-prone, and DMA races can lead to nondeterministic bugs which are hard to reproduce and fix. We present a method for DMA race analysis in C programs. Our method works by automatically instrumenting a program with assertions modeling the semantics of a memory flow controller. The instrumented program can then be analyzed using state-of-the-art software model checkers. We show that bounded model checking is effective for detecting DMA races in buggy programs. To enable automatic verification of the correctness of instrumented programs, we present a new formulation of k-induction geared towards software, as a proof rule operating on loops. Our techniques are implemented as a tool, Scratch, which we apply to a large set of programs supplied with the IBM Cell SDK, in which we discover a previously unknown bug. Our experimental results indicate that our k-induction method performs extremely well on this problem class. To our knowledge, this marks both the first application of k-induction to software verification, and the first example of software model checking in the context of heterogeneous multicore processors.

Exploring Online Synthesis for CGRAs with Specialized Operator Sets

The design of energy-efficient systems has become a major challenge for engineers over the last decade. One way to save energy is to spread out computations in space rather than in time (as traditional processors do). Unfortunately, this requires to design specialized hardware for each application. Also, the nonrecurring expenses for the manufacturing of chips continuously grow. Implementing the computations on FPGAs and CGRAs solves this dilemma, as the non recurring expenses are shared between many different applications. We believe that online synthesis that takes place during the execution of an application is one way to broaden the applicability of reconfigurable architectures as no expert knowledge of synthesis and technologies is required. In this paper, we give a detailed analysis of the amount and specialization of resources in a CGRA that are required to grant a significant speedup of Java bytecode. In fact, we show that even a relatively small number of specialized reconfigurable resources is sufficient to speed up applications considerably. Particularly, we look at the number of dedicated multipliers and dividers. Also, we discuss the required number of concurrent memory access operations inside the CGRA. Again, it shows that two concurrent memory access operations are sufficient for almost all applications.

Computational Steering and Parallel Online Monitoring Using RMA through the HDF5 DSM Virtual File Driver

Abstract As systems provide more resources and host an indefinitely growing number of cores, the amount of data produced by simulation codes is steadily increasing, creating a bottleneck at the point where the data must be transferred to post processing software. One solution is to avoid the use of a file system altogether and couple post processing software directly to the simulation using an interface common to both sides of the transfer. HDF5, the widely known IO library, offers a modular mapping of file contents to storage, allowing the user to use different methods (drivers) for reading and writing data. These drivers are organized in a Virtual File Layer (VFL) so that the user can easily switch between – and if necessary – extend them. In order to be able to visualize and analyze data in-situ, we developed a parallel virtual file driver called the DSM driver, which allows the transfer of data in parallel between two different codes using only the HDF5 API; this driver has now been extended to support remote memory access operations. Whilst the original implementation allows one to post-process data in-situ, we present in this paper extensions to the driver that provide the ability to couple parallel applications bidirectionally. We use this to perform computational steering of simulations. Commands and data are sent back to the simulation using either the driver layer itself (primarily commands) or the HDF5 layer via the DSM driver (datasets). The use of HDF5 datasets for transfer between codes makes true parallel coupling possible, even when the data models of the codes are not directly compatible. The steering interface presented here is shown implemented within ParaView, the parallel visualization application, but the API is generic and in fact any applications that make use of HDF5 may be connected using the driver.

A Real-Time FPGA-Based 20 000-Word Speech Recognizer With Optimized DRAM Access

A real-time hardware-based large vocabulary speech recognizer requires high memory bandwidth. We have developed a field-programmable-gate-array (FPGA)-based 20 000-word speech recognizer utilizing efficient dynamic random access memory (DRAM) access. This system contains all the functional blocks for hidden-Markov-model-based speaker-independent continuous speech recognition: feature extraction, emission probability computation, and intraword and interword Viterbi beam search. The feature extraction is conducted in software on a soft-core-based CPU, while the other functional units are implemented using parallel and pipelined hardware blocks. In order to reduce the number of memory access operations, we used several techniques such as bitwidth reduction of the Gaussian parameters, multiframe computation of the emission probability, and two-stage language model pruning. We also employ a customized DRAM controller that supports various access patterns optimized for each functional unit of the speech recognizer. The speech recognition hardware was synthesized for the Virtex-4 FPGA, and it operates at 100 MHz. The experimental result on Nov 92 20 k test set shows that the developed system runs 1.52 and 1.39 times faster than real time using the bigram and trigram language models, respectively.